KR19980019808A - CMOS semiconductor device and manufacturing method thereof - Google Patents
CMOS semiconductor device and manufacturing method thereof Download PDFInfo
- Publication number
- KR19980019808A KR19980019808A KR1019960038051A KR19960038051A KR19980019808A KR 19980019808 A KR19980019808 A KR 19980019808A KR 1019960038051 A KR1019960038051 A KR 1019960038051A KR 19960038051 A KR19960038051 A KR 19960038051A KR 19980019808 A KR19980019808 A KR 19980019808A
- Authority
- KR
- South Korea
- Prior art keywords
- polysilicon layer
- lto
- conductivity type
- forming
- region
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823835—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은, 제1 및 제2 전도형의 웰이 표면 근방에 형성되어 있고 소자분리 산화막, 게이트 산화막 및 제1 전도형의 제1 폴리실리콘층이 적층되어 있는 반도체 기판 상에 질화막을 침적한 후 게이트 폴리 형성 부분에 위치하는 질화막을 제거하고 그 측벽에 LTO 스페이서를 형성하는 단계; 상기 질화막의 개구부에 제1 전도형의 제2 폴리실리콘층과 살리사이드층을 순차적으로 적층하여 채워 넣고 상기 질화막을 제거하는 단계; 하나의 포토레지스트 패턴을 사용하여 각 웰에 주입된 불순물과 다른 전도형의 불순물을 웰의 표면 근방에 고농도로 주입하고 상기 LTO 스페이서 제거후 다시 같은 전도형의 불순물을 저농도로 주입하여 LDD를 갖는 소스/드레인 영역을 형성하는 단계; 및 상기 결과물 상에 LTO를 침적한 후 이를 선택적으로 식각하여 제2 폴리실리콘층과 살리사이드 측벽에 LTO 스페이서를 형성함과 동시에 LTO를 과도 식각하여 하부의 제1 폴리실리콘층을 제거하는 단계에 의해 제조되는 씨모스 반도체 장치를 제공한다.According to the present invention, a nitride film is deposited on a semiconductor substrate on which wells of the first and second conductivity types are formed in the vicinity of the surface and on which a device isolation oxide film, a gate oxide film, and a first polysilicon layer of the first conductivity type are stacked. Removing the nitride film positioned at the gate poly forming portion and forming an LTO spacer on a sidewall of the nitride film; Sequentially stacking and filling a second polysilicon layer and a salicide layer of a first conductivity type in the opening of the nitride film and removing the nitride film; Using a single photoresist pattern, impurities implanted in each well and other conductivity type impurities are injected at a high concentration near the surface of the well, and after removing the LTO spacer, impurities of the same conductivity type are injected again at a low concentration to have an LDD source. Forming a / drain region; And depositing LTO on the resultant and selectively etching the LTO to form LTO spacers on the sidewalls of the second polysilicon layer and the salicide, and simultaneously over-etching the LTO to remove the lower first polysilicon layer. Provided is a CMOS semiconductor device manufactured.
이러한 방법은 하나의 포토레지스트를 사용하여 LDD를 갖는 소스/드레인 영역을 형성하므로 공정이 간단하고, 이 공정에 의해 제조되는 씨모스 반도체 장치는 LDD 영역이 필드 산화막으로 구분된 소자 영역 상에 형성되는 게이트 폴리의 제1 폴리실리콘층에 의해 덮인 구조가 되므로 핫-캐리어 효과에 대한 내성을 갖는다.This method uses a single photoresist to form a source / drain region having an LDD, so the process is simple, and the CMOS semiconductor device manufactured by this process is characterized in that the LDD region is formed on a device region in which the LDD region is divided into field oxide films. The structure covered by the first polysilicon layer of the gate poly has resistance to hot-carrier effects.
Description
본 발명은 씨모스(CMOS) 반도체 장치 및 그 제조방법에 관한 것으로서, 보다 상세하게는 반도체의 직접화에 따라 커지고 있는 소자의 핫-캐리어(hot carrier)를 효과를 감소시킨 인버스 트랜지스터 엘디디(Inverse Transistor Lightly Doped Drain: ITLDD) CMOS 반도체 장치 및 이를 간단한 공정에 의해 제조할 수 있는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS semiconductor device and a method of fabricating the same, and more particularly, to an inverse transistor LED having an effect of reducing the hot carrier of a device, which is growing according to the directization of a semiconductor. Transistor Lightly Doped Drain (ITLDD) CMOS semiconductor device and a method capable of manufacturing the same by a simple process.
반도체 장치의 고직접화 경향에 따라 CMOS 소자의 경우에도 크기가 작아짐에 따라 미크론(㎛)급 채널 길이가 이미 보편화 되었고, 하프(half) 미크론급 또는 쿼터(quarter) 미크론급 크기의 채널을 갖는 CMOS 소자까지도 등장하고 있다.As the size of semiconductor devices increases, the size of semiconductor devices has become smaller, and micron (μm) channel lengths have become more common, and CMOS with half-micron or quarter-micron-sized channels has become common. Even devices have appeared.
이와 같이 채널 길이가 작아짐에 따라 CMOS 반도체 장치는, 도 1에 도시된 바와 같이 소스/드레인 영역(50)(50a)(52)(52a)과 각 게이트 폴리(40)의 제1 폴리실리콘층(42) 사이에 존재하는 과도한 불순물로 인하여 소자 구동시 핫-캐리어 효과가 발생하였다. 특히 쇼트-채널인 엔모스(NMOS) 반도체 장치는 시간의 흐름에 따라 채널 영역에 걸리는 전기장의 크기가 커져 문턱 전압이 증가하고 드레인/소스간 전류가 감소하여, 결국 소자의 특성이 저하되었다.As the channel length decreases as described above, the CMOS semiconductor device, as shown in FIG. 1, has a source / drain regions 50, 50a, 52, 52a and a first polysilicon layer of each gate poly 40 ( Excessive impurities present between 42) resulted in a hot-carrier effect when driving the device. In particular, the short-channel NMOS semiconductor device has a large electric field applied to the channel region over time, thereby increasing the threshold voltage and decreasing the drain / source current, resulting in deterioration of device characteristics.
따라서 최근에는 상기 단점을 해결한 것으로, LDD(Lightly Doped Drain), 게이트 오버랩 LDD(Gate Overlapped LDD: GOLD), ITLDD 등 여러 종류의 소자가 제안되어 사용되고 있으나, 이들 또한 그 제조 공정이 매우 복잡하다.Therefore, in order to solve the above-mentioned drawbacks, various types of devices, such as Lightly Doped Drain (LDD), Gate Overlapped LDD (GOLD), and ITLDD, have been proposed and used. However, these manufacturing processes are also very complicated.
본 발명의 목적은 간단한 공정에 의해 핫-캐리어 효과를 보다 감소시킨 씨모스(CMOS) 반도체 장치를 제공하는 데에 있다.It is an object of the present invention to provide a CMOS semiconductor device which further reduces the hot-carrier effect by a simple process.
또한 본 발명의 다른 목적은 보다 간단한 공정으로 상기 씨모스(CMOS) 반도체 장치를 제조할 수 있는 방법을 제공하는 데에 있다.Another object of the present invention is to provide a method for manufacturing the CMOS semiconductor device by a simpler process.
상기 본 발명의 목적을 달성하기 위한 씨모스(CMOS) 반도체 장치는, 필드 산화막으로 구분된 소자 영역 상에 게이트 전극에 연결된 제1 폴리실리콘층을 소스/드레인 영역의 LDD 영역이 덮어지도록 형성하여 핫-캐리어 효과를 감소시킨 데에 그 특징이 있다.In the CMOS semiconductor device, the first polysilicon layer connected to the gate electrode is formed on the device region divided by the field oxide layer so that the LDD region of the source / drain region is covered. -Characterized in reducing the carrier effect.
또한 씨모스(CMOS) 반도체 장치의 제조 방법은, 반도체 기판의 표면 근방에 제1 및 제2 전도형의 웰을 각각 형성한 후 그 위에 소자분리 산화막을 형성하고, 상기 소자분리 산화막에 의해 구분된 소자 영역 상에 게이트 산화막을 형성하는 단계; 상기 결과물 상부 전면에 제1 전도형 불순물이 고농도로 도핑된 제1 폴리실리콘층과 실리콘질화막을 순차적으로 형성하는 단계; 상기 실리콘질화막의 게이트 폴리 형성 영역 부분을 제1 폴리실리콘층이 노출되도록 식각하여 제거하는 단계; 상기 실리콘질화막의 개구부 측벽에 LTO(저온증착산화막) 스페이서를 형성하는 단계; 상기 실리콘질화막의 개구부가 채워지도록 제1 전도형 불순물이 고농도로 도핑된 제2 폴리실리콘층과 살리사이드층을 순차적으로 적층하여 게이트 폴리를 형성하는 단계; 상기 실리콘질화막을 제거한 후 웰에 주입된 불순물과 다른 전도형의 불순물을 기판 상부로 부터 소자 영역의 웰내에 고농도로 주입하고, 상기 LTO 스페이서를 제거한 다음 다시 같은 전도형의 불순물을 저농도로 주입하여 LDD를 갖는 소스/드레인 영역을 형성하는 단계; 상기 결과물 상에 LTO를 침적한 후 이를 등방성 식각하여 제2 폴리실리콘층과 살리사이드 측벽에 스페이서를 형성하고 동시에 LTO를 과도 식각하여 하부의 제1 폴리실리콘층을 제거하는 단계; 및 상기 결과물 상에 절연막을 침적한 후 각 전극을 형성하는 단계를 구비하여 이루어진 데에 그 특징이 있다.In addition, in the method of manufacturing a CMOS semiconductor device, first and second conductivity type wells are formed in the vicinity of a surface of a semiconductor substrate, and then an element isolation oxide film is formed thereon, separated by the element isolation oxide film. Forming a gate oxide film on the device region; Sequentially forming a first polysilicon layer and a silicon nitride film doped with a high concentration of a first conductivity type impurity on the entire upper surface of the resultant product; Etching to remove a portion of the gate poly formation region of the silicon nitride layer to expose the first polysilicon layer; Forming an LTO spacer on a sidewall of the opening of the silicon nitride layer; Sequentially forming a second polysilicon layer and a salicide layer doped with a first conductivity type impurity so that the opening of the silicon nitride layer is filled to form a gate poly; After the silicon nitride film is removed, impurities implanted in the well and other conductivity type impurities are implanted at a high concentration into the well of the device region from the top of the substrate, the LTO spacer is removed, and impurities of the same conductivity type are injected again at a low concentration. Forming a source / drain region having a; Depositing LTO on the resultant and isotropically etching it to form spacers on the sidewalls of the second polysilicon layer and the salicide, and simultaneously over-etching the LTO to remove the lower first polysilicon layer; And depositing an insulating film on the resultant to form each electrode.
도 1 은 종래 씨모스(CMOS) 반도체 장치의 구조 단면도.1 is a structural cross-sectional view of a conventional CMOS semiconductor device.
도 2 는 본 발명에 따른 씨모스(CMOS) 반도체 장치의 구조 단면도.2 is a cross-sectional view of a structure of a CMOS semiconductor device according to the present invention;
도 3 내지 도 10은 도 2에 도시된 반도체 장치의 공정 단면도.3 to 10 are process cross-sectional views of the semiconductor device shown in FIG. 2.
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
10 : 실리콘 기판 20,20a : 웰10: silicon substrate 20,20a: well
30,32 : 산화막 35 : 질화막30,32 oxide film 35 nitride film
40 : 게이트 폴리 42,44 : 폴리실리콘층40: gate poly 42,44: polysilicon layer
46 : 살리사이드층 48,48a : LTO 스페이서46: salicide layer 48,48a: LTO spacer
50,50a,52,52a : 소스/드레인 영역 60,62 : 포토레지스트50, 50a, 52, 52a: source / drain regions 60, 62: photoresist
70 : 절연막 80,80a,82,82a : 전극70: insulating film 80, 80a, 82, 82a: electrode
이하, 본 발명을 첨부 도면에 의거하여 보다 상세하게 설명한다.EMBODIMENT OF THE INVENTION Hereinafter, this invention is demonstrated in detail based on an accompanying drawing.
도 2 는 본 발명에 다른 씨모스 반도체 장치의 구조 단면도이며, 도 3 내지 도 11 은 도 2 에 도시된 반도체 장치의 제조 공정에 따라 단면을 도시한 것이다.2 is a structural cross-sectional view of a CMOS semiconductor device according to the present invention, and FIGS. 3 to 11 are cross-sectional views of the semiconductor device shown in FIG.
통상의 실리콘 기판(10)의 표면 근방에 p웰(20)과 n웰(22)을 형성하고, 액티브 마스크 및 LOCOS(실리콘의 국부적인 산화)법을 이용하여 기판(10) 상부에 엔모스(NMOS)와 피모스(PMOS) 소자 영역을 분리하기 위하여 소자분리 산화막(30)을 형성한다. LOCOS 공정에 사용된 질화막과 패드 산화막(도면에는 도시하지 않음)을 제거하고 열산화법을 이용하여 상기 결과물 상에 150∼200Å 두께의 게이트 산화막(32)을 성장시킨다. 그리고 그 위에 400∼500Å 두께의 n+ 제1 폴리실리콘층(42)과 4000∼5000Å 두께의 실리콘질화막(35)를 순차적으로 형성하고, 게이트 마스크를 이용하여 각 웰(20)(22) 중간 부위, 즉 각 소자 영역의 중앙부에 위치한 실리콘질화막(35)을 제1 폴리실리콘층(42)이 노출되도록 식각하여 도 3 과 같이 개구부를 형성한다.The p well 20 and the n well 22 are formed in the vicinity of the surface of the conventional silicon substrate 10, and the NMOS (top surface) of the NMOS is formed on the substrate 10 by using an active mask and LOCOS (local silicon oxidation) method. A device isolation oxide layer 30 is formed to separate the NMOS) and the PMOS device regions. The nitride film and the pad oxide film (not shown) used in the LOCOS process are removed, and the gate oxide film 32 having a thickness of 150 to 200 Å is grown on the resultant by thermal oxidation. Next, the n + first polysilicon layer 42 having a thickness of 400 to 500 kPa and the silicon nitride film 35 having a thickness of 4000 to 5000 kPa are sequentially formed thereon, and an intermediate portion of each well 20, 22 is formed using a gate mask. That is, the silicon nitride film 35 positioned in the center of each device region is etched to expose the first polysilicon layer 42 to form an opening as shown in FIG. 3.
다음, 상기 결과물 상부로 부터 실리콘질화막(35)의 개구부를 통하여 각 웰(20)(22)의 표면 근방에 채널 이온(Boron)을 주입한 다음, 도 4와 같이 기판(10)의 상부 전면에 LTO를 형성한 후 이를 선택적으로 식각하여 실리콘질화막(35)의 측벽에 LTO 스페이서(48)를 형성한다.Next, channel ions (Boron) are implanted into the vicinity of the surfaces of the wells 20 and 22 through the openings of the silicon nitride layer 35 from the upper part of the resultant, and then, on the upper front surface of the substrate 10 as shown in FIG. After the LTO is formed, it is selectively etched to form the LTO spacer 48 on the sidewall of the silicon nitride film 35.
다음 도 5와 같이, 상기 결과물 상부에 n+ 폴리실리콘을 7000∼10000Å 두께로 침적하고 에치-백 방법으로 식각하여 상기 실리콘질화막(35) 상부의 폴리실리콘을 제거함과 동시에 개구부 상단의 LTO 스페이서(48)가 노출되도록 과도 식각하여 개구부 내에 제2 폴리실리콘층(44)을 형성하고, 그 상부에 살리사이드(46)를 채워 넣어 게이트 폴리(40)를 형성한다.Next, as shown in FIG. 5, n + polysilicon is deposited on the resultant to a thickness of 7000 to 10000 mm 3 and etched by an etch-back method to remove polysilicon on the silicon nitride layer 35 and at the same time the LTO spacer 48 at the top of the opening. Is over-etched to expose the second polysilicon layer 44 in the opening, and the salicide 46 is filled in the upper portion to form the gate poly 40.
이 공정에서 소자의 채널이 형성될 곳에만 보론(Boron) 이온을 주입하므로, 채널 이온이 다음 공정에서 형성할 소스/드레인 영역의 LDD 영역에 주입되어서 발생하게 되는 전자 이동도의 감소 현상이 발생하지 않게 되는 것이다.In this process, since boron ions are implanted only where the channel of the device is to be formed, the electron mobility is not reduced due to the implantation of channel ions into the LDD region of the source / drain region to be formed in the next process. Will be.
다음 도 6과 같이, 상기 실리콘질화막(35)을 완전히 제거한 다음, 그 결과물 상부에 포토레지스트를 도포한 후 이를 노광 및 현상하여 피모스 소자 영역 상부, 즉 n웰(22)의 상부에만 도포되도록 포토레지스트(60) 패턴을 형성하고, 이를 마스크로 사용하여 기판(10) 상부로부터 p웰(20)의 표면 근방에 n+ 불순물을 주입한다. 그리고 도 7과 같이, LTO 스페이서(48)를 제거한 후 같은 방법으로 n- 불순물을 주입하여 LDD를 갖는 소스/드레인 영역(50)(50a)을 형성한다.Next, as shown in FIG. 6, the silicon nitride film 35 is completely removed, and then a photoresist is applied on the resultant, and then the photoresist is exposed and developed to apply only to the upper part of the PMOS device region, that is, the upper part of the n well 22. A resist 60 pattern is formed and n + impurity is implanted from the top of the substrate 10 to the vicinity of the surface of the p well 20 using the mask. As shown in FIG. 7, after removing the LTO spacer 48, n- impurities are implanted in the same manner to form source / drain regions 50 and 50a having LDD.
이때 LDD의 폭은 상기 LTO 스페이서(48)의 폭에 의해 조절되며, 한번의 사진 및 현상 공정으로 엔모스 영역에 고농도 및 저농도의 n형 불순물을 이온 주입하여 LDD를 포함하는 소스/드레인 영역(50)(50a)을 형성할 수 있으므로, 공정을 단순화 할 수 있다.At this time, the width of the LDD is controlled by the width of the LTO spacer 48, and the source / drain region 50 including the LDD by ion implantation of high and low concentrations of n-type impurities into the NMOS region in one photo and development process. ) 50a can be formed, so that the process can be simplified.
다음 상기 포토레지스트(50)을 제거한 후, 도 8 및 도 9 에 도시된 바와 같이 엔모스 소자 영역에 소스/드레인 영역(50)(50a)을 형성하는 방법과 같은 방법을 사용하여 피모스 소자 영역에 소스/드레인 영역(52)(52a)을 형성한다. 여기서 도면 부호 62는 포토레지스트이다.Next, after the photoresist 50 is removed, the PMOS device region is formed using the same method as that of forming the source / drain regions 50 and 50a in the NMOS device region as shown in FIGS. 8 and 9. Source / drain regions 52 and 52a are formed in the substrate. Reference numeral 62 denotes a photoresist.
p+ 및 p- 불순물 이온 주입시 살리사이드층(46)이 마스크 역할을 하게 되어 게이트 폴리(40) 즉, 제2 폴리실리콘층(44) 및 그 하부의 제1 폴리실리콘층(42)에는 이온이 주입되지 않는다.When the p + and p− impurity ions are implanted, the salicide layer 46 serves as a mask so that ions may be formed in the gate poly 40, that is, the second polysilicon layer 44 and the first polysilicon layer 42 thereunder. It is not injected.
다음 도 10 에 도시된 바와 같이, 포토레지스트(62)를 제거한 후 그 결과물 상에 LTO를 침적하고 등방성 식각하여 게이트 폴리(40) 즉, 제2 폴리실리콘층(44)와 살리사이드층(46)의 측벽에 LTO 스페이서(48a)를 형성한다. 이때 LTO를 과도 식각하여 기판(10) 상의 제1 폴리실리콘층(42)을 제거한다.Next, as shown in FIG. 10, after the photoresist 62 is removed, LTO is deposited and isotropically etched on the resultant gate poly 40, that is, the second polysilicon layer 44 and the salicide layer 46. LTO spacers 48a are formed on the sidewalls of the substrate. At this time, the LTO is excessively etched to remove the first polysilicon layer 42 on the substrate 10.
다음 상기 결과물 상에 절연막(70)을 침적하고 소스 영역, 드레인 영역 및 게이트 폴리에 연결되는 전극(80)(80a)(82)(82a)을 형성하면, 도 2에 도시된 바와 같은 씨모스 반도체 소자가 제조된다.Next, when the insulating film 70 is deposited on the resultant and the electrodes 80, 80a, 82, and 82a are connected to the source region, the drain region, and the gate poly, the CMOS semiconductor as shown in FIG. The device is manufactured.
이와 같은 공정에 의해 제조된 씨모스 반도체 장치는 LTO를 침적하고 이를 식각하여 게이트 폴리(40)에 LTO 스페이서(48a)를 형성하는 공정에서 게이트 폴리(40) 측벽에 남아 있는 스페이서(48a)가 마스크 역할을 하여 스페이서(48a) 하부의 제1 폴리실리콘층(42)이 식각되지 않고 남게 되어 결국, LDD 영역 상부가 제1 폴리실리콘(42)층에 의해 덮여 있는 구조가 된다.In the CMOS semiconductor device manufactured by the above process, the spacer 48a remaining on the sidewall of the gate poly 40 is masked by depositing and etching the LTO to form the LTO spacer 48a on the gate poly 40. The first polysilicon layer 42 under the spacer 48a remains without being etched, resulting in a structure in which the upper portion of the LDD region is covered by the first polysilicon 42 layer.
이상에서 상세히 설명한 바와 같이, 본 발명은 LDD를 갖는 소스/드레인 영역을 한 번의 사진 및 현상 공정에 의해 형성할 수 있으므로 제조 공정이 간단하고, 게이트 폴리의 제1 폴리실리콘층이 LDD 영역을 덮도록 형성하여 핫-캐리어 효과에 대한 내성을 강화시킨 효과가 있다.As described in detail above, the present invention can form the source / drain region having the LDD by one photographing and developing process, so that the manufacturing process is simple, and the first polysilicon layer of the gate poly covers the LDD region. It has the effect of strengthening the resistance to hot-carrier effect by forming.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960038051A KR100206130B1 (en) | 1996-09-03 | 1996-09-03 | Method of fabricating cmos semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960038051A KR100206130B1 (en) | 1996-09-03 | 1996-09-03 | Method of fabricating cmos semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19980019808A true KR19980019808A (en) | 1998-06-25 |
| KR100206130B1 KR100206130B1 (en) | 1999-07-01 |
Family
ID=19472620
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019960038051A KR100206130B1 (en) | 1996-09-03 | 1996-09-03 | Method of fabricating cmos semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100206130B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100676194B1 (en) * | 2000-03-30 | 2007-01-30 | 삼성전자주식회사 | Method for fabricating CMOS Transistor |
-
1996
- 1996-09-03 KR KR1019960038051A patent/KR100206130B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100676194B1 (en) * | 2000-03-30 | 2007-01-30 | 삼성전자주식회사 | Method for fabricating CMOS Transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100206130B1 (en) | 1999-07-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5933738A (en) | Method of forming a field effect transistor | |
| US5714393A (en) | Diode-connected semiconductor device and method of manufacture | |
| US5214295A (en) | Thin film field effect transistor, CMOS inverter, and methods of forming thin film field effect transistors and CMOS inverters | |
| US6066534A (en) | Method of manufacturing a field effect transistor | |
| US5654215A (en) | Method for fabrication of a non-symmetrical transistor | |
| US5705439A (en) | Method to make an asymmetrical LDD structure for deep sub-micron MOSFETS | |
| US5923982A (en) | Method of making asymmetrical transistor with lightly and heavily doped drain regions and ultra-heavily doped source region using two source/drain implant steps | |
| US6238985B1 (en) | Semiconductor device and method for fabricating the same | |
| JP2951893B2 (en) | Method of manufacturing transistor for semiconductor device | |
| US5903013A (en) | Thin film transistor and method of manufacturing the same | |
| JPH077773B2 (en) | Method for manufacturing semiconductor device | |
| JP2908715B2 (en) | Mosfet (MOSFET) and manufacturing method thereof | |
| KR100265526B1 (en) | Maufacturing method of semiconductor device | |
| JP3049496B2 (en) | Method of manufacturing MOSFET | |
| JP2952570B2 (en) | Method for manufacturing semiconductor device | |
| US5920784A (en) | Method for manufacturing a buried transistor | |
| KR100415191B1 (en) | Method for fabricating asymmetric cmos transistor | |
| KR19980019808A (en) | CMOS semiconductor device and manufacturing method thereof | |
| KR100188008B1 (en) | Method of manufacturing cmos semiconductor device | |
| KR0165421B1 (en) | Process of fabricating mos transistor | |
| KR100412143B1 (en) | Method of manufacturing semiconductor device applying a triple gate oxide | |
| KR100676194B1 (en) | Method for fabricating CMOS Transistor | |
| KR100479820B1 (en) | Manufacturing method of semiconductor device | |
| KR0161118B1 (en) | Method of forming semiconductor device | |
| KR960013947B1 (en) | Mos transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20070327 Year of fee payment: 9 |
|
| LAPS | Lapse due to unpaid annual fee |