KR0161118B1 - Method of forming semiconductor device - Google Patents
Method of forming semiconductor device Download PDFInfo
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- KR0161118B1 KR0161118B1 KR1019950015738A KR19950015738A KR0161118B1 KR 0161118 B1 KR0161118 B1 KR 0161118B1 KR 1019950015738 A KR1019950015738 A KR 1019950015738A KR 19950015738 A KR19950015738 A KR 19950015738A KR 0161118 B1 KR0161118 B1 KR 0161118B1
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- film
- semiconductor substrate
- oxidizing
- oxide film
- forming
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 66
- 238000000034 method Methods 0.000 title claims description 13
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 230000001590 oxidative effect Effects 0.000 claims abstract description 28
- 239000012535 impurity Substances 0.000 claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 claims abstract description 13
- 229910004298 SiO 2 Inorganic materials 0.000 claims abstract description 11
- 239000004020 conductor Substances 0.000 claims abstract description 9
- 238000000059 patterning Methods 0.000 claims abstract description 6
- 210000003323 beak Anatomy 0.000 claims abstract description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 5
- 238000009279 wet oxidation reaction Methods 0.000 claims description 3
- 238000000206 photolithography Methods 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 11
- 230000003647 oxidation Effects 0.000 description 9
- 238000007254 oxidation reaction Methods 0.000 description 9
- 230000000694 effects Effects 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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Abstract
본 발명의 반도체 소자 제조방법은, 1) 제1도전형 반도체기판의 전면에 제2도전형의 저농도 불순물 도핑영역을 형성하는 단계와, 2) 상기 반도체기판 상에 비산화성막을 형성하고 상기 비산화성막을 패터닝하여 게이트전극이 형성될 부분을 제외한 상기 반도체기판을 노출시키는 단계와, 3) 상기 노출된 반도체기판을 산화시켜 상기 반도체기판 상에 새부리형상을 갖는 두꺼운 산화막(SiO2)을 형성하는 단계와, 4) 상기 두꺼운 산화막을 선택적으로 제거하여 상기 비산화성막의 양측하부에 형성된 새부리형상의 산화막은 잔류시키는 단계와, 5) 상기 비산화성막을 제거하는 단계와, 6) 상기 반도체기판 상에 게이트절연막을 형성하는 단계와, 7) 상기 게이트절연막 상에 전도체층을 형성하고 상기 전도체층을 패터닝하여 게이트전극을 형성하는 단계와, 8) 상기 반도체기판에 상기 게이트 및 새부리형상의 산화막을 마스크로 사용하여 제2도전형의 불순물이 고농도로 도핑하여 고농도 불순물 도핑영역을 형성하는 단계를 포함하여 이루어진다.The semiconductor device manufacturing method of the present invention comprises the steps of: 1) forming a low concentration impurity doped region of the second conductivity type on the entire surface of the first conductive semiconductor substrate, and 2) forming a non-oxidizing film on the semiconductor substrate and Patterning a film to expose the semiconductor substrate except for a portion where a gate electrode is to be formed, and 3) oxidizing the exposed semiconductor substrate to form a thick oxide film (SiO 2 ) having a beak shape on the semiconductor substrate; 4) selectively removing the thick oxide film to leave a beak-shaped oxide film formed on both sides of the non-oxidizing film, 5) removing the non-oxidizing film, and 6) removing a gate insulating film on the semiconductor substrate. 7) forming a conductor layer on the gate insulating film and patterning the conductor layer to form a gate electrode; 8) Group is achieved by using a semiconductor substrate, the impurity of the second conductivity type using said gate oxide film and the saeburi shape as a mask in a high concentration doping and forming a high concentration impurity doped region.
Description
제1도는 종래의 반도체 소자의 모스 트랜지스터를 도시한 도면.1 is a diagram showing a MOS transistor of a conventional semiconductor device.
제2도는 종래의 반도체 LDD 구조를 갖는 모스 트랜지스터의 제조과정 중 일부를 도시한 도면.2 is a view illustrating a part of a manufacturing process of a MOS transistor having a conventional semiconductor LDD structure.
제3도는 본 발명의 반도체 소자 제조방법을 설명하기 위해 도시한 도면.3 is a view for explaining a method of manufacturing a semiconductor device of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11,21,31 : 반도체기판 12,13 : 소스/드레인11,21,31: semiconductor substrate 12,13: source / drain
22-1,32-1,32a-1 : 저농도 불순물영역 22-2,32-2 : 고농도 불순물영역22-1,32-1,32a-1: low concentration impurity region 22-2,32-2: high concentration impurity region
14,24,34 : 게이트절연막 15,25,35 : 게이트14,24,34 gate insulating film 15,25,35 gate
26-1 : 산화실리콘막 26-2 : 측벽26-1: silicon oxide film 26-2: side wall
37,37a,37b : 패드산화막 38,38a,38b : 비산화성막37,37a, 37b: pad oxide film 38,38a, 38b: non-oxidation film
39 : 두꺼운 산화막39: thick oxide film
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 모스 트랜지스터 장치에 있어서 단 채널 현상(Short channel effect)을 방지하여 모스 트랜지스터의 전기적 특성이 저하되는 것을 방지하므로써 반도체 소자의 신뢰도를 향상시킬 수 있게 한 반도체 소자 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, to prevent short channel effects in a MOS transistor device, thereby preventing the electrical characteristics of the MOS transistor from being degraded, thereby improving reliability of the semiconductor device. A method for manufacturing a semiconductor device.
제1도는 종래의 반도체 소자의 모스(MOS) 트랜지스터를 도시한 도면으로 도면을 참조하여 간단히 설명하면, 소스(Source : 12)와 드레인(Drain : 13) 영역이 형성된 반도체기판(11) 상의 수정 부분에 게이트절연막(14)이 있고 그 위에 게이트(Gate : 15)가 형성된 형태이다.FIG. 1 is a diagram illustrating a MOS transistor of a conventional semiconductor device. Referring to FIG. 1, a crystal part on a semiconductor substrate 11 having a source 12 and a drain 13 is formed. The gate insulating film 14 is formed on the gate 15.
그러나 현재 고집적화 추세에 따라 반도체 소자는 미세 디자인 룰을 갖게 되므로써 채널 길이가 매우 짧아지게 된다. 이러한 단 채널(Short channel)은 모스 트랜지스터의 접합 브레이크다운 전압(Junction Breakdown voltage)을 감소시키게 되어 일정한 채널 길이 이하로는 트랜지스터를 만들 수 없게 되며 소비 전류 또한 많게 하는 문제점이 있다. 그 예로써 종래의 방법으로 제조된 모스 트랜지스터는 현재 디자인 룰이 1.5㎛ 이하에서는 제대로 트랜지스터의 역할을 못하고 있다. 또한 게이트 폭이 좁아짐에 따라 드레인 부근의 핀치 호프(Pinch-off) 영역에 발생하는 고전계에 기인한 '핫 캐리어 효과(Hot carrier effect)'라는 문제점을 초래하고 있다. 이러한 핫 캐리어 효과는 저도핑 드레인(Lightly Doped Drain : 이하, LDD라 칭함) 구조를 형성하므로써 완화될 수 있으나 제품 완성 후에 반도체기판의 표면에 식각 손상을 받게 되어 누설 전류(Leakage current)가 증가하는 문제점을 가지고 있다.However, according to the current trend of high integration, the semiconductor device has a fine design rule, and thus the channel length becomes very short. Such a short channel reduces the junction breakdown voltage of the MOS transistor, which makes it impossible to make the transistor below a certain channel length and increases the current consumption. As an example, the MOS transistor manufactured by the conventional method currently does not function properly as a transistor when the design rule is 1.5 µm or less. In addition, as the gate width becomes narrower, a problem of 'hot carrier effect' caused by the high electric field occurring in the pinch-off region near the drain is caused. This hot carrier effect can be alleviated by forming a lightly doped drain (LDD) structure, but after the completion of the product, the surface of the semiconductor substrate is etched and the leakage current increases. Have
즉, 제2도는 종래의 반도체 LDD 구조를 갖는 모스 트랜지스터의 제조과정 중 일부를 도시한 도면으로써 도면을 참조하여 설명하면, 종래에는 LDD 구조를 갖는 모스 트랜지스터는 반도체기판(21) 상의 소정 부분에 게이트절연막(24)과 게이트전극(25)이 순차적으로 형성되고, 저농도 불순물영역(22-1)이 상기 반도체기판(21)에 상기 게이트전극(25)을 마스크로 사용하여 형성된다. 그리고, 상기 반도체기판(21) 상에 상기 게이트전극(25)을 덮도록 산화실리콘막(SiO2: 26-1)을 형성한 후 에치백(etch-back) 즉, 건식식각 방법으로 상기 게이트전극(25)의 측면에 측벽(side-well : 26-2)을 형성하게 된다. 이 측벽(26-2)은 고농도 불순물영역(22-2)의 형성에 있어 도핑 장애막 역할을 하게되는데, 상기 측벽(26-2)을 형성하기 위한 에치백에 의해 반도체기판(21)이 손상을 입게 되며, 이러한 반도체기판의 손상은 반도체 소자의 제조 후에 누설 전류 증가의 원인이 되고 있다.That is, FIG. 2 is a diagram illustrating a part of a manufacturing process of a MOS transistor having a conventional semiconductor LDD structure. Referring to the drawings, in the related art, a MOS transistor having an LDD structure is gated at a predetermined portion on a semiconductor substrate 21. The insulating film 24 and the gate electrode 25 are sequentially formed, and the low concentration impurity region 22-1 is formed on the semiconductor substrate 21 using the gate electrode 25 as a mask. Then, a silicon oxide film (SiO 2 : 26-1) is formed on the semiconductor substrate 21 to cover the gate electrode 25, and then the gate electrode is etched back, that is, by a dry etching method. A side-well 26-2 is formed on the side of 25. The sidewalls 26-2 serve as a doping barrier in the formation of the high concentration impurity regions 22-2, and the semiconductor substrate 21 is damaged by the etch back to form the sidewalls 26-2. The damage to the semiconductor substrate is a cause of the leakage current increase after the manufacture of the semiconductor device.
따라서, 본 발명은 반도체 소자의 단 채널에 따른 문제점 및 LDD 구조의 형성에 있어 반도체기판의 식각 손상을 방지하여 누설 전류의 증가를 방지하는 것을 가능하게 하는 반도체 소자 제조방법을 제공하는데 목적이 있다.Accordingly, an object of the present invention is to provide a method for fabricating a semiconductor device capable of preventing an increase in leakage current by preventing etching damage of a semiconductor substrate in forming an LDD structure and a problem according to a short channel of the semiconductor device.
본 발명의 반도체 소자 제조방법은, 1) 제1도전형 반도체기판의 전면에 제2도전형의 저농도 불순물 도핑영역을 형성하는 단계와, 2) 상기 반도체기판 상에 비산화성막을 형성하고 상기 비산화성막을 패터닝하여 게이트전극이 형성될 부분을 제외한 상기 반도체기판을 노출시키는 단계와, 3) 상기 노출된 반도체기판을 산화시켜 상기 반도체기판 상에 새부리형상을 갖는 두꺼운 산화막(SiO2)을 형성하는 단계와, 4) 상기 두꺼운 산화막을 선택적으로 제거하여 상기 비산화성막의 양측하부에 형성된 새부리형상의 산화막은 잔류시키는 단계와, 5) 상기 비산화성막을 제거하는 단계와, 6) 상기 반도체기판 상에 게이트절연막을 형성하는 단계와, 7) 상기 게이트절연막 상에 전도체층을 형성하고 상기 전도체층을 패터닝하여 게이트전극을 형성하는 단계와, 8) 상기 반도체기판에 상기 게이트 및 새부리형상의 산화막을 마스크로 사용하여 제2도전형의 불순물이 고농도로 도핑하여 고농도 불순물 도핑영역을 형성하는 단계를 포함하여 이루어진다.The semiconductor device manufacturing method of the present invention comprises the steps of: 1) forming a low concentration impurity doped region of the second conductivity type on the entire surface of the first conductive semiconductor substrate, and 2) forming a non-oxidizing film on the semiconductor substrate and Patterning a film to expose the semiconductor substrate except for a portion where a gate electrode is to be formed, and 3) oxidizing the exposed semiconductor substrate to form a thick oxide film (SiO 2 ) having a beak shape on the semiconductor substrate; 4) selectively removing the thick oxide film to leave a beak-shaped oxide film formed on both sides of the non-oxidizing film, 5) removing the non-oxidizing film, and 6) removing a gate insulating film on the semiconductor substrate. 7) forming a conductor layer on the gate insulating film and patterning the conductor layer to form a gate electrode; 8) Group is achieved by using a semiconductor substrate, the impurity of the second conductivity type using said gate oxide film and the saeburi shape as a mask in a high concentration doping and forming a high concentration impurity doped region.
여기에서, 3)단계에서 두꺼운 산화막의 형성은 습식산화로 하되 게이트전극이 형성될 부위의 저농도 불순물 도핑영역을 전부 산화시키고, 2)단계의 비산화성막은 질화실리콘막(Si3N4)으로 형성하되 반도체기판과 질화실리콘막의 사이에 패드산화막(SiO2)을 개재한 후 형성하고, 4)단계의 식각은 비산화성막을 식각마스크로하여 비등방성 식각하고, 5)단계의 게이트절연막은 산화실리콘막(SiO2)이며 7)단계의 전도체층은 다결정실리콘(Polysilicon)으로 형성한다.Here, in step 3), the thick oxide film is formed by wet oxidation, but all of the low concentration impurity doped regions of the region where the gate electrode is to be formed are oxidized, and the non-oxidizing film in step 2) is formed of a silicon nitride film (Si 3 N 4 ). After the pad oxide film (SiO 2 ) is interposed between the semiconductor substrate and the silicon nitride film, the etching of step 4) is anisotropically etched using a non-oxidizing film as an etching mask, and the gate insulating film of step 5) is a silicon oxide film. (SiO 2 ) and the conductor layer of step 7) is formed of polysilicon.
이하, 본 발명을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, described in detail with reference to the accompanying drawings of the present invention.
제3도는 본 발명의 반도체 소자 제조방법을 설명하기 위해 도시한 반도체 소자의 일부 단면도이다.3 is a partial cross-sectional view of the semiconductor device shown for explaining the method of manufacturing a semiconductor device of the present invention.
먼저, 제3도의 (a)에서 도시한 바와 같이 P형 반도체기판(31)의 전면에 N형 저농도 불순물을 도핑하여 상기 반도체기판(31)의 상부에 그 표면으로부터 소정 깊이에 이르는 저농도 불순물 영역(32-1)을 형성한다.First, as shown in FIG. 3A, a low concentration impurity region (not shown) is doped on the entire surface of the P-type semiconductor substrate 31 to reach a predetermined depth from the surface of the semiconductor substrate 31. 32-1).
이어서, 상기 저농도 불순물 영역(32-1)이 형성된 반도체기판(31) 상에 질화실리콘(Si3N4)을 이용하여 비산화성막(38)을 형성하는 데, 제3도의 (b)와 같이 반도체기판(31)과 비산화성막(38)인 실리콘기판과 질화실리콘의 사이에 완충역할을 하는 패드산화막(SiO2: 37)을 형성한 후 상기 패드산화막(37) 상에 질화실리콘을 증착하여 비산화성막(38)을 형성한다.Subsequently, a non-oxidation film 38 is formed on the semiconductor substrate 31 on which the low concentration impurity region 32-1 is formed using silicon nitride (Si 3 N 4 ), as shown in FIG. After forming a pad oxide film (SiO 2 : 37) that acts as a buffer between the semiconductor substrate 31, the silicon substrate as the non-oxidizing film 38, and silicon nitride, silicon nitride is deposited on the pad oxide film 37. A non-oxidizing film 38 is formed.
다음에 제3도의 (c)와 같이 비산화성막(38) 및 패드산화막(37)을 사진식각(Photolithograpy)하여 게이트전극이 형성될 부위의 반도체기판(31)에 형성된 저농도 불순물영역(32-1)을 노출시키는 비산화성막(38a) 및 패드산화막(37a) 패턴을 형성한다. 즉, 상기 비산화성막(38) 상에 감광막(Photoresist : 도시하지 않음)을 도포한 후 노광 및 현상하여 감광막 마스크패턴(도시하지 않음)을 형성한 후 감광막 마스크패턴을 식각마스크로 사용하여 상기 질화실리콘막(38) 및 패드산화막(37)을 식각한 후 감광막 마스크패턴을 제거하여 비산화성막(38a) 및 패드산화막(37a) 패턴을 형성한다.Next, as shown in FIG. 3C, the low concentration impurity region 32-1 formed on the semiconductor substrate 31 at the portion where the gate electrode is to be formed by photolithography of the non-oxidation film 38 and the pad oxide film 37 is performed. ) Patterns of the non-oxidation film 38a and the pad oxide film 37a are formed. That is, after the photoresist (not shown) is coated on the non-oxidizing film 38, the photoresist layer is exposed and developed to form a photoresist mask pattern (not shown), and then the photoresist mask pattern is used as an etching mask. After etching the silicon film 38 and the pad oxide film 37, the photoresist mask pattern is removed to form the non-oxidation film 38a and the pad oxide film 37a.
다음에 제3도의 (d)에 도시한 바와 같이 비산화성막(38b) 패턴이 형성되지 않아 노출된 반도체기판(31)을 산화시킨다. 즉, 비산화성막(38b)으로 게이트전극이 형성될 부분을 제외한 나머지 부분을 보호하고 게이트전극이 형성될 노출된 부분을 습식산화시켜 두꺼운 산화막(SiO2: 39)을 형성한다. 이때 도면에서 알 수 있는 바와 같이 상기 두꺼운 산화막(39)이 형성될 때, 상기 비산화성막(38b)의 양측면 밑으로 측면산화가 이루어져 상기 비산화성막(38b)의 양측면 하부에 새부리형상의 산화막이 형성된다. 그리고, 상기에서 두꺼운 산화막(39)을 형성할 때, 게이트전극이 형성될 부위의 저농도 불순물영역(32-1)이 모두 산화되도록 한다.Next, as shown in FIG. 3D, the non-oxidation film 38b pattern is not formed, thereby oxidizing the exposed semiconductor substrate 31. In other words, a thick oxide film (SiO 2 : 39) is formed by protecting the remaining portions except for the portion where the gate electrode is to be formed by the non-oxidation layer 38b and wet oxidizing the exposed portion where the gate electrode is to be formed. At this time, as can be seen in the figure when the thick oxide film 39 is formed, the side oxide is formed under both sides of the non-oxidizing film 38b to form a beak-shaped oxide film below both sides of the non-oxidizing film 38b. Is formed. When the thick oxide film 39 is formed, all of the low concentration impurity regions 32-1 in the region where the gate electrode is to be formed are oxidized.
이어 제3도의 (e)에 도시한 바와 같이 게이트전극이 형성될 부분에 형성된 상기 두꺼운 산화막(39)을 식각하여 제거하되, 상기 비산화성막(38b)의 양측면 하부에 형성된 새부리형상의 산화막(39a)을 남긴다. 즉, 비산화성막(38b)인 질화실리콘막을 식각마스크로 하여 상기 두꺼운 산화막(39)을 식각하면 상기 새부리형상의 산화막(39a)이 잔류한다. 도시하지 않았지만 상기 새부리형상의 산화막을 잔류시키고 두꺼운 산화막을 선택적으로 제거하는 다른 방법으로는 비산화성막인 질화실리콘막을 제거하고 상기 패드산화막 및 두꺼운 산화막 상에 감광막 마스크패턴을 형성한 다음 감광막 마스크패턴을 식각마스크로 하여 식각한 후 감광막 마스크 패턴을 제거하여도 같은 결과를 얻을 수 있다.Subsequently, as illustrated in (e) of FIG. 3, the thick oxide film 39 formed on the portion where the gate electrode is to be formed is etched and removed, but the bird-shaped oxide film 39a formed on both sides of the bottom surface of the non-oxidizing film 38b is removed. ). That is, when the thick oxide film 39 is etched using the silicon nitride film, which is the non-oxidation film 38b, as an etching mask, the bird-shaped oxide film 39a remains. Although not shown, another method of remaining the bird-shaped oxide film and selectively removing the thick oxide film is to remove the non-oxidizing silicon nitride film, form a photoresist mask pattern on the pad oxide film and the thick oxide film, and then apply a photoresist mask pattern. The same result can be obtained by removing the photoresist mask pattern after etching using the etching mask.
이어 비산화성막(38b)인 질화실리콘막을 제거한 후 제3도의 (f)와 같이 전면에 게이트절연막(34)으로 산화실리콘막(SiO2)을 형성한다.Then, after removing the silicon nitride film, which is the non-oxidation film 38b, a silicon oxide film (SiO 2 ) is formed on the entire surface as the gate insulating film 34 as shown in FIG.
그리고, 제3도의 (g)와 같이 상기 게이트절연막(34) 상에 게이트전극(35)을 형성한다. 즉, 상기 게이트절연막(34) 상에 게이트전극형성용 전도체층으로 다결정 실리콘을 증착한 다음 상기 다결정실리콘 상에 감광막 마스크패턴을 형성하고 감광막 마스크패턴을 식각마스크로 하여 다결정실리콘을 패터닝하여 게이트전극(35)을 형성한 후 감광막 마스크패턴을 제거하는 방법으로 게이트전극(35)을 형성한다.A gate electrode 35 is formed on the gate insulating film 34 as shown in FIG. That is, polycrystalline silicon is deposited on the gate insulating layer 34 as a gate electrode forming conductor layer, and then a photoresist mask pattern is formed on the polysilicon, and the polysilicon is patterned using the photoresist mask pattern as an etch mask. After forming 35, the gate electrode 35 is formed by removing the photoresist mask pattern.
이어서, 제3도의 (h)와 같이 상기 반도체기판(31)에 N형 고농도 불순물을 도핑하여 반도체기판 내에 고농도 불순물 영역(32-2)을 형성한다. 즉, 게이트전극(35)의 양측면에 형성된 새부리형상의 산화막(39a)을 도핑 장애막으로 하여 반도체기판(31) 내에 상기 반도체기판(31)과 도전형이 다른 고농도 불순물영역(32-2)을 형성하므로써 LDD 구조를 형성한다.Subsequently, as shown in FIG. 3 (h), the N-type high concentration impurity is doped into the semiconductor substrate 31 to form a high concentration impurity region 32-2 in the semiconductor substrate. That is, the highly doped impurity region 32-2 having a different conductivity type from that of the semiconductor substrate 31 is formed in the semiconductor substrate 31 by using the bent-shaped oxide film 39a formed on both sides of the gate electrode 35 as a doping barrier film. By forming, LDD structure is formed.
이후 공정은 종래의 방법과 동일한 방법으로 진행한다.Thereafter, the process proceeds in the same manner as the conventional method.
본 발명의 반도체 소자 제조방법은 다음과 같은 개선효과가 있다.The semiconductor device manufacturing method of the present invention has the following improvement effect.
종래의 방법으로 형성된 반도체 소자와는 달리 채널길이를 충분히 확보하므로써 단 채널에 따른 제반 문제점, 즉 트랜지스터의 접합 브레이크다운 전압이 감소함에 따라 야기되는 문제점들을 해결할 수 있고, 집적도를 개선할 수 있어 더 고집적의 제품을 생산할 수가 있고, 제조과정에서 마진을 많이 확보할 수 있다. 또한, 습식산화를 이용하여 측벽을 형성하므로써 반도체기판에 식각손상을 주지 않고도 LDD 구조를 형성하는 것이 가능하므로 종래의 방법보다 제품 완성 후 발생하는 누설 전류를 감소시키며 핫 캐리어 효과를 개선할 수 있다.Unlike the semiconductor device formed by the conventional method, by sufficiently securing the channel length, it is possible to solve the problems caused by the short channel, that is, the problems caused by the decrease in the junction breakdown voltage of the transistor, and to improve the degree of integration. Can produce products, and can secure a lot of margin in the manufacturing process. In addition, since the LDD structure can be formed without etching damage to the semiconductor substrate by forming the sidewalls by using wet oxidation, the leakage current generated after the completion of the product can be reduced and the hot carrier effect can be improved.
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