JP2954311B2 - MOS transistor - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a MOS transistor which can suppress the occurrence of double hump characteristics and is suitable for high voltage driving.

(Prior Art) Conventionally, a high breakdown voltage MOS transistor, for example, an offset type M
OS transistors are disclosed in JP-A-61-171165 and JP-A-61-171165.
There is a structure disclosed in JP-A-239667, which has a high withstand voltage and high reliability and has a structure suitable for fine processing.

6 (a) to 6 (d) are process sectional views of a method for manufacturing an offset type MOS transistor corresponding to the "MOS transistor" disclosed in Japanese Patent Application Laid-Open No. 61-171165.

6 (a) to 6 (d), a method for manufacturing a conventional offset type MOS transistor will be described.

First, the source, gate, and drain formation regions are covered with an oxidation-resistant film 1a on the P-type semiconductor substrate 1, the oxidation-resistant film 1a is patterned, and ion implantation of N-type impurities is performed using the oxidation-resistant film 1a as a mask. To form the offset layers 2, 2a. (See FIG. 6 (a)) Next, selective oxidation is performed to form selective oxide films 3, 3a. At this time, the offset layer 2a formed below a part of the selective oxide film 3a serves as a drift region, and the other offset layers 2 serve as regions which contribute to improvement in withstand voltage. (Refer to FIG. 6 (b).) Next, after forming a gate oxide film 4 and a gate electrode pattern 5 on the P-type semiconductor substrate 1 between the offset layers 2a, using the selective oxide films 3, 3a as a mask, an N-type Impurity ion implantation is performed to convert the source / drain diffusion layer 6 to the offset layer 2,
Formed between 2a. Next, after the formation of the intermediate insulating film 7, a contact hole is formed in the intermediate insulating film 7, and a wiring metal pattern 8 is formed in the contact hole. Thus, an offset type MOS transistor is formed. (Refer to FIG. 6 (d)) (Problem to be Solved by the Invention) However, in the device having the above structure, the concentration difference between the offset layer and the source layer which is a draft region on the source side during the operation of the transistor is large, and the electric field is high. , The substrate current generally called a double hump characteristic is increased. As shown in FIG. 2, when the gate voltage is increased, the substrate current increases again after reaching the first maximum value. This substrate current is trapped in the oxide film, or early deterioration of gm and V _T, and the like becomes a trigger current of the latch-up, which hinders the reliability of the MOS transistor.

In addition, a method of increasing the concentration of the offset layer to reduce the substrate current is conceivable, but this degrades the withstand voltage of the transistor, and has to sacrifice the main characteristics of the offset MOS transistor.

SUMMARY OF THE INVENTION An object of the present invention is to provide a MOS transistor which suppresses the occurrence of double hump characteristics and is suitable for high-voltage driving in order to eliminate the above-described problem of reliability deterioration due to an increase in substrate current.

(Means for Solving the Problems) In a MOS transistor according to the present invention, a gate oxide film formed on a semiconductor substrate, source / drain regions formed outside the gate oxide film, the gate oxide film and a source A MOS having an offset layer formed between the drain regions and a gate electrode formed on the gate oxide film
In the transistor, the gate electrode overlaps both sides of the source-side offset layer and the drain-side offset layer, and an overlap length with the source-side offset layer is longer than an overlap length with the drain-side offset layer. It is characterized by the following.

(Operation) According to the present invention, the MOS transistor is configured as described above. For example, when an n-type semiconductor substrate is used, the drain-side offset layer has a gate electrode having the same potential as the substrate.
That is, the drain is positively biased,
A depletion layer occurs from the gate, and the effective conductive region for lowering the electric field between the gate and the drain becomes longer.

Also, the source-side offset layer becomes a storage layer when the gate electrode is negatively biased with respect to the substrate,
The effective concentration increases, and the electric field due to the concentration difference between the source-side offset layer and the source region is weakened.

(Embodiment) An offset type MOS transistor will be described as a first embodiment of the present invention with reference to FIG.

11 is an n-type semiconductor substrate, 12 is a gate oxide film, 13 is a selective oxide film, 14 is a source side offset layer, 15 is a drain side offset layer, 16 is a source region, 17 is a drain region, and 18 is a gate electrode.

A is the gate length, B is the offset length on the source side, C
Is the drain side offset length, D is the overlap length between the gate electrode and the source side offset length, and E is the overlap length between the gate electrode and the drain side offset length.

The lengths of these A to E are set as follows.

A is arbitrarily set to satisfy the required performance of MOS such as gm and _ID . Further, B is usually set to a minimum value within a range in which the manufacturing variation can be suppressed because the parasitic resistance component is reduced. Next, C is to reduce the electric field between the drain and the gate, the breakdown voltage deterioration and gm, is set to a sufficiently long value so as to suppress the fluctuation of V _T. Next, D and E are used only for the alignment margin so that the gate insulating film is not exposed even if the misalignment occurs in the photolithography process of the gate electrode.
Set longer. However, in this embodiment, E has only the matching margin as in the related art, but D has been increased to such an extent that it does not cover the source diffusion layer. That is, assuming that the alignment margin is α, E = α, D = B−α, and D> E.

FIGS. 3 and 4 show the results of experiments performed using the offset type MOS transistors set as described above.

First, FIG. 3 shows the relationship between the overlap length (E) of the drain-side offset layer and the gate electrode and the breakdown voltage. As E becomes longer, the withstand voltage deteriorates. This means that in the offset layer in the E region, the gate electrode is at the same potential as the substrate, that is, positively biased with respect to the drain, a depletion layer from the gate easily occurs, and an effective offset that lowers the electric field between the gate and the drain. This is because the layer becomes shorter.

Next, FIG. 4 shows the substrate current characteristics using the overlap length (D) between the source-side offset layer and the gate electrode as a parameter. Generally, when the source region and the drain region are asymmetric with respect to the gate electrode, a double hump characteristic of the substrate current as shown in FIG. 2 is exhibited.

As D becomes longer, the double hump characteristic of the substrate current disappears, and the current amount also decreases. This is because the offset layer in the D region becomes a storage layer when the gate electrode is negatively biased with respect to the substrate, the effective concentration increases, and the electric field due to the concentration difference between the source side offset layer and the source region is weakened. It is because.

In this embodiment, only the gate electrode forming the overlap is shown, but it is apparent that the same result can be obtained by using a wiring metal having the same potential as the gate electrode.

Next, a method for manufacturing an offset type MOS transistor as a first embodiment of the present invention will be described with reference to FIGS. 6 (a) to 6 (d).

The source, gate, and drain formation regions are covered with an oxidation-resistant film 21a on the n-type semiconductor substrate 21, the oxidation-resistant film 21a is patterned, and p-type impurity ions (for example, boron) are formed using the oxidation-resistant film 21a as a mask. The offset layers 22, 22a are formed by performing the ion implantation of (2). (Refer to FIG. 5A.) Next, selective oxidation is performed by heat treatment in a wet oxygen atmosphere to form selective oxide films 23 and 23a. At this time, the selective oxide film 23
The offset layer 22a formed under a part of a becomes a drift region, and the other offset layers 22 become regions contributing to an improvement in breakdown voltage. (Refer to FIG. 5 (b).) Next, the oxidation resistant film 21a is removed, and then the offset layer 2 is removed.
A gate oxide film 24 and a gate electrode pattern 25 are formed on the n-type semiconductor substrate 21 between 2a.

Next, ion implantation of an n-type impurity is performed using the selective oxide films 23 and 23a as a mask to form the source / drain regions 26.
Is formed between the offset layers 22 and 22a. (Refer to FIG. 5 (c).) Next, the overlap length of the gate electrode pattern 25 and the offset layer is made longer on the source side and shorter on the drain side with respect to the gate electrode pattern 25 previously formed by the photolithography technique. Perform patterning. (Refer to FIG. 5 (d).) In the first embodiment of the present invention, an offset type MOS transistor has been described as an example.
It can also be applied to transistors.

Further, in the first embodiment of the present invention, the formation of the overlap is shown only by the gate electrode, but it is apparent that the same result can be obtained by using a wiring metal having the same potential as the gate electrode.

(Effects of the Invention) As described above, according to the present invention, the overlap length between the gate electrode and the source-side offset layer is set longer than the overlap length between the gate electrode and the drain-side offset layer. There is no deterioration, the occurrence of the double hump characteristic of the substrate current is suppressed, and a significant improvement in the reliability of the MOS transistor can be expected. In addition, since the resistance of the source region during operation decreases, the drain saturation current increases, and gm
Can be expected to improve.

[Brief description of the drawings]

FIG. 1 is a sectional view of an offset type MOS transistor according to a first embodiment of the present invention, FIG. 2 is a view showing a double hump characteristic of a substrate current, and FIG. 3 is a graph showing a relationship between an overlap length of a gate electrode and a drain side offset layer. Graph showing the change in withstand voltage,
FIG. 4 is a diagram showing a change in substrate current due to the overlap between the gate electrode and the source-side offset layer, FIG. 5 is a sectional view showing a manufacturing process of the offset type MOS transistor according to the first embodiment of the present invention, and FIG. FIG. 7 is a cross-sectional view illustrating a step in the manufacturing method of FIG. 11 ... n-type semiconductor substrate, 12 ... gate oxide film, 13 ... selective oxide film, 14 ... source side offset layer, 15 ... drain side offset layer, 16 ... source region, 17 ... drain region, 18 ... Gate electrode, A ... Gate length, B ... Offset length on the source side, C ... Offset length on the drain side, D ...
... overlap length between the gate electrode and the source-side offset layer, E ... overlap length between the gate electrode and the drain-side offset layer.

Claims (2)

(57) [Claims] A gate oxide film formed on a semiconductor substrate; a source / drain region formed outside the gate oxide film; and an offset layer formed between the gate oxide film and the source / drain region. A MOS transistor having a gate electrode formed on the gate oxide film, wherein the gate electrode overlaps both sides of a source-side offset layer and a drain-side offset layer, and has an overlap length with the source-side offset layer. Is longer than the overlap length with the drain-side offset layer. 2. The MOS transistor according to claim 1, wherein said offset layer is formed below a selective oxide film having a thickness larger than said gate oxide film.