JPS6345860A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To manufacture a high-withstand voltage transistor which shows no flucturation in its characteristics by a method wherein inverse conductivity type impurity layers and high-concentration inverse conductivity type impurity layers are each formed in the surface of a substrate using a lower electrode and an upper electrode, each consisting of a poly Si layer, as masks. CONSTITUTION:A field oxide film 2, by which an element forming region 3 is isolated, is formed on a p-type semiconductor substrate 1 and thereafter an oxide film 4 is formed on this region 3. Then, a first poly Si layer is formed on the whole surface and a lower electrode 5 is formed by patterning. Then, after n<-> regions 8 are formed in the above region 3 using the lower electrode 5 as a mask, an oxide film 6 is formed on the electrode 5. Then, an upper electrode 7 consisting of a second poly Si layer is formed. Then, an N-type impurity is implanted using the upper electrode 7 as a mask and n<+> regions 9 for constituting a source and a drain are formed in the element forming region 3. Subsequently, after an oxide film is formed on the surface of the upper electrode 7, a wiring 10 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device having a high breakdown voltage transistor used in a nonvolatile memory.

[Conventional technology]

Conventionally, semiconductor devices having this type of high voltage transistor have been constructed as shown in FIGS. 3 to 6.

That is, as shown in FIG. 3, using a gate electrode 5A made of polycrystalline silicon formed on a P-type semiconductor substrate 1 through an oxide film 4 as a mask, impurity ions are implanted using ion implantation methods with different energies. , a double diffusion train structure in which an N- type region 8 and an N+ type region 9 are formed on the surface of the semiconductor substrate, and as shown in FIGS. 4 and 5, the gate voltage IF! After ion implantation using 5A as a mask to form N- type region 8, ion implantation is performed using source/drain and in-formation masks such as oxide film 4A or aluminum PA12 as a mask to form N+ type region 9.
A D (lightly doped drain) structure and a structure called a contact method in which an N+ type region 9 is formed using a contact hole for wiring as shown in FIG. 6 are known.

[Problem that the invention seeks to solve]

The semiconductor device having the conventional structure described above has the following problems.

First, the structures shown in FIGS. 3 and 4 have a disadvantage in that they do not have a breakdown voltage that can be used as a high breakdown voltage transistor for a nonvolatile memory because the distance between the N-type regions in the lateral direction cannot be wide.

In addition, in the example shown in FIG. 5, if a photoresist is used as a mask during ion implantation of source/drain impurities,
Aluminum or the like is usually used as a mask because the photoresist hardens and becomes difficult to remove, but etching must be performed wet to prevent damage to the diffusion layer. At this time, the lateral distance of the N-type region varies depending on how the metal film used as a mask is overetched, so there is a drawback that the characteristics vary depending on the lot.

Furthermore, the method shown in FIG. 6 has the disadvantage that the process is complicated because the steps for forming the sources and drains of the high voltage transistor and other transistors are different.

An object of the present invention is to provide a method for manufacturing a semiconductor device having a high breakdown voltage transistor with less variation in characteristics and a simple manufacturing process.

[Means for solving problems]

The method for manufacturing a semiconductor device of the present invention includes the steps of: - forming a field oxide film for separating an element formation region on a conductive type semiconductor substrate; and forming a first polycrystalline silicon layer on the element formation region via an oxide film. a step of forming a lower layer electrode consisting of;
A step of ion-implanting a reverse conductivity type impurity using the lower layer electrode as a mask to form a low concentration reverse conductivity type impurity region in the element formation region, and forming an oxide film on the surface of the lower layer electrode, and then depositing a second polyimide film on the entire surface. forming a crystalline silicon layer and patterning it to form an upper layer electrode covering the lower electrode and a part of the low concentration opposite conductivity type region; and ion-implanting opposite conductivity type impurities using the upper layer electrode as a mask. forming a highly concentrated opposite conductivity type impurity region in the element formation region.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1(a) to 1(c) are cross-sectional views of a semiconductor chip shown in order of steps for explaining an embodiment of the present invention.

First, as shown in FIG. 1(a), a field oxide film 2 is formed on a P-type semiconductor substrate 1 by selective oxidation to separate element formation regions 3. As shown in FIG. Next, an oxide film 4 is formed on this element formation region 3, and then a first polycrystalline silicon layer is formed on the entire surface and patterned to form a lower electrode 5 made of the first polycrystalline silicon.

Next, as shown in FIG. 1(b), N-type impurities are ion-implanted into the element formation region 3 using the lower electrode 5 as a mask.
- forming the mold region 8; Next, an oxide film 6 is formed on the surface of the lower electrode 5 by a thermal oxidation method, and then a second polycrystalline silicon layer is formed on the entire surface, and patterned by a dry etching method to form the lower electrode 5 and the N-type region 8. An upper layer electrode 7 is formed to cover a portion.

Next, as shown in FIG. 1(c), N type impurity ions are implanted using the upper layer electrode 7 as a mask to form N+ type regions 9 constituting sources and drains in the element forming region 3. Subsequently, an oxide film is formed on the surface of the upper electrode 7, and then a contact hole is formed in the oxide film 4 above the N+ type region 9. Below, after forming an aluminum film on the entire surface, it is patterned and wiring 1
The transistor is completed by forming .

Note that the gate wiring 11 is, as shown in the plan view of FIG.
It is connected to the lower layer electrode 5, and the upper layer electrode 7 is left in a floating state.

According to this embodiment, as shown in FIG. 1(b), the upper layer electrode 7 serving as a mask for forming the N+ type region 9 is formed from a polycrystalline silicon layer, so it is not dry. Patterning can be performed with high precision using the etching method. Therefore, since there is no over-etching unlike in the case of using conventional aluminum, there is no variation in characteristics, and furthermore, a transistor with a narrow width of the N1 type region 9 can be formed.

In the above embodiment, the case of an N-channel transistor has been described, but the same applies to the case of a P-channel transistor.

〔Effect of the invention〕

As explained above, in the present invention, a low concentration impurity region of the opposite conductivity type is formed on the surface of a semiconductor substrate of one conductivity type using a lower layer electrode made of polycrystalline silicon as a mask, and then a low concentration impurity region is formed between the lower layer electrode and the lower layer electrode through an oxide film. By using the upper layer electrode made of polycrystalline silicon, which is formed to cover a portion of the opposite conductivity type impurity region as a mask, to form a highly concentrated opposite conductivity type impurity region, there is little variation in characteristics and the manufacturing process is simplified. This has the effect that a semiconductor device having a high breakdown voltage transistor can be obtained.

[Brief explanation of drawings]

1(a) to 1(C) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining one embodiment of the present invention, FIG. 2 is a plan view of FIG. 1(c), and FIGS. 3 to 3. FIG. 6 is a cross-sectional view for explaining a conventional semiconductor device. 1... P-type semiconductor substrate, 2... Field oxide film,
3... Element formation region, 4... Oxide film, 5... Lower layer electrode, 5A... Gate electrode, 6... Oxide film, 7...
- Upper layer electrode, 8... N- type region, 9... N+ type region 10... Wiring, 11... Gate wiring, 12...
Aluminum membrane. Figure 2 Figure 6

Claims (1)

[Claims] a step of forming a field oxide film separating an element formation region on a semiconductor substrate of one conductivity type; a step of forming a lower electrode made of a first polycrystalline silicon layer on the element formation region via an oxide film; A step of ion-implanting a reverse conductivity type impurity using the lower layer electrode as a mask to form a low concentration reverse conductivity type impurity region in the element formation region, and forming an oxide film on the surface of the lower layer electrode, and then depositing a second polyimide film on the entire surface. forming a crystalline silicon layer and patterning it to form an upper layer electrode covering the lower electrode and a part of the low concentration opposite conductivity type region; and ion-implanting opposite conductivity type impurities using the upper layer electrode as a mask. A method for manufacturing a semiconductor device, comprising the step of forming a highly concentrated opposite conductivity type impurity region in the element formation region.