KR970054369A - Bipolar Transistor Manufacturing Method - Google Patents

Bipolar Transistor Manufacturing Method Download PDF

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Publication number
KR970054369A
KR970054369A KR1019950047330A KR19950047330A KR970054369A KR 970054369 A KR970054369 A KR 970054369A KR 1019950047330 A KR1019950047330 A KR 1019950047330A KR 19950047330 A KR19950047330 A KR 19950047330A KR 970054369 A KR970054369 A KR 970054369A
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KR
South Korea
Prior art keywords
oxide film
forming
bipolar transistor
polysilicon layer
layer
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KR1019950047330A
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Korean (ko)
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KR100332116B1 (en
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준 황
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김주용
현대전자산업 주식회사
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Priority to KR1019950047330A priority Critical patent/KR100332116B1/en
Publication of KR970054369A publication Critical patent/KR970054369A/en
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Publication of KR100332116B1 publication Critical patent/KR100332116B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bipolar Transistors (AREA)

Abstract

본 발명은 바이폴라 트랜지스터 제조방법 개시된다.The present invention discloses a bipolar transistor manufacturing method.

본 발명은 실리콘 기판의 P웰 상에 콜렉터 N+에피층을 형성한 후, 필드 산화막을 형성하여 액티브영역을 확정하고, N+에피층의 일부와 필드 산화막의 일부상에 중첩되도록 산화막 및 P+타입의 불순물이 도핑된 베이스 폴리실리콘층을 적층한 후 그 측부에 스페이서를 형성하고, BF2로 페스탈이온주입공정을 실시한 후 열처리함에 의해 N+에피층의 일부에 P-확산영역을 형성하고, P-확산영역의 일부와 상기 산화막의 일부상에 중첩되도록 N+타입의 불순물이 도핑된 에미터 폴리실리콘층을 형성하여 바이폴라 트랜지스터를 제조한다.The present invention forms a collector N + epi layer on a P well of a silicon substrate, and then forms a field oxide film to determine an active region, and the oxide film and P + so as to overlap a part of the N + epi layer and a part of the field oxide film. After stacking a base polysilicon layer doped with a type of impurity, spacers are formed on the side, and a P - diffusion region is formed on a portion of the N + epilayer by performing a heat treatment after performing a pestal ion implantation process with BF 2 . A bipolar transistor is fabricated by forming an emitter polysilicon layer doped with an N + type impurity so as to overlap a portion of the P − diffusion region and a portion of the oxide film.

본 발명은 실리콘 기판이 식각손상되지 않아 하이 컷 오프 프리퀀시와 하이 스피드를 갖는 바이폴라 트랜지스터를 제조할 수 있다.The present invention can produce a bipolar transistor having a high cut-off frequency and a high speed since the silicon substrate is not etched.

Description

바이폴라 트랜지스터 제조방법Bipolar Transistor Manufacturing Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1A도 내지 제1C도는 본 발명의 제1실시예에 의한 바이폴라 트랜지스터 제조방법을 설명하기 위해 도시한 소자의 단면도.1A to 1C are cross-sectional views of a device for explaining the bipolar transistor manufacturing method according to the first embodiment of the present invention.

Claims (3)

바이폴라 트랜지스터 제조방법에 있어서, P웰이 형성된 실리콘 기판이 제공되고, 상기 P웰 상에 콜렉터 N+에 피층이 형성되는 단계; 소자분리공정에 의해 필드 산화막을 형성하여 액티브영역이 확정되는 단계; P+타입의 불순물이 도핑된 베이스 폴리실리콘층 및 산화막을 상기 N+에피층을 포함한 상기 필드 산화막상에 순차적으로 형성한 후, 상기 N+에 피층의 일부와 상기 필드 산화막의 일부상에 중첩되도록 상기 산화막 및 상기 베이스 폴리실리콘층이 패턴닝되는 단계; 상기 패턴닝된 산화막 및 베이스 폴리실리콘층의 측부에 스페이서가 형성되는 단계; BF2로 페스탈이온주입공정을 실시한 후 열처리함에 의해 상기 노출된 N+에피층에 P-확산영역이 형성되는 단계; 및 상기 P-확산영역의 일부와 상기 산화막의 일부상에 중첩되도록 N+타입의 불순물이 도핑된 에미터 폴리실리콘층이 형성되는 단계로 이루어지는 것을 특징으로 하는 바이폴라 트랜지스터 제조방법.A method of manufacturing a bipolar transistor, comprising: providing a silicon substrate having a P well formed thereon, and forming a layer on the collector N + on the P well; Forming a field oxide film by an element isolation process to determine an active region; A base polysilicon layer and an oxide film doped with an impurity of P + type are sequentially formed on the field oxide film including the N + epi layer, and then overlapped with a portion of the N + layer and a part of the field oxide film. Patterning the oxide film and the base polysilicon layer; Forming a spacer on sides of the patterned oxide film and the base polysilicon layer; Forming a P − diffusion region in the exposed N + epitaxial layer by performing heat treatment after performing a pestal ion implantation process with BF 2 ; And forming an emitter polysilicon layer doped with an N + type impurity so as to overlap a portion of the P − diffusion region and a portion of the oxide film. 제1항에 있어서, 상기 스페이서는 산화막으로 이루어지는 것을 특징으로 하는 바이폴라 트랜지스터 제조방법.The method of claim 1, wherein the spacer is formed of an oxide film. 제1항에 있어서, 상기 스페이서는 질화막으로 이루어지는 것을 특징으로 하는 바이폴라 트랜지스터 제조방법.The method of claim 1, wherein the spacer is formed of a nitride film. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950047330A 1995-12-07 1995-12-07 Method for fabricating bipolar transistor KR100332116B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950047330A KR100332116B1 (en) 1995-12-07 1995-12-07 Method for fabricating bipolar transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950047330A KR100332116B1 (en) 1995-12-07 1995-12-07 Method for fabricating bipolar transistor

Publications (2)

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KR970054369A true KR970054369A (en) 1997-07-31
KR100332116B1 KR100332116B1 (en) 2002-07-31

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Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR950000137B1 (en) * 1987-09-11 1995-01-10 삼성전자 주식회사 Manufacturing method of semiconductor device
KR920010063B1 (en) * 1989-03-30 1992-11-13 삼성전자 주식회사 Manufacturing method of self-matched bipolar transistor
KR930011542B1 (en) * 1991-08-09 1993-12-10 삼성전자 주식회사 Manufacturing method of bipolar transistor
US5204277A (en) * 1992-02-03 1993-04-20 Motorola, Inc. Method of forming bipolar transistor having substrate to polysilicon extrinsic base contact
JPH06244365A (en) * 1993-02-15 1994-09-02 Hitachi Ltd Semiconductor device, and manufacture thereof

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