KR920013700A - Soy structure transistor manufacturing method - Google Patents

Soy structure transistor manufacturing method Download PDF

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Publication number
KR920013700A
KR920013700A KR1019900020953A KR900020953A KR920013700A KR 920013700 A KR920013700 A KR 920013700A KR 1019900020953 A KR1019900020953 A KR 1019900020953A KR 900020953 A KR900020953 A KR 900020953A KR 920013700 A KR920013700 A KR 920013700A
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KR
South Korea
Prior art keywords
gate
forming
photo
oxide film
etch process
Prior art date
Application number
KR1019900020953A
Other languages
Korean (ko)
Other versions
KR930004301B1 (en
Inventor
김웅희
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019900020953A priority Critical patent/KR930004301B1/en
Publication of KR920013700A publication Critical patent/KR920013700A/en
Application granted granted Critical
Publication of KR930004301B1 publication Critical patent/KR930004301B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind

Abstract

내용 없음No content

Description

소이 구조의 트랜지스터 제조방법Soy structure transistor manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 제조 공정 단면도.2 is a cross-sectional view of the manufacturing process of the present invention.

Claims (2)

베어 웨이퍼에 산화규소막과 에피층을 차례로 성장시키는 단계, 상기 에피층에 포토/에치 공정을 실시하여 소정갯수의 트렌치를 형성하는 단계, 상기 트렌치내에 산화를 행하여 필드산화막을 형성하고 마스킹용 산화막을 형성한 다음 포토/에치 공정을 실시하여 게이트가 형성될 에피층 부위를 경사지게 형성하는 단계, 게이트용 산화막과 게이트용 폴리실리콘막 및 실리사이드막을 차례로 형성하고 포토/에치 공정을 거쳐 게이트를 형성하는 단계, 소오스/드레인용 저농도 이온을 주입하는 단계, 산화막을 형성하고 이를 에치하여 측벽 스페이서를 형성하는 단계, 소오스/드레인 접합용 고농도 이온주입을 실시하는 단계가 차례로 포함됨을 특징으로 하는 소이구조의 트랜지스터 제조방법.Growing a silicon oxide film and an epitaxial layer on a bare wafer in turn, and performing a photo / etch process on the epitaxial layer to form a predetermined number of trenches; Forming a portion of the epi layer on which the gate is to be formed by inclining the photo / etch process, sequentially forming a gate oxide film, a gate polysilicon film, and a silicide layer, and forming a gate through a photo / etch process; Implanting low-concentration ions for source / drain, forming an oxide film and etching the same to form sidewall spacers, and performing high-concentration ion implantation for source / drain junctions. . 제1항에 있어서, 게이트가 형성될 에피층 부위는 이방성 에치법으로 에치하여 경사지게 형성함을 특징으로하는 소이구조의 트랜지스터 제조방법.The method of claim 1, wherein the epi layer portion on which the gate is to be formed is etched by an anisotropic etching method so as to be inclined to form a transistor having a soy structure. ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.※ Note: This is to be disclosed by the original application.
KR1019900020953A 1990-12-18 1990-12-18 Making method of transistor of short channel effect structure KR930004301B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900020953A KR930004301B1 (en) 1990-12-18 1990-12-18 Making method of transistor of short channel effect structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900020953A KR930004301B1 (en) 1990-12-18 1990-12-18 Making method of transistor of short channel effect structure

Publications (2)

Publication Number Publication Date
KR920013700A true KR920013700A (en) 1992-07-29
KR930004301B1 KR930004301B1 (en) 1993-05-22

Family

ID=19307798

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900020953A KR930004301B1 (en) 1990-12-18 1990-12-18 Making method of transistor of short channel effect structure

Country Status (1)

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KR (1) KR930004301B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100304974B1 (en) * 1993-03-11 2001-11-30 김영환 Method for manufacturing mos transistor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100304974B1 (en) * 1993-03-11 2001-11-30 김영환 Method for manufacturing mos transistor

Also Published As

Publication number Publication date
KR930004301B1 (en) 1993-05-22

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