KR960026766A - Transistor Manufacturing Method - Google Patents

Transistor Manufacturing Method Download PDF

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KR960026766A
KR960026766A KR1019940037669A KR19940037669A KR960026766A KR 960026766 A KR960026766 A KR 960026766A KR 1019940037669 A KR1019940037669 A KR 1019940037669A KR 19940037669 A KR19940037669 A KR 19940037669A KR 960026766 A KR960026766 A KR 960026766A
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South Korea
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gate electrode
semiconductor substrate
insulating film
mask
forming
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KR1019940037669A
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Korean (ko)
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KR0167606B1 (en
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박상훈
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김주용
현대전자산업 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Ceramic Engineering (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 얕은 접합을 형성하기 위한 매립형 LDD 구조 트랜지스터 제조방법에 관한 것으로, 반도체기판에 소자분리층, 게이트 및 소스/드레인이 형성되는 트랜지스터 제조방법에 있어서, 게이트전극 측벽에 제1스페이서를 형성한 후 이를 마스크로 상기 반도체기판에이온주입하는 제1단계; 상기 게이트전극 및 제1스페이서 측벽에 제2스페이서를 형성한 후 이를 마스크로 게이트전극 하부의 반도체기판에 트랜치를 형성하는 제2단계를 포함하여 이루어지는 것을 특징으로 한다.The present invention relates to a method of manufacturing a buried LDD structure transistor for forming a shallow junction. In a transistor manufacturing method in which an isolation layer, a gate, and a source / drain are formed on a semiconductor substrate, a first spacer is formed on a sidewall of a gate electrode. A first step of implanting ions into the semiconductor substrate using a mask; And forming a second spacer on the sidewalls of the gate electrode and the first spacer, and then forming a trench in the semiconductor substrate under the gate electrode using the mask.

Description

트랜지스터 제조방법Transistor Manufacturing Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 내지 제2E도는 본 발명의 일실시예에 다른 트랜지스터 제조과정을 나타내는 공정 단면도.2A through 2E are cross-sectional views illustrating a process of fabricating another transistor according to an embodiment of the present invention.

Claims (11)

반도체기판에 소자분리층, 게이트 및 소스/드레인이 형성되는 트랜지스터 제조방법에 있어서, 게이트전극 측벽에 제1스페이서를 형성한 후 이를 마스크로 상기 반도체기판에 이온주입하는 제1단계; 상기 게이트전극 및 제1스페이서 측벽에 제2스페이서를 형성한 후 이를 마스크로 게이트전극 하부의 반도체기판에 트랜치를 형성하는 제2단계를 포함하여 이루어지는 것을 특징으로 하는 트랜지스터 제조방법.A transistor manufacturing method in which a device isolation layer, a gate, and a source / drain are formed on a semiconductor substrate, the method comprising: forming a first spacer on a sidewall of a gate electrode and implanting ions into the semiconductor substrate using a mask; And forming a second spacer on the sidewalls of the gate electrode and the first spacer and forming a trench in the semiconductor substrate under the gate electrode using the mask. 제1항에 있어서, 상기제1단계는 게이트전극용 폴리실리콘막 형성후 마스크를 이용한 비등방성 과소식각 하여 폴리실리콘막이 하부에 소정정도 잔류하도록 하는 제3단계; 상기 폴리실리콘막을 이온주입마스크로 하여 노출된 반도체기판에 불순물을 이온주입하는 제4단계; 상기 구조 전체 상부에 절연막을 증착한 후 비등방성 과소식각하여 게이트전극 측벽에 소정두께의 산화막이 잔류하도록 하는 제5단계를 포함하여 이루어지는 것을 특징으로 하는 트랜지스터 제조방법.The method of claim 1, wherein the first step comprises: a third step of anisotropic over-etching using a mask to form a polysilicon film for the gate electrode so that the polysilicon film remains at a predetermined level under the gate electrode; A fourth step of ion implanting impurities into the exposed semiconductor substrate using the polysilicon film as an ion implantation mask; And depositing an insulating film over the entire structure, and performing anisotropic underetching so that an oxide film having a predetermined thickness remains on the sidewall of the gate electrode. 제2항에 있어서, 상기 제3단계의 마스크로 감광막패턴을 사용하는 것을 특징으로 하는 트랜지스터 제조방법.The method of claim 2, wherein a photosensitive film pattern is used as the mask of the third step. 제2항에 있어서, 상기 잔류하는 폴리실리콘막은 50 내지 100Å 두께가 되도록 하는 것을 특징으로 하는 트랜지스터 제조방법.3. The method of claim 2, wherein the remaining polysilicon film is 50 to 100 microns thick. 제2항에 있어서, 상기 제4단계는 N형 불순물을 소정의 각도로 기울여서 2회 반복하여 이온주입함으로써 이루어지는 것을 특징으로 하는 트랜지스터 제조방법.The method of claim 2, wherein the fourth step is performed by ion implantation twice by tilting an N-type impurity at a predetermined angle. 제5항에 있어서, 상기 N형 불순물 이온주입은 인(P) 원자를 50 내지 80KeV, 1×1012내지 1×1015원자/㎠의 조건으로 주입함으로써 이루어지는 것을 특징으로 하는 트랜지스터 제조방법.The method of claim 5, wherein the implantation of the N-type impurity ions is performed by implanting phosphorus (P) atoms under conditions of 50 to 80 KeV and 1 × 10 12 to 1 × 10 15 atoms / cm 2. 제2항에 있어서, 제5단계는 전체구조 상부에 절연막 1000 내지 2000Å 증착한 후 비등방성 과소식각하여 게이트전극 측벽에 100Å 내외의 절연막이 잔류하도록 함으로써 이루어지는 것을 특징으로 하는 트랜지스터 제조방법.The method of claim 2, wherein the fifth step is performed by depositing 1000 to 2000 microns of insulating film over the entire structure, and then anisotropically over-etching to leave an insulating film of about 100 microns on the sidewall of the gate electrode. 제7항에 있어서, 상기 절연막은 TEOS 산화막인 것을 특징으로 하는 트랜지스터 제조방법.8. The method of claim 7, wherein the insulating film is a TEOS oxide film. 제1항에 있어서, 상기 제2단계는 제1단계 수행후 상기 구조 전체 상부에 절연막을 증착 및 비등방성 식각하여 절연막 스페이서를 형성하는 단계; 상기 절연막 스페이서를 마스크로 노출된 반도체기판을 식각하는 단계를 포함하여 이루어지는 것을 특징으로 하는 트랜지스터 제조방법.The method of claim 1, wherein the second step comprises: forming an insulating film spacer by depositing and anisotropically etching the insulating film over the entire structure after performing the first step; And etching the semiconductor substrate exposed by the insulating film spacers as a mask. 제9항에 있어서, 절연막은 500 내지 1000Å 두께의 질화막인 것을 특징으로 하는 트랜지스터 제조방법.10. The method of claim 9, wherein the insulating film is a nitride film having a thickness of 500 to 1000 mW. 제1항, 제2항, 제9항 중 어느 한 항에 있어서, 상기 반도체 기판에 트랜치 형성후 노출된 반도체기판 및 게이트 전극에 선택적인 실리사이드막을 형성하는 단계를 더 포함하여 이루어지는 것을 특징으로 하는 트랜지스터 제조방법.10. The transistor of any one of claims 1, 2, and 9, further comprising forming a selective silicide layer on the exposed semiconductor substrate and gate electrode after the trench is formed in the semiconductor substrate. Manufacturing method. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940037669A 1994-12-28 1994-12-28 Process of fabricating mos-transistor KR0167606B1 (en)

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Publication number Priority date Publication date Assignee Title
KR100438665B1 (en) * 1996-12-30 2004-10-08 주식회사 하이닉스반도체 Method for manufacturing embedded memory device using dual insulating spacer with different etching selectivity
KR100885787B1 (en) * 2006-10-31 2009-02-26 주식회사 하이닉스반도체 Method of manufacturing a non-volatile memory device

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