KR19980046001A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

The present invention relates to a semiconductor device capable of suppressing the short channel effect by forming a source and drain region having an extremely shallow and high doping concentration, and a method of manufacturing the semiconductor device according to the present invention comprises a first conductive semiconductor substrate; A gate formed on the substrate; First insulating film spacers formed on both sidewalls of the gate; An epitaxial layer of a second conductivity type formed on the substrate on both sides of the first insulating film spacer; Second insulating film spacers formed on both side walls of the first insulating film spacer and on a predetermined portion on the epitaxial layer; And a source and drain region of the second conductivity type of the LDD structure formed in the substrate on both sides of the gate.

Description

Semiconductor device and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device and a method for manufacturing the same that can reduce a short channel effect.

As the semiconductor technology becomes thin and short and small, the channel spacing between the source and drain regions of the unit device is decreasing. Accordingly, in order to suppress the accompanying short channel effect, an extremely shallow and very high concentration of source and drain junction regions is required. However, it is difficult to form source and drain regions with shallow, high concentration impurity profiles by ion implantation processes. In particular, PMOS is more vulnerable than NMOS because it is difficult to control the impurity profile of B and its diffusion is severe.

1A to 1C are cross-sectional views illustrating a method of manufacturing a transistor having a conventionally lightly doped drain (LDD) structure used to reduce a short channel effect.

First, as shown in FIG. 1A, a gate insulating film 2 and a gate 3 are formed on a semiconductor substrate 1, and low concentration impurity ions are introduced into the substrate 1 using the gate 3 as an ion implantation mask. Injecting to form the low concentration diffusion region (4).

As shown in FIG. 1B, oxide spacers 5 are formed on both sidewalls of gate 3, and high concentration impurity ions are implanted into substrate 1 to form high concentration diffusion region 6.

As shown in FIG. 1C, annealing is performed to activate the low concentration and high concentration impurity ions, thereby completing the junction region of the LDD structure of the low concentration diffusion region 5 and the high concentration diffusion region 6.

However, the transistor of the conventional LDD structure has a short channel effect because the reliability of the device decreases as the ion implantation process is performed in a fine structure, and the depth of the low concentration diffusion region and the high concentration diffusion region is very deep, such as 0.1 to 0.3 μm. Vulnerable to

On the other hand, in order to reduce the short channel effect in addition to the LDD structure, a low energy ion implantation process and a counter doping method are used, but the process is not only complicated, but also increases the contact resistance and the junction capacitance. It was accompanied.

Accordingly, an object of the present invention is to provide a semiconductor device capable of suppressing short channel effects by forming a source and drain region having an extremely shallow and high doping concentration, and a method of manufacturing the same. have.

1A to 1C are cross-sectional views sequentially showing the method of manufacturing a conventional semiconductor device having an LDD structure.

2A through 2E are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

11: semiconductor substrate 12: field oxide film

13 gate oxide film 14 gate

15 insulating film spacer 16 epitaxial layer

17: p ^- region 18: oxide spacer

19: p ⁺ region

A semiconductor device according to the present invention for achieving the above object is a first conductivity type semiconductor substrate; A gate formed on the substrate; First insulating film spacers formed on both sidewalls of the gate; An epitaxial layer of a second conductivity type formed on the substrate on both sides of the first insulating film spacer; A second insulating film spacer formed on both sidewalls of the first insulating film spacer and a predetermined portion on the epitaxial layer; And a source and drain region of the second conductivity type of the LDD structure formed in the substrate on both sides of the gate.

In addition, a method of manufacturing a semiconductor device according to the present invention for achieving the above object comprises the steps of sequentially forming a gate insulating film and a gate on a first conductivity type semiconductor substrate; Forming first insulating film spacers on both sidewalls of the gate; Forming an epitaxial layer of a second conductivity type on the substrate on both sides of the first insulating film spacer; Forming a low concentration impurity region of a second conductivity type in the substrate below the epitaxial layer; Forming second insulating film spacers on both sidewalls of the first insulating film spacers; Implanting high concentration impurity ions of a second conductivity type into the substrate on both sides of the second insulating layer spacer to form high concentration impurity ions of a second conductivity type; And annealing the low concentration impurity and high concentration impurity ions.

In addition, the epitaxial layer grows the epitaxial layer in an in situ manner and simultaneously dopes the second conductivity type impurity, and the second conductivity type low concentration impurity region is formed of the doped second conductivity type impurity. It is characterized by forming by diffusion.

According to the present invention having the above structure, after forming the epitaxial layer of the second conductivity type, impurities are diffused into the substrate to form low concentration regions, and high concentration impurity ions are implanted through the epitaxial layer to form high concentration regions. As a result, the source and drain regions having a high doping concentration and a shallow depth can be formed.

EXAMPLE

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.

2A through 2E are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

First, as shown in FIG. 2A, the field oxide film 12 is formed on the semiconductor substrate 11 by a known LOCOS (LOCal Oxidation of Silicon) method. A gate oxide film 13 is formed on the substrate 11 in the active region between the field oxide films 12, and a polysilicon film is deposited and patterned on the gate oxide film 13 to form the gate 14.

As shown in FIG. 2B, a nitride film having a relatively high dielectric constant is deposited to a thickness of 200 to 1,000 GPa on the substrate 11 on which the gate 14 is formed, and the nitride film is anisotropic blanket etched to form both side walls of the gate 14. An insulating film spacer 15 is formed on the substrate.

As shown in FIG. 2C, an epitaxial layer 16 doped with B in an in-situ manner is formed on the substrate 11 on both sides of the insulating film spacer 15 to a thickness of 200 to 500 Å. At this time, the epitaxial layer is grown by autodoping as amorphous silicon. Subsequently, B doped in the epitaxial layer 16 in a solid state diffusion manner is diffused into the lower substrate 11 to form the p ⁻ region 17.

As shown in FIG. 2D, an oxide film is thickly deposited on the substrate 11 having the p ⁻ region 17 formed thereon by LPCVD, and the oxide film is anisotropic blanket etched to form oxide spacers on both sides of the insulating film spacer 15. 18). Subsequently, p ⁺ ions are implanted into the substrate 11 using the oxide spacer 18 as an ion implantation mask to form a p ⁺ region 19.

As shown in FIG. 2E, the source and drain regions are completed with p ⁻ region 17 and p ⁺ region 19 by annealing for activation of the p ⁻ and p ⁺ impurities.

On the other hand, the above embodiment has been described in the case of the P MOS transistor, it can be easily understood by those skilled in the art that it can be applied to the N MOS transistor.

According to the above embodiment, as the impurity doped epitaxial layer is formed and then the impurities are diffused into the substrate to form a low concentration region, it is easy to adjust the impurity profile of B, for example. In addition, by implanting high concentration impurity ions through the epitaxial layer, source and drain regions having a high doping concentration and a shallow depth can be formed.

Accordingly, the reliability of the device can be improved by effectively suppressing the short channel effect in a highly integrated device, for example, a device having a channel length of 0.25 mu m or less.

In addition, this invention is not limited to the said Example, It can variously deform and implement within the range which does not deviate from the technical summary of this invention.

Claims (20)

A first conductivity type semiconductor substrate; A gate formed on the substrate; First insulating film spacers formed on both sidewalls of the gate; An epitaxial layer of a second conductivity type formed on the substrate on both sides of the first insulating film spacer; Second insulating film spacers formed on both sidewalls of the first insulating film spacer and a predetermined portion on the epitaxial layer; And, And a source and drain region of the second conductivity type of the LDD structure formed in the substrate on both sides of the gate. The semiconductor device of claim 1, wherein the epitaxial layer is amorphous silicon. The semiconductor device according to claim 1, wherein said first insulating film is a nitride film. The semiconductor device according to claim 1, wherein the second insulating film is an oxide film. The semiconductor device according to claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type. 6. The semiconductor device of claim 5, wherein the epitaxial layer is doped with B. The semiconductor device according to claim 1, wherein the first conductivity type is p-type and the second conductivity type is n-type. Sequentially forming a gate insulating film and a gate on the first conductivity type semiconductor substrate; Forming first insulating film spacers on both sidewalls of the gate; Forming an epitaxial layer of a second conductivity type on the substrate on both sides of the first insulating film spacer; Implanting low concentration impurity ions of a second conductivity type into the substrate below the epitaxial layer to form high concentration impurity ions of a second conductivity type; Forming second insulating film spacers on both sidewalls of the first insulating film spacers; Forming a high concentration impurity region of a second conductivity type in the substrate on both sides of the second insulating film spacer; And, And annealing the low concentration impurity and high concentration impurity regions. The method of claim 8, wherein the epitaxial layer grows the epitaxial layer in an in situ manner and simultaneously dopes the second conductivity type impurity. 10. The method of claim 9, wherein the epitaxial layer is grown by autodoping in an amorphous state. The method of claim 10, wherein the epitaxial layer is formed to a thickness of 200 to 500 kPa. 10. The method of claim 9, wherein the second conductivity type low concentration impurity region is formed by diffusing the doped second conductivity type impurity. The method of claim 12, wherein the diffusion process proceeds in a solid state diffusion manner. 10. The method of claim 8, wherein the first insulating film is a nitride film. 15. The method of claim 14, wherein the first insulating film spacer is formed by depositing a nitride film on the substrate and etching anisotropically. 15. The method of claim 14, wherein the nitride film is deposited to a thickness of 200 to 1,000 mW. 10. The method of claim 8, wherein the second insulating film is an oxide film. The method of claim 8, wherein the first conductivity type is n-type and the second conductivity type is p-type. The method of claim 18, wherein the epitaxial layer is doped with B. 19. The method of claim 8, wherein the first conductivity type is p-type and the second conductivity type is n-type.