JPS6386476A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the collector resistance by forming a base electrode drawing layer within a recess in the base layer surface, and providing a construction so that the base layer and the base contact portion of the base electrode become the side wall part of the recess. CONSTITUTION:In a semiconductor integrated circuit device wherein a collector buried layer 5 of the second conductivity type is formed in a semiconductor substrate 1 of the first conductivity type and thereon a collector layer 6, a base layer 14 of the first conductivity type and an emittor layer 30 of the second conductivity type are formed, a recess 17 is formed in the surface of the base layer 14 and a hole section 19 reaching the collector buried layer 5 from a predetermined part of the surface of the device region consisting of the respective layers is formed, a wiring material layer is formed on the surfaces of the recess 17 and the hole section 19, and thereafter performing anisotropic etching, thereby forming a base electrode drawing layer 25 and a collector electrode drawing layer 26 respectively within the recess 17 and the hole section 19. With this, the spacing between the base contact part and the emitter contact part can be made small to reduce the base resistance.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor integrated circuit device, and particularly to a method of manufacturing a Brainer transistor.

[Prior Art] A conventional method for manufacturing a brainer transistor will be described with reference to FIGS. 2(a) to 2(d).

First, as shown in FIG. 2(a), an oxide film 2 is formed on a first conductivity type silicon substrate 1, and after patterning with a resist 3, this oxide film 2 and a second conductivity type are formed using a cyst 3 as a mask. Impurity 4 is ion-implanted. As shown in FIG. 2(b), after removing the oxide film 2 and the resist 3, the implanted impurity of the second conductivity type is activated by heat treatment to form the collector buried layer 5. A second conductivity type collector layer 6 is formed thereon by epitaxial growth. Next, as shown in FIG. 2(c), an oxide film 7 and a nitride film 8 are formed on the surface, and a resist 10 is used to remove the oxide film 7 and nitride film 8 in the element isolation region 9. Then, using the oxide film 7, nitride film 8, and resist 10 as masks, silicon etching is performed on the element isolation region 9. Furthermore, as shown in FIG. 2(d), after removing the resist 10, a field oxide film 11 is formed in the element isolation region 9.

Then, a highly concentrated collector all 5a of the second conductivity type is formed from a predetermined region to the upper part of the collector buried layer 5 by ion implantation, and the base layer 14 is formed by thermal diffusion of the first conductivity type impurity.
The emitter layer 30 is formed by thermal diffusion of second conductivity type impurities. After that, a contact hole is provided at a predetermined location in the oxide film 7, and the base electrode 32 is connected through the silicide layer 31.
, a collector electrode 33 and an emitter electrode 34 are formed.

In this way, the device is completed.

[Problems to be Solved by the Invention] In the Brainer transistor manufactured by the conventional method as described above, the base electrode and the emitter electrode are formed on the same plane, and the base electrode and the emitter electrode are separated. Because it is necessary to provide a margin for
It is not possible to form the emitter layer and the contact part of the emitter electrode (emitter contact part) close to each other.
It was not possible to reduce the base resistance very much. Furthermore, since the base contact portion and the emitter contact portion are on the same plane, base current is concentrated at the emitter side end of the base contact portion, increasing contact resistance. Furthermore, for the contact between the collector and the collector electrode', in order to reduce the resistance between the collector buried layer and the collector electrode, it is necessary to form a collector all with high concentration impurity ions implanted, which increases the number of steps. There were problems such as.

Furthermore, misalignment when forming the base electrode and the collector electrode on the base contact portion and the collector contact portion, respectively, has also been a problem.

This invention was made to solve the above-mentioned problems, and it is possible to reduce the base resistance by reducing the distance between the base contact part and the emitter contact part, and also to make it possible to reduce the base resistance evenly in the base contact part. A method for manufacturing a semiconductor integrated circuit device in which the contact resistance can be reduced by flowing a base current, the collector resistance can be reduced without a collector all, and there is no misalignment when forming the base electrode and the collector electrode. The purpose is to provide

Means for Solving Problem E] In the manufacturing method according to the present invention, a collector buried layer of the second conductivity type is formed on a semiconductor substrate of the first conductivity type, and a collector layer of the first conductivity type is formed on the collector buried layer of the second conductivity type. In a semiconductor integrated circuit device in which a base layer and an emitter layer of a second conductivity type are formed, a recess is formed on the surface of the base layer, and a hole reaches the collector buried layer from a predetermined location on the surface of the element region made up of each of the layers. After forming a wiring material layer on the surfaces of the four parts and the hole, anisotropic etching is performed to form a base electrode lead layer and a collector electrode lead layer inside the four parts and the hole, respectively. be.

[Function] According to the method for manufacturing a semiconductor integrated circuit device according to the present invention, the base electrode extraction layer is formed inside the recess on the surface of the base layer, so that the base contact portion, which is the contact portion between the base layer and the base electrode, is formed inside the recess. It becomes the side wall part of. Therefore, by forming the recess near the emitter contact portion, which is the contact portion between the emitter layer and the emitter electrode, the distance between the base contact portion and the emitter contact portion can be reduced. At this time, since the base contact portion and the emitter contact portion are not on the same plane, there is no need to separate the base contact portion and the emitter contact portion by providing a margin for separating the base electrode and the emitter electrode.

Further, since the base contact portion becomes the side wall portion of the recess, the base current flows uniformly almost perpendicularly to the base contact portion. Further, contact between the collector and the collector electrode is made directly from the collector buried layer to the collector electrode extraction layer through the hole. Furthermore, by anisotropically etching the wiring material layer formed on the surfaces of the recesses and holes, a base electrode lead layer and a collector electrode lead layer are formed in a self-aligned manner inside the four parts and the hole, respectively.

[Example] An embodiment of the present invention will be described below with reference to the drawings.

FIGS. 1A to 1Q are process cross-sectional views showing a method for manufacturing a semiconductor integrated circuit device according to the present invention.

First, as shown in FIG. 1(a), an oxide film 2 is formed on a silicon substrate 1 of a first conductivity type, and this oxide film 2 is buttered with a resist 3. Second conductivity type impurity 4 is ion-implanted using a mask. Then, as shown in FIG. 1(b), the oxide film 2 and the resist 3
After removing, the implanted second conductivity type impurities are activated by heat treatment to form the collector buried layer 5.

Next, as shown in FIG. 1C, a second conductivity type collector layer 6 is formed on the collector buried layer 5 by epitaxial growth. Furthermore, as shown in FIG. 1(d), an oxide film 7 and a nitride film 8 are formed on the surface, and a resist 10 is patterned to etch an element isolation region 9.
After forming, nitride film etching and oxide film etching are performed, and silicon etching is further performed. Then, Figure 1 (
As shown in e), after removing the resist 10, a field oxide film 11 is formed in the element isolation region 9.

Next, as shown in FIG. 1(f), after removing the nitride film 8 and the oxide film 7, an oxide film 12 is formed over the entire surface, and the first
A conductive type impurity 13 is ion-implanted. And Figure 1 (g
), the implanted impurities are activated by heat treatment to form a base layer 14, and a nitride film 15 is formed over the entire surface. Furthermore, as shown in FIG. 1(h), a resist 16 is formed in a predetermined region on the nitride film 15 in the element region. And as shown in Figure 1(i),
After etching the nitride film 15 and oxide film 12, the surface of the base layer 14 is etched with silicon to form shallow recesses 17 and 1.
Form 7a.

Next, as shown in FIG. 1(j), a resist 18 is formed in the recess 17 where the base electrode is taken out, and the recess 17a where the collector electrode is taken out is etched with silicon until it reaches the collector buried layer 5. A hole 19 is formed. Then, as shown in FIG. 1(k), after removing the resists 16 and 18, an oxide film 20 is formed on the surface. Next, Figure 1 (1
), after removing the resist 18, an oxide film 20 is formed on the surface. Next, as shown in FIG. 1 (Q), the region of the hole 19 is covered with a resist 21, and the oxide film 20 in other regions is removed. Then, as shown in FIG. 1(m), after removing the resist 21, anisotropic etching is performed to remove the oxide film on the bottom of the hole 19, leaving the oxide film 20 on the side wall of the hole 19. 20 is removed to expose the silicon surface of the collector buried layer 5. At this time, anisotropic etching is performed under conditions such that the etching rate of the oxide film is higher than the etching rate of the nitride film.

Next, as shown in FIG. 1(n), after removing the nitride film 15 by etching, polysilicon 22 is deposited over the entire surface, and a resist 23 is deposited on the area to be used as the electrode lead-out portion.
form. Next, as shown in FIG. 1(0), anisotropic processing and soching are performed until the polysilicon layer 22 is removed from the surface of the element region 24, and the polysilicon remaining on the side walls of the recess 17 and the electrode lead-out portion is used as a base. Electrode drawer 1 layer 2
5, and the polysilicon remaining on the side wall portion of the hole 19 and the electrode lead-out portion is used as the collector electrode lead-out layer 26.

At this time, anisotropic etching is performed under conditions such that the etching rate of polysilicon is higher than the etching rate of the oxide film. Furthermore, as shown in FIG. 1(p), a resist 27 is formed on the surface, patterned so that the region where the emitter is to be formed is opened, and the oxide film 12 in the opened portion is removed to form a contact hole. After forming 28, second conductivity type impurity 29 is ion-implanted.

Then, as shown in FIG. 1(q), the implanted impurities are activated by heat treatment to form an emitter layer 30. After that, the resist 27 is removed and the silicide layer 31 is removed.
The surface of the base electrode extraction layer 25, the collector electrode extraction layer 2
Emitter layer 3 on the surface of 6 and in the contact hole 27
0, and a base electrode 32 is formed on the surface of each base electrode 32.
, a collector electrode 33 and an emitter electrode 34 are formed.

The device is completed in the above manner.

In the semiconductor integrated circuit device manufactured by this method, since the base electrode extraction layer 25 is formed inside the four parts 17,
A contact portion between the base layer 14 and the base electrode extraction layer 25 becomes a side wall portion of the recess 17.

By forming the recess 17 near the emitter layer 30, it is possible to reduce the distance between the base contact portion and the emitter contact portion, thereby reducing the base resistance. Further, in this semiconductor integrated circuit device, since the base contact portion becomes the side wall portion of the recess 17, the base current flows uniformly almost perpendicularly to the base contact portion, reducing contact resistance.

Furthermore, according to this method, the base electrode extraction layer 25 and the collector electrode extraction layer 26 are formed in a self-aligned manner inside the recess 17 and the hole 19, respectively, so that misalignment when forming the electrodes does not pose a problem.

Note that instead of forming the base electrode lead layer 25 and the collector electrode lead layer 26 into a two-layer structure of polysilicon and silicide, these portions may be formed of molybdenum silicide.

[Effects of the Invention] As described above, according to the method of manufacturing a semiconductor integrated circuit device of the present invention, the contact portion between the base layer and the base electrode is located on the side wall of the recess, so that the base contact portion and the emitter The spacing between the contact portions can be reduced, thereby reducing the base resistance. Furthermore, since the base current flows uniformly through the base contact portion, the contact resistance is reduced. Furthermore, since the collector contact is made directly from the collector buried layer through the hole, the collector resistance is reduced and the step of forming the collector wall is omitted. Moreover,
Since the base electrode lead layer and the collector electrode lead layer are formed in a self-aligned manner with respect to their respective contact portions, misalignment between the electrodes and the contact portions does not pose a problem.

Therefore, it becomes possible to construct a high-speed and highly integrated semiconductor integrated circuit.

[Brief explanation of the drawing]

1(a) to q) are process sectional views showing an embodiment of the method for manufacturing a semiconductor integrated circuit device of the present invention, and FIG.
a) to d) are process cross-sectional views showing a conventional manufacturing method. In the figure, 1 is a silicon substrate, 5 is a collector buried layer,
6 is a collector layer, 14 is a base layer, 17 is a recess, 19 is a hole, 22 is a polysilicon layer, 24 is an element region, 25 is a base electrode extraction layer, 26 is a collector electrode extraction layer, and 30 is an emitter layer. . Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (4)

[Claims] (1) A step of forming a second conductivity type collector buried layer on a first conductivity type semiconductor substrate, a step of forming a collector layer on the collector layer, and a first conductivity type collector layer on the top of the collector layer. a step of forming a base layer of a conductivity type; a step of forming an emitter layer of a second conductivity type in a predetermined region on the surface of the base layer; a step of forming a recess in another region of the surface of the base layer; forming a hole reaching the collector buried layer from a predetermined location on the surface of the element region, forming a wiring material layer on the surface of the recess and hole, and performing anisotropic etching to form the recess and hole. 1. A method for manufacturing a semiconductor integrated circuit device, comprising forming a base electrode lead layer and a collector electrode lead layer inside each part. (2) The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the wiring material layer is formed of polysilicon. (3) A method for manufacturing a semiconductor integrated circuit device according to claim 1, characterized in that a silicide layer is formed on the surfaces of the base electrode lead layer and the collector electrode lead layer. (4) The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the wiring material layer is formed of molybdenum silicide.