JPH0147900B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device comprising a composite device of a bipolar transistor and an insulated gate field effect transistor, and a self-aligned manufacturing method thereof.

Conventionally, in a semiconductor device made of this type of composite element, the bipolar transistor and the insulated gate field effect transistor are separated by an element isolation region, which increases the area occupied by the composite element as a whole. There was a drawback.

In order to improve these drawbacks, a structure has been proposed in which a bipolar transistor and an insulated gate field effect transistor are integrated into one transistor structure region (Japanese Patent Application No. 1983-3841). Even in that case, since the emitter and the drain, that is, the emitter and the base electrode extraction region are not formed in self-alignment with each other, there is a limit to the reduction in the area occupied by the element.

In addition, in the conventional manufacturing method of this type of composite element, diffusion of the base, diffusion of the emitter, source, and drain, diffusion of the region for leading out the base electrode, formation of the contact hole, and formation of the electrode are performed five or more times. These photolithography processes include a photoring-fly process, and it is necessary to provide a photomask alignment margin within the region for forming the transistor, which also causes an increase in the area occupied by the composite element.

Furthermore, with the increase in the number of photolithography processes, especially photolithography processes that require highly accurate mask alignment, an increase in the number of defects in devices is unavoidable, so there is a limit to the improvement in device manufacturing yield. Ta.

The present invention has been made in view of the above circumstances, and its purpose is to reduce the area occupied by a composite element of a bipolar transistor and an insulated gate field effect transistor, improve the degree of integration, and miniaturize the device. The aim is to improve performance such as speeding up.

Another object of the present invention is to determine the mutual positions of each impurity region and each electrode constituting an element with high precision,
The present invention also aims to improve the manufacturing yield and device performance of the composite device by reducing the number of photolithography steps that require highly accurate mask alignment.

In order to achieve such an object, a semiconductor device according to the present invention is constructed by integrating a bipolar transistor and an insulated gate field effect transistor without separating them by an isolation region, and also has a drain connected to a base electrode. The structure also serves as a lead-out region, and the source, drain, gate, and emitter electrodes, each made of a semiconductor, are separated from each other by an insulating film formed on their outer surfaces by thermal oxidation. In manufacturing, the main components are formed in a self-aligned manner by forming a semiconductor electrode using a lift-off technique and diffusing impurities from the semiconductor electrode. Hereinafter, a semiconductor device and a method for manufacturing the same according to the present invention will be explained in detail using Examples.

FIG. 1 is a sectional view showing an embodiment of a semiconductor device according to the present invention. In the figure, an N-type epitaxial silicon layer 2 is provided on a P-type silicon wafer 1 as a semiconductor substrate having a first conductivity type.
Therein, a transistor forming region 3, an N-type collector electrode lead-out region 4, and a P-type impurity region 5 for element isolation are provided. The transistor forming region 3 is separated from a transistor forming region of an adjacent element (not shown) by a silicon dioxide film 6 as a dielectric for element isolation, an impurity region 5 for element isolation, and a silicon wafer 1. ing. Note that when the bottom of the silicon dioxide film 6 reaches the silicon wafer 1, the element isolation impurity region 5 is not necessary. Furthermore, in the figure, the transistor forming region 3 and the collector electrode lead-out region 4 are separated by a silicon dioxide film 6'.
It is also possible to omit the silicon dioxide film 6' and configure the collector electrode lead-out region 4 within the transistor forming region. A P-type base diffusion region 8 as an impurity region having a second conductivity type is provided on the main surface 7 side of the transistor forming region 3. Furthermore, an emitter electrode 9 made of an N-type polycrystalline silicon film is provided on the main surface 7a of the base diffusion region 8 among the main surfaces 7 of the transistor forming region 3, and the main surface excluding the base diffusion region 8 is provided with an emitter electrode 9 made of an N-type polycrystalline silicon film. A source electrode 10 made of a P-type polycrystalline silicon film is provided on the main surface 7b, and a drain electrode 11 made of a P-type polycrystalline silicon film is provided spanning both main surfaces 7a and 7b. Further, in the transistor forming region 3, an emitter 1 made of an N-type silicon film formed by diffusing impurities from the emitter electrode 9 is provided.
2. A source 13 made of a P-type silicon film formed by diffusing impurities from the source electrode 10, and a drain 14 made of a P-type silicon film formed by diffusing impurities from the drain electrode 11. Here, the emitter is constructed within the base diffusion region 8. Such transistor configuration region 3
Of these, if the region excluding the base diffusion region 8 is defined as the collector 15 and the region of the base diffusion region 8 excluding the emitter 12 is defined as the base 16, then the emitter 12, the base 16 and the collector 15
NPN bipolar transistor can be configured. Here, the source 13 is formed within the collector 15. Further, the drain 14 is formed astride both the base diffusion region 8 and the collector 15 and also serves as a region for leading out the base electrode, and the drain electrode 11 also serves as the base electrode.
Further, a collector electrode 17 made of an N-type polycrystalline silicon film is provided on the main surface of the collector electrode extraction region 4. Further, in the transistor forming region 3, the region sandwiched between the source 13 and the drain 14 is defined as a channel region 18, and a polycrystalline silicon film or a metal film is formed on the main surface of the channel region 18 via a gate insulating film 19 made of a silicon dioxide film. A gate electrode 20 made of a film is provided. Here, since the source electrode 10 and the drain electrode 11 are made of a polycrystalline silicon film, by thermally oxidizing their outer surfaces, the first insulating coatings 21 and 22 made of a silicon dioxide film are formed.
can be formed. Therefore, the source electrode 10 and the gate electrode 20 are connected to each other by the first insulating coating 21 on the outer surface of the source electrode, and the drain electrode 11 and the gate electrode 20 are connected to each other by the first insulating coating 21 on the outer surface of the drain electrode.
Further, the emitter electrode 9 and the drain electrode 11 are also separated by a first insulating film 22 on the outer surface of the drain electrode. As a result, a PMOS insulated gate field effect transistor including the source 13, drain 14, gate electrode 20, gate oxide film 19, and channel region 18 can be constructed.

Note that normally used values can be applied to the impurity concentration, junction depth, and thickness of the epitaxial silicon layer, polycrystalline silicon film, silicon dioxide film, etc. in each of the above-mentioned impurity regions.

As mentioned above, in the semiconductor device of FIG. 1, the emitter 12, base 16, and collector 15 that constitute the NPN bipolar transistor,
The source 13, drain 14, and channel region 18 constituting the PMOS insulated gate field effect transistor can be separated from each other by an isolation region.
The semiconductor electrodes of the emitter electrode 9, the base electrode, that is, the drain electrode 11, the source electrode 10, and the gate electrode 20 are formed on the main surface 7 of the transistor forming region 3. is forming. The emitter 12, source 13, and drain 14 are the emitter electrode 9, source electrode 10, and drain electrode 11, respectively.
The source electrode 10 is formed between the semiconductor electrodes by impurity diffusion from the source electrode 10.
and are separated by first insulating films 21 and 22 obtained by thermally oxidizing the outer surface of the drain electrode 11. For this reason, the source 1 with respect to the source electrode 10
3. The drain 14 is positioned with respect to the drain electrode 11 and the emitter 12 is positioned with respect to the emitter electrode 9 in a self-aligned manner, and the source electrode 10
and the gate electrode 2 with respect to the drain electrode 11.
0, the emitter electrode 9 is formed in a self-aligned manner with respect to the drain electrode 11. Furthermore, since the drain 14 also serves as a region for drawing out the base electrode, the base (drain)
A base electrode extraction region (drain) 14 is formed in a self-aligned manner with respect to the electrode 11 and the emitter 12, respectively.

FIG. 2 shows an equivalent circuit of the semiconductor element shown in FIG. 1. That is, in FIG. 2, Q1 represents an NPN bipolar transistor, and Q2 represents a PMOS insulated gate field effect transistor. As described above, since the drain 14 also serves as the region for leading out the base electrode, the drain 14 of Q2 and the base 16 of Q1 have approximately the same potential. Furthermore, since the channel region 18 is formed within the collector 15, the back gate potential of Q2 is approximately the same potential as the potential of the collector 15 of Q1. Furthermore, source 13 of Q2 and Q1
Since a PN junction is formed between the collector 15 of the PN junction diode D1, the PN junction diode D1 exists.

In the above embodiment, the peripheral part of the emitter electrode 9 is overlapped on the drain electrode 11, but conversely, the peripheral part of the drain electrode can be overlapped on the emitter electrode. is also possible. In the latter case, the outer surface of the emitter electrode made of a polycrystalline silicon film is thermally oxidized to form a second insulating film made of a silicon dioxide film, thereby separating the emitter electrode and the drain electrode. .

Furthermore, in the embodiment described above, the base 16
Both of the emitter 12 and the emitter 12 are in contact with the silicon dioxide film 6 for isolation between elements, but by surrounding the side surface of the emitter 12 with a region for leading out the base electrode, that is, the drain 14, the emitter 12 is brought into contact with the silicon dioxide film 6. It is also possible to have a configuration in which there is no direct contact. In such a case, the emitter electrode 9 is surrounded by the base electrode, that is, the drain electrode 11 on the main surface 7 of the transistor forming region 3 .

FIG. 3 is a cross-sectional view showing a semiconductor device during each step in an embodiment of the method for manufacturing a semiconductor device according to the present invention. In other words, the figure shows an NPN bipolar transistor and a PMOS transistor, similar to that shown in Figure 1.
A case is shown in which a semiconductor device is manufactured as a composite device with an insulated gate field effect transistor. A detailed explanation will be given below step by step.

First Step [FIG. 3A] A region for forming a transistor is formed in a semiconductor substrate having a first conductivity type, with elements separated by a dielectric.

That is, first, as shown in FIG. 3A, an N-type epitaxial silicon layer 32 as a semiconductor substrate having a first conductivity type is placed on a P-type silicon wafer 31.
form. Next, a P-type impurity is diffused into the element isolation region from the main surface side of the epitaxial silicon layer 32 to form an element isolation impurity region 33. Furthermore, by an isoplanar method using a silicon nitride film 34, a first silicon dioxide film 35 as a dielectric for isolation between elements, a region for forming a transistor 36, and a region for leading out a collector electrode 37 are formed.
A second silicon dioxide film 38 is formed at the same time. Although two masks are required for the impurity diffusion method and the isoplanar method, highly accurate mask alignment is not required between them. Here, the lower side of the silicon nitride film 34 has a film thickness of 50 nm in advance.
A thin third silicon dioxide film 39 is laid down. This third silicon dioxide film 39
serves to protect the epitaxial silicon layer 32 when the silicon nitride film 34 is plasma etched later. Here, the phosphorus concentration of the epitaxial silicon layer 32 is 10 ¹⁶ /cm ³ and the film thickness is
3 μm, the boron concentration of the impurity region 33 for element isolation is 10 ¹⁸ /cm ³ , and the thickness of the silicon nitride film 34 is
100nm, first and second silicon dioxide films 3
It is preferable that the thickness of the layers 5 and 38 be 2 μm.

Next, phosphorus ions are implanted into the collector electrode extraction region 37 through the silicon nitride film 34 using an ion implantation mask made of aluminum. In this case, highly accurate mask alignment is not required in the photolithography process for forming the ion implantation mask. Next, after removing the ion implantation mask, heat treatment is performed at 1100° C. to give a phosphorus concentration of 10 ¹⁹ /cm ³ .

Note that the second silicon dioxide film 38 may be omitted depending on the intended use of the device. Furthermore, if the bottom of the first silicon dioxide film 35 reaches the silicon wafer 31, it goes without saying that the element isolation impurity region 33 can be omitted.

Second Step [FIG. 3B] An oxidation-resistant layer pattern is formed on the main surface of the transistor forming region using an etching mask.

That is, in the first stage, the silicon nitride film 34, which is an oxidation-resistant layer, remains on the main surfaces of the transistor forming region 36 and the collector electrode drawing region 37. A photoresist pattern 40 is formed on this main surface by a photolithography process as shown in FIG. 3B. Next, using the photoresist pattern 40 as an etching mask, the silicon nitride film 34 on the transistor forming region 36 is etched with _CF4 gas plasma.
etching. Subsequently, the third silicon dioxide film 39 below it is coated with buffered liquid (HF: 1,
NH ₃ F: 3.5, H ₂ O: 6.5) to form a photoresist pattern 40 - silicon nitride film 34 -
A three-layer pattern consisting of a third silicon dioxide film 39 is formed.

In addition, although the case where the oxidation-resistant pattern is formed using the silicon nitride film 34 formed in the first step as it is has been described above, the silicon nitride film 34
4 may be removed in the first step, and a new silicon nitride film may be formed in this step. In such a case, there is an advantage that phosphorus ions can be implanted into the collector electrode extraction region 37 without passing through the silicon nitride film 34.

Third step [Figure 3C] A semiconductor layer having the second conductivity type is formed on the main surface of the transistor component region in which the etching mask and the oxidation-resistant layer pattern are mounted, and then the etching mask is removed. By doing so, only the portion of the semiconductor layer on the etching mask is selectively removed, and the remaining portion forms a source electrode and a drain electrode.

That is, first, on the epitaxial silicon layer 32 on which the three-layer pattern formed in the second step is mounted, a P-type polyester having a poron concentration of 10 ²⁰ /cm ³ and a film thickness of 500 nm is formed as a semiconductor layer having a second conductivity type. A crystalline silicon film (first polycrystalline silicon film) is formed by sputtering. In the sputtering method, the film formation temperature can be controlled to 200° C. or less, so damage such as pattern collapse or sticking is not caused to the photoresist pattern 40.

Next, by removing the photoresist pattern 40 using a resist stripping solution, only the portion of the first polycrystalline silicon film that was on the photoresist pattern 40 is selectively removed as shown in FIG. 3C. However, only the portions forming the source electrode 42 and drain electrode 43 are left. As a result, the silicon nitride film 34 as an oxidation-resistant layer remains in a self-aligned manner on the main surface of the transistor forming region 36 except for the source electrode 42 and the drain electrode 43.

Fourth step (FIG. 3D) Selective oxidation is performed leaving the oxidation-resistant layer pattern to form a first insulating film on the outer surfaces of the source and drain electrodes.

That is, first, oxidation treatment is performed in steam at 900℃,
As shown in FIG. 3D, the outer surface of the first polycrystalline silicon film constituting the source electrode 42 and drain electrode 43 is covered with a fourth silicon dioxide film 44 having a thickness of 300 nm. This fourth silicon dioxide film 44 becomes the first insulating film. In this case, since there is a silicon nitride film 34 as an oxidation-resistant layer on the epitaxial silicon layer 32, the main surface of the epitaxial silicon layer 32 is not oxidized.

Fifth Step [FIG. 3E] Impurities are diffused from the source electrode and drain electrode into the transistor forming region to form a source and a drain.

That is, as shown in FIG. 3E, a source 45 and a drain 46 having a junction depth of 500 nm and a boron concentration of 10 ²⁰ /cm ³ can be formed in a self-aligned manner by heat treatment at 1000° C.

Note that photolithography processing is not required in the third to fifth steps described above.

Sixth step [Figure 3F] The oxidation-resistant layer on the main surface of the channel region, which is the region sandwiched between the source and drain in the transistor forming region, is removed, and a gate insulating film is formed on the surface of the channel region. A gate electrode is further formed to cover the gate insulating film.

That is, first, using a newly formed photoresist pattern (not shown) as an etching mask, only the portion of the silicon nitride film 34 on the main surface of the channel region 47 is etched using CF ₄ gas plasma as shown in FIG. 3F. remove. Here, the channel region 47 is a surface region of the transistor forming region 36 that is sandwiched between the source 45 and the drain 46 . In this case, photolithography processing also does not require highly accurate mask alignment. Next, the third silicon dioxide film 39 exposed under the removed silicon nitride film is removed using a buffer solution.
A channel region 47 as a part of the transistor forming region 36 is exposed to the surface. Next, after removing the photoresist, a fifth silicon dioxide film having a thickness of 60 nm is formed as a gate insulating film 48 on the surface of the channel region 47 by oxidation in dry oxygen at 1000°C. Next, a boron concentration of 10 ²⁰ /
After forming a P-type second polycrystalline silicon film with a thickness of 500 nm and a thickness of 500 nm, a gate electrode ⁴ made of this second polycrystalline silicon film is formed by photolithography.
form 9. In this case, photolithography processing also does not require highly accurate mask alignment. Here, the gate electrode 49 and the source electrode 42 are separated in a self-aligned manner by the fourth silicon dioxide film 44 on the surface of the source electrode, and the gate electrode 49 and the drain electrode 43 are separated on the surface of the drain electrode. They are separated by a fourth silicon dioxide film 44 in a self-aligned manner.

Note that the third silicon dioxide film 39 may be used as it is as the gate insulating film 48 without being removed. However, a gate insulating film 48 of better quality can be obtained by newly forming a thermal oxide film like the fifth silicon dioxide film described above. In addition, after forming this gate insulating film 48 and before forming the second polycrystalline silicon film, in order to adjust the threshold voltage of the PMOS insulated gate type field effect transistor, 10 ¹¹ /cm ³ It is also possible to ion-implant some boron or phosphorus.

Seventh step [Figure 3 G] In the transistor forming region, an impurity region having the second conductivity type and connected to the drain is formed by implanting impurities from the main surface side, and at the same time, an impurity region is formed in the main surface of the transistor forming region. The overlying oxidation-resistant layer is removed and a third insulating film is formed on the outer surface of the gate electrode.

That is, first, by oxidation in dry oxygen at 900°C, a third layer is formed on the outer surface of the gate electrode 49 as shown in FIG. 3G.
a sixth silicon dioxide film 50 as an insulating film;
form. Next, all remaining silicon nitride film 34 is removed by CF ₄ gas plasma. Next, using the source electrode 42 and drain electrode 43 and the second polycrystalline silicon film 49, which have already been formed of the second silicon dioxide film, as masks, boron ions are implanted into the transistor forming region 36 in a self-aligned manner. Subsequently, heat treatment is performed at 1000° C. to form a base diffusion region 51 consisting of an impurity region with a boron concentration of 10 ¹⁸ /cm ³ and a junction depth of 60 nm.
Both the base diffusion region 51 and the drain 46 are of P type and overlap each other. Through this ion implantation step, boron is also implanted into the collector electrode extraction region 37, but there is no particular problem because the phosphorus concentration in the collector electrode extraction region 37 is higher. No photolithography process is required at this stage.

Note that here, the base diffusion region 51 is
A source electrode 42 and a drain electrode 4 are formed in a self-aligned manner with respect to the emitter formed in the step.
Although the base diffusion region 51 is formed after the formation of the gate electrode 49 and the gate electrode 49, if one photomask is added, the base diffusion region 51 can be formed before forming these electrodes, for example, the second
It is also possible to form this base diffusion region 51 by ion implantation between the step and the third step.

Further, the thermal diffusion treatment in the fifth stage may be omitted and also used as the heat treatment in this stage.

Eighth step [Figure 3H] The surface of the impurity region is exposed and an opening is provided,
An emitter electrode made of a semiconductor having a first conductivity type is formed to cover this opening.

That is, first, the third silicon dioxide film 39 on the surfaces of the base diffusion region 51 and the collector electrode extraction region 37 is removed using a buffer solution, and openings are provided to expose the surfaces of both regions. Next, arsenic is added by vapor phase growth or sputtering.
The thickness of the third polycrystalline silicon film doped with 10 ²⁰ / ^cm3
Form to 500nm. Then, through a photolithography process, an emitter electrode 52 and a collector electrode 53 made of a third polycrystalline silicon film are formed to cover the opening, as shown in FIG. 3H. This photolithography process also does not require highly accurate mask alignment. In addition, the emitter electrode 52
and the drain electrode 43 are separated in a self-aligned manner by a fourth silicon dioxide film 44 on the surface of the drain electrode.

In addition, in the seventh step, boron ion implantation and base diffusion region 5 are performed while leaving the silicon nitride film 34.
1 can also be formed, but in that case, it is necessary to remove the silicon nitride film 34 at the beginning of this step in order to provide an opening on the surface of the base diffusion region 51.

Ninth Step [FIG. 3] Impurities are diffused from the emitter electrode into the impurity region to form an emitter.

That is, by heat treatment at 1000°C, the emitter electrode 5
Arsenic is diffused from 2 into the base diffusion region 51, and the arsenic concentration is 10 ²⁰ /
cm ³ and a junction depth of 300 nm, an emitter 54 is formed.
At the same time, arsenic is diffused from the collector electrode 53 into the collector electrode extraction region 37, making it easier to establish ohmic contact with the collector electrode. No photolithography process is required at this stage.

Note that the heat diffusion treatment in the fifth and seventh stages may be omitted and may also be used as the heat treatment in this stage. In this case, the source 45, drain 46, emitter 5
4. The base diffusion region 51 is formed at the same time in this step. Therefore, in that case, boron as an impurity is ion-implanted into the transistor forming region 36, and the region where the base diffusion region 51 is to be formed later becomes an impurity region.

In FIG. 3, a region of the base diffusion region 51 excluding the emitter 54 is defined as a base 55, and a region of the base diffusion region 51 of the transistor forming region 36 is defined as a base 55.
If the area excluding 1 is the collector 56, an NPN consisting of the emitter 54, the base 55, and the collector 56
A bipolar transistor is configured. Furthermore, the source 45, drain 46, gate electrode 49, gate insulating film 48, and channel region 47 provide
A PMOS insulated gate field effect transistor is constructed. Here, the drain 46 also serves as a region for leading out the base electrode, and the drain electrode 43 also serves as the base electrode.

Although a P-type polycrystalline silicon film is used as the gate electrode 49 in FIG. 3, if the gate electrode 49 is formed of an N-type polycrystalline silicon film, the emitter electrode 52 and the gate electrode 49
can be formed simultaneously. In this case, the formation of the gate electrode 49 is omitted in the sixth step,
The silicon nitride film 34 on the main surface of the channel region 47 and on the main surface of the portion where the base diffusion region is to be formed is removed to form a thermal oxide film. Next, in a seventh step, a base diffusion region 51 is formed by ion implantation using a photoresist as a mask. Furthermore, the eighth
In the step, after removing the thermal oxide film on the main surface of the base diffusion region 51 while leaving the thermal oxide film on the main surface of the channel region 47 as the gate insulating film 48, a gate electrode made of an N-type polycrystalline silicon film is removed. 49 and an emitter electrode 52 are formed.

Another embodiment of the method for manufacturing a semiconductor device according to the present invention will be described with reference to FIG. This example is also an example of manufacturing a semiconductor device consisting of a composite element of an NPN bipolar transistor and a PMOS insulated gate field effect transistor, similar to the above-mentioned example (hereinafter referred to as the first example). A detailed explanation of the steps will be omitted, and only the differences will be shown. Similarly, in FIG. 4, the same or corresponding parts as in FIG. 3 are designated by the same symbols, and detailed explanation thereof will be omitted.

First stage [Fig. 4A] A region for forming a transistor separated between elements by a first silicon dioxide film 35 as a dielectric on an N-type epitaxial silicon layer 32 as a semiconductor substrate having a first conductivity type. form 36. The details of the process are the same as the first stage of the first embodiment.

Second Step [FIG. 4B] A silicon nitride film 34 as a first oxidation-resistant layer pattern is formed on the main surface of the transistor forming region 36 using a first etching mask consisting of a photoresist pattern 40. . Although the pattern is different, the details of the process are the same as in the second stage of the first embodiment.

Third Step [FIG. 4C] An impurity region having the second conductivity type is formed in the transistor forming region 36 by implanting impurities from the main surface side.

That is, boron ions are implanted using the photoresist pattern 40 as a mask to form a boron implanted region 70 as an impurity region, as shown in FIG. 4C. In addition, due to the heat treatment in the later 6th step,
The boron in this boron implanted region 70 is diffused to form a base diffusion region 71 which also serves as an impurity region. In this embodiment, boron ions were implanted in this step in order to form the base diffusion region 71 in a self-aligned manner with respect to the emitter formed in the sixth step. However, by increasing the number of photomasks by one, it is also possible to form the base diffusion region 71 by ion implantation between the first stage and the second stage.

Fourth Step [FIG. 4D] On the main surface of the transistor forming region 36 on which the photoresist pattern 40 as the first etching mask and the silicon nitride film 34 as the first oxidation-resistant layer pattern are mounted, a By forming a first semiconductor layer having one conductivity type and then removing the photoresist pattern 40 serving as a first etching mask, only the portion of the first semiconductor layer that is on the first etching mask is removed. is selectively removed, and the remaining portion is used to form an emitter electrode 72 on the main surface of the boron implanted region 70 as the impurity region.

This step is basically the same as the third step of the first embodiment, but instead of the semiconductor layer having the second conductivity type in the first embodiment, a first semiconductor layer having the first conductivity type is used. A third polycrystalline silicon film with an arsenic concentration of 10 ²⁰ /cm ³ and a film thickness of 500 nm is used as the third polycrystalline silicon film, and this third polycrystalline silicon film left on the main surface of the boron implanted region 70 constitutes the emitter electrode 72. It is something. Further, by removing the photoresist pattern 40, the silicon nitride film 34 as an oxidation-resistant layer is left in a self-aligned manner on the main surface of the transistor forming region 36 except for the emitter electrode 72. At the same time, the collector electrode extraction area 37
A collector electrode 73 is formed by the third polycrystalline silicon film left on the main surface.

Fifth step [Figure 4E] Selective oxidation is performed while leaving the silicon nitride film 34 as the first oxidation-resistant layer pattern, and the emitter electrode 7
A seventh silicon dioxide film 74 as a second insulating film is formed on the outer surfaces of the silicon dioxide film 2 and the collector electrode 73 .

This is because, in the fourth step of the first embodiment, a fourth silicon dioxide film 4 is formed as a first insulating film on the outer surfaces of the source electrode 42 and the drain electrode 43.
It can be carried out by the same process as that for forming No. 4.

Sixth step [FIG. 4E] Impurities are diffused from the emitter electrode 72 to the boron implanted region 70 as an impurity region to form the emitter 54.
form.

This can be carried out by a heat treatment process similar to the fifth step of the first embodiment. Note that, as described in the third step, the base diffusion region 71 can also be formed by this heat treatment, and thereafter the base diffusion region becomes an impurity diffusion region.

No photolithography process is required in the steps 3 to 6 above.

Seventh step [FIG. 4F] On the main surface of the transistor forming region 36, the silicon nitride film 34 as the first oxidation-resistant layer is etched using the second etching mask, and the second oxidation-resistant layer is etched. A layer pattern 80 is formed.

That is, up to the sixth stage, the first oxidation-resistant layer pattern made of the silicon nitride film 34 remains on the main surface of the portion of the transistor forming region 36 excluding the emitter electrode 72. This is etched using the photoresist pattern 79 as a second etching mask in the same process as the second step of the first embodiment to form a second oxidation-resistant layer pattern 80.

Eighth Step [FIG. 4G] A photoresist pattern 79 serving as a second etching mask and a second oxidation-resistant layer pattern 80 are mounted on the main surface of the transistor forming region 36 having a first conductivity type. The second semiconductor layer is formed by forming a second semiconductor layer and then removing the photoresist pattern 79.
Of the semiconductor layer, only the portion on the second etching mask is selectively removed, and the remaining portion forms a source electrode 75 and a drain electrode 76.

The details of this process are the same as the third stage of the first embodiment. However, instead of the semiconductor layer having the second conductivity type in the first embodiment, a P-type first polycrystalline silicon film is used as the second semiconductor layer having the first conductivity type. A part of the drain electrode 76 formed here is on the emitter electrode 72, and both electrodes are separated by the seventh silicon dioxide film 74 on the outer surface of the emitter electrode.

Ninth Step [FIG. 4H] Impurities are diffused from the source electrode 75 and the drain electrode 76 into the transistor forming region 36 to form the source 45 and the drain 46, respectively.

This step can be performed in the same manner as the fifth step of the first embodiment. Here, the drain 46 is formed to be connected to the base diffusion region 71 as an impurity region.

Note that the heat treatment in the sixth stage may be omitted and the heat treatment in this stage may also be used.

Tenth step (FIG. 4H) Selective oxidation is performed using the second oxide layer pattern 80 as a mask, and a first insulating film made of an eighth silicon dioxide film 77 is formed on the outer surfaces of the source electrode 75 and drain electrode 76. Form.

That is, up to the ninth stage, the second oxide layer pattern 80 as a part of the silicon nitride film remains on the main surface of the channel region 47 in the transistor forming region 36. The following steps can be carried out in the same manner as in the case where the first insulating film made of the fourth silicon dioxide film 44 was formed in the fourth step of the first embodiment.

No photolithography process is required in the 8th to 10th steps.

Eleventh step (FIG. 4) The second oxide layer pattern 80 is removed and the source 45 is removed.
A gate insulating film 48 is formed on the surface of the channel region 47 sandwiched between the gate electrode 47 and the drain 46, and a gate electrode 78 covering the gate insulating film 48 is further formed.

This process can be performed in the same process as that for forming the gate electrode 49 in the sixth step of the first embodiment. Here, the gate electrode 78 can also be formed of a P-type or N-type second polycrystalline silicon film or a metal film. The photolithography process in this case does not require highly accurate mask alignment.

Through the above steps, a semiconductor element consisting of a composite element of an NPN bipolar transistor and a PMOS insulated gate field effect transistor can be formed, as in the first embodiment.

It goes without saying that in both of the embodiments described above, it is possible to make slight changes to the details of the process, such as the order of heat treatment, the type of impurity, the thickness of the semiconductor layer or the insulating layer, etc.

Furthermore, in the above-described embodiments, a semiconductor device consisting of a composite element of an NPN bipolar transistor and a PMOS insulated gate field effect transistor and a method for manufacturing the same were described.
It goes without saying that a semiconductor element consisting of a composite element of a PNP bipolar transistor and an NMOS insulated gate field effect transistor can be formed in exactly the same manner.

As described above, according to the semiconductor device and the method for manufacturing the same according to the present invention, the emitter, base, and collector of the bipolar transistor constituting the device and the source, drain, and channel region of the insulated gate field effect transistor are separated between the devices. It is formed integrally in one transistor forming region without being separated by a storage region, and also serves as a region for leading out the drain and base electrodes, and the emitter electrode, base electrode, source electrode, drain electrode, and gate electrode of the transistor. By forming it on the main surface of the configuration region, the area occupied by the element can be reduced and the degree of integration can be improved. Furthermore, by separating the electrodes by an insulating film formed by thermally oxidizing their outer surfaces, each electrode and each impurity region can be positioned in a self-aligned manner with respect to each other, so that As the positional accuracy becomes more accurate and the amount of deviation during mask alignment becomes smaller, the area occupied by the composite element made up of both transistors can be further miniaturized. Therefore, improvements in operating characteristics associated with miniaturization, such as faster operation of bipolar transistors due to reductions in base-collector junction capacitance and base resistance, and improvements in insulated gate type electric field due to reductions in capacitance between the source or drain and the substrate. It is possible to speed up the operation of the effect transistor, and also to speed up the operation of the composite element by eliminating the need for wiring connecting the drain and base.

Further, according to the method of manufacturing a semiconductor device according to the present invention, only two photomasks, a mask for a dielectric pattern for element isolation and a mask for a source electrode and a drain-base electrode pattern, or an emitter electrode pattern are used for this. With only 3 photomasks including 1 mask, emitter, base, collector, base electrode extraction area, source, drain,
The pattern dimensions of the main constituent parts of the device, such as the channel region and the gate insulating film, can be determined in a self-aligned manner, and there is no need for highly accurate mask alignment other than the alignment of these two or three masks. Therefore, it has various excellent effects, such as reducing the occurrence of device defects and variations in device characteristics associated with the photolithography process, and improving the manufacturing yield and performance of devices.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing one embodiment of a semiconductor device according to the present invention, FIG. 2 is an equivalent circuit diagram thereof, and FIGS. FIG. 2 is a cross-sectional view showing a semiconductor element during a manufacturing process. 2, 32...Epitaxial silicon layer, 3,
36...Transistor configuration area, 4, 37...
Collector electrode extraction region, 5, 33... Impurity region for element isolation, 6, 6', 35, 38, 39,
44, 50, 74, 77... silicon dioxide film,
7...Main surface of transistor forming region, 7a...
Main surface of base diffusion region among 7, 7b...main surface excluding 7a among 7, 8, 51, 71... base diffusion region, 9, 52, 72... emitter electrode, 1
0,42,76...source electrode, 11,43,7
5...Drain electrode, 12,54...Emitter,
13,45...source, 14,46...drain, 15,56...collector, 16,55...base, 17,53,73...collector electrode, 1
8, 47... Channel region, 19, 48... Gate insulating film, 20, 49, 78... Gate electrode, 2
1, 22... Insulating film, 34... Silicon nitride film, 40, 79... Photoresist pattern, 70...
...Boron implantation region, 80...Oxide layer pattern, Q1
... Bipolar transistor, Q2 ... Insulated gate field effect transistor.

Claims (1)

[Claims] 1. A semiconductor substrate having a first conductivity type, having a transistor forming region formed with elements separated by a dielectric, and a second conductive type formed on the main surface side of the transistor forming region. an emitter electrode made of a semiconductor having a first conductivity type formed on a main surface of the impurity region; and an emitter electrode of a second conductivity type formed on the main surface of the transistor forming region excluding the impurity region. a source electrode made of a semiconductor, a drain electrode made of a semiconductor having a second conductivity type formed over the main surface of the impurity region and the transistor forming region excluding the impurity region, and the emitter electrode in the impurity region. an emitter formed by diffusing impurities from an electrode; a source and a drain formed by diffusing impurities from the source electrode and the drain electrode into the transistor forming region; thermally oxidizing the gate insulating film formed on the main surface of the channel region consisting of the surface region of the transistor forming region, the gate electrode formed on the gate insulating film, and the outer surfaces of the drain electrode and the source electrode; a first insulating film formed between the drain and source electrodes and the gate electrode; separated by a second insulating film formed by thermally oxidizing the emitter, a base consisting of the impurity region excluding the emitter, and a collector consisting of the transistor forming region excluding the impurity region. 1. A semiconductor device comprising a transistor and an insulated gate field effect transistor formed from the source, drain, and gate electrode. 2. A transistor forming region formed on a semiconductor substrate having a first conductivity type with element isolation, an impurity region having a second conductivity type formed on the main surface side of the transistor forming region, and an impurity region within the impurity region. an emitter having a first conductivity type formed therein; a source having a second conductivity type formed in the transistor formation region excluding the impurity region; and a source having a second conductivity type formed in the transistor formation region excluding the impurity region A gate insulating film formed on the main surface over a channel region consisting of a drain having a second conductivity type formed over the main surface, and a surface region of the transistor forming region sandwiched between the source and the drain. A bipolar transistor is formed from a gate electrode formed on the gate insulating film, the emitter, a base consisting of the impurity region excluding the emitter, and a collector consisting of the transistor forming region excluding the impurity region. 1. A semiconductor device comprising: an insulated gate field effect transistor formed from the source, drain, and gate electrode. 3. Forming a transistor forming region in which elements are separated by a dielectric in a semiconductor substrate having a first conductivity type, and forming an oxidation-resistant layer pattern on the main surface of the transistor forming region using an etching mask. After forming a semiconductor layer having the second conductivity type on the main surface of the transistor forming region on which the etching mask and the oxidation-resistant layer pattern are mounted, removing the etching mask, A step of selectively removing only a portion of the semiconductor layer located on the etching mask to form a source electrode and a drain electrode made of the semiconductor layer, and performing selective oxidation using the oxidation-resistant layer pattern as a mask. a step of forming an insulating film on the outer surface of the source electrode and the drain electrode; a step of forming the source and the drain by diffusing impurities from the source electrode and the drain electrode into the transistor forming region, respectively; A step of forming a gate electrode on the main surface of the region sandwiched between the source and the drain in the structure region through a gate insulating film, and implanting an impurity into the transistor structure region from the main surface side. forming an impurity region having a second conductivity type and connected to the drain, forming an emitter electrode made of a semiconductor having a first conductivity type on the main surface of the impurity region; forming an emitter by diffusing an impurity from an electrode to the impurity region, the base comprising the emitter, the impurity region excluding the emitter, and the transistor forming region excluding the impurity region. 1. A method of manufacturing a semiconductor device, comprising configuring a bipolar transistor having a collector, and configuring an insulated gate field effect transistor having the source, drain, and gate electrode. 4. Forming a transistor forming region in which elements are separated by a dielectric in a semiconductor substrate having a first conductivity type, and forming a first etching pattern on the main surface of the transistor forming region using a first etching pattern. a step of forming an oxidation-resistant layer pattern; a step of forming an impurity region having a second conductivity type in the transistor forming region by implanting impurities from the main surface side; After forming a first semiconductor layer having a first conductivity type on the main surface of a transistor forming region equipped with an oxidation-resistant layer pattern, the first semiconductor layer is removed by removing the first etching mask. The emitter electrode is formed by selectively removing only the portion on the first etching mask and forming the emitter electrode with the remaining portion, and performing selective oxidation while leaving the first oxidation-resistant layer pattern. forming an insulating film on the outer surface of the electrode; forming an emitter by diffusing impurities from the emitter electrode into the impurity region; and etching a second etching film on the main surface of the transistor forming region. a step of forming a second oxidation resistant layer pattern by etching the first oxidation resistant layer pattern using a mask; and a step of forming a second oxidation resistant layer pattern using the second etching mask and the second oxidation resistant layer pattern. After forming a second semiconductor layer having the first conductivity type on the main surface of the mounted transistor forming region, the second etching mask is removed to remove the second semiconductor layer from the second semiconductor layer. selectively removing only a portion on the etching mask and forming a source electrode and a drain electrode using the remaining portion; and diffusing impurities from the source electrode and drain electrode into the transistor forming region, respectively. After forming the source and drain by forming the source and drain, the method includes a step of connecting the drain to the impurity region, and a step of forming a gate electrode between the source electrode and the drain electrode, and forming the emitter and the emitter. An insulated gate field effect transistor having an insulated gate field effect transistor comprising a base consisting of the impurity region excluding the impurity region and a collector consisting of the transistor forming region excluding the impurity region forming a bipolar transistor, and the source and drain and the gate electrode. A method for manufacturing a semiconductor device, characterized in that it constitutes an effect transistor. 5. Forming a region for forming a transistor separated between elements in a semiconductor substrate having a first conductivity type, and forming a source and a drain having a second conductivity type by diffusing impurities into each of the regions for forming a transistor. forming a gate electrode on the main surface of the region sandwiched between the source and drain in the transistor forming region via a gate insulating film; a step of forming an impurity region having a second conductivity type and connecting to the drain by implanting an impurity; and a step of forming an emitter having a first conductivity type by diffusing impurities into the impurity region. constitutes a bipolar transistor having the emitter, a base made of the impurity region excluding the emitter, and a collector consisting of the transistor forming region excluding the impurity region, and the source, drain, and gate electrode. 1. A method for manufacturing a semiconductor device, comprising configuring an insulated gate field effect transistor having: