JPS56114368A - Manufacture of semiconductor ic device - Google Patents

Manufacture of semiconductor ic device

Info

Publication number
JPS56114368A
JPS56114368A JP1692480A JP1692480A JPS56114368A JP S56114368 A JPS56114368 A JP S56114368A JP 1692480 A JP1692480 A JP 1692480A JP 1692480 A JP1692480 A JP 1692480A JP S56114368 A JPS56114368 A JP S56114368A
Authority
JP
Japan
Prior art keywords
type
region
layer
diffusion
regions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1692480A
Other languages
Japanese (ja)
Inventor
Tadashi Hirao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP1692480A priority Critical patent/JPS56114368A/en
Publication of JPS56114368A publication Critical patent/JPS56114368A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222Bipolar technology
    • H01L21/8226Bipolar technology comprising merged transistor logic or integrated injection logic

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To obtain the IC with no characteristic difference arising between output terminals by a method wherein when an electrode is formed on a base region in which a plurality of collector regions are formed, a common electrode by which all of the base regions exposed between the collector regions is formed. CONSTITUTION:An N<+> type burried region 2 is diffusion-formed on a P type Si substrate 1, an N<-> type layer 3 is epitaxially grown on the whole surface including the diffusion-formed region 2 and a thick insulating film 103 with a P type channel cut region 5 made as an underlay is formed on the periphery of the layer 3 and the layer 3 is separated in island-shape. Then, the island-shaped layer 3 is separated into two by the insulating film reaching the region 2 and a P<-> type base region 6 is formed by diffusion in one layer 3. Thereafter, N<+> type collector regions 9-11 are formed in the region 6 and an N<+> type electrode taking-out region 12 in the other layer 3 with polycrystalline Si 304-306 and 302 containing N type impurities as the diffusion sources, and heat-treated to change the surfaces of the polycrystalline diffusion sources to oxide films 106-110. Subsequently, P<+> type regions 8 are diffusion-formed in the regions 6 exposed between those films and cover-attached with the common base electrode 403.
JP1692480A 1980-02-13 1980-02-13 Manufacture of semiconductor ic device Pending JPS56114368A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1692480A JPS56114368A (en) 1980-02-13 1980-02-13 Manufacture of semiconductor ic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1692480A JPS56114368A (en) 1980-02-13 1980-02-13 Manufacture of semiconductor ic device

Publications (1)

Publication Number Publication Date
JPS56114368A true JPS56114368A (en) 1981-09-08

Family

ID=11929667

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1692480A Pending JPS56114368A (en) 1980-02-13 1980-02-13 Manufacture of semiconductor ic device

Country Status (1)

Country Link
JP (1) JPS56114368A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5989457A (en) * 1982-11-15 1984-05-23 Hitachi Ltd Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5989457A (en) * 1982-11-15 1984-05-23 Hitachi Ltd Manufacture of semiconductor device

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