JPS57115822A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS57115822A JPS57115822A JP169481A JP169481A JPS57115822A JP S57115822 A JPS57115822 A JP S57115822A JP 169481 A JP169481 A JP 169481A JP 169481 A JP169481 A JP 169481A JP S57115822 A JPS57115822 A JP S57115822A
- Authority
- JP
- Japan
- Prior art keywords
- region
- type
- substrate
- epitaxial layer
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/0257—Doping during depositing
- H01L21/02573—Conductivity type
- H01L21/02576—N-type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/0257—Doping during depositing
- H01L21/02573—Conductivity type
- H01L21/02579—P-type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
Abstract
PURPOSE:To enable the growth of a thin epitaxial layer for the subject semiconductor device by a method wherein an epitaxial layer is grown on a semiconductor crystal substrate, having a buried layer of high density impurities, after the substrate has been baked at a high temperature in hydrogen. CONSTITUTION:An N<+> type diffused buried layer 2 is formed on the prescribed region of a P type Si substrate 1. Then, the substrate 1 is baked at a high temperature in hydrogen. As a result, the density on the surface of region 2 is reduced, and an N type diffused buried layer 2 is formed. An N type epitaxial layer 3 is then formed on the entire surface of the substrate 1. At this time, an N type region 4, having a higher impurity density than the layer 3 and moved up a little from the region 2', is formed. Besides, a P type insulation spilt diffusion region 5, a P type base diffusion region 7, and an N type emitter diffusion region 8 are formed. Accordingly, as autodoping can be suppressed, and a high breakdown voltage between region 7 and region 2 can be maintained, thereby enabling the formation of a thin epitaxial layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP169481A JPS57115822A (en) | 1981-01-08 | 1981-01-08 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP169481A JPS57115822A (en) | 1981-01-08 | 1981-01-08 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57115822A true JPS57115822A (en) | 1982-07-19 |
Family
ID=11508631
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP169481A Pending JPS57115822A (en) | 1981-01-08 | 1981-01-08 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57115822A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5927521A (en) * | 1982-08-06 | 1984-02-14 | Hitachi Ltd | Fabrication of semiconductor substrate |
FR2766845A1 (en) * | 1997-07-31 | 1999-02-05 | Sgs Thomson Microelectronics | EPITAXY PROCESS ON A SILICON SUBSTRATE COMPRISING AREAS HIGHLY DOPED WITH ARSENIC |
WO2001035452A1 (en) * | 1999-11-10 | 2001-05-17 | Shin-Etsu Handotai Co., Ltd. | Production method for silicon epitaxial wafer and silicon epitaxial wafer |
-
1981
- 1981-01-08 JP JP169481A patent/JPS57115822A/en active Pending
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5927521A (en) * | 1982-08-06 | 1984-02-14 | Hitachi Ltd | Fabrication of semiconductor substrate |
JPH0361335B2 (en) * | 1982-08-06 | 1991-09-19 | Hitachi Ltd | |
FR2766845A1 (en) * | 1997-07-31 | 1999-02-05 | Sgs Thomson Microelectronics | EPITAXY PROCESS ON A SILICON SUBSTRATE COMPRISING AREAS HIGHLY DOPED WITH ARSENIC |
EP0897024A1 (en) * | 1997-07-31 | 1999-02-17 | STMicroelectronics SA | Process for epitaxy on a silicon substrate containing zones highly doped with arsenic |
US6162706A (en) * | 1997-07-31 | 2000-12-19 | Stmicroelectronics S.A. | Method of epitaxy on a silicon substrate comprising areas heavily doped with arsenic |
US6776842B2 (en) | 1997-07-31 | 2004-08-17 | Stmicroelectronics S.A. | Method of epitaxy on a silicon substrate comprising areas heavily doped with arsenic |
WO2001035452A1 (en) * | 1999-11-10 | 2001-05-17 | Shin-Etsu Handotai Co., Ltd. | Production method for silicon epitaxial wafer and silicon epitaxial wafer |
US6589336B1 (en) | 1999-11-10 | 2003-07-08 | Shin-Etsu Handotai Co., Ltd. | Production method for silicon epitaxial wafer and silicon epitaxial wafer |
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