JPS6240719A - Manufacture of epitaxial wafer - Google Patents
Manufacture of epitaxial waferInfo
- Publication number
- JPS6240719A JPS6240719A JP18066285A JP18066285A JPS6240719A JP S6240719 A JPS6240719 A JP S6240719A JP 18066285 A JP18066285 A JP 18066285A JP 18066285 A JP18066285 A JP 18066285A JP S6240719 A JPS6240719 A JP S6240719A
- Authority
- JP
- Japan
- Prior art keywords
- boron
- diffusing
- substrate
- diffusion
- specific portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はクリコン半導体素子を製造するためのクリコン
基板に関し、特に、ラッチアップ防止。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a crystalline silicon substrate for manufacturing a silicone semiconductor device, and in particular to prevention of latch-up.
ソフトエラー防止機能を持つ半導体素子製造を目的とす
るエビタキクアルウエーハに関fる。The present invention relates to Evita kiqual wafers for the purpose of manufacturing semiconductor devices with a soft error prevention function.
従来、この種のエビタキクアルウェーハは、P型または
N型の高濃度基板(比抵抗0.01〜0.02Ω・cr
ll)の上にエピタキシアル成長させる事によって製造
され、使用に供されていた。極端に高濃度のP型ウェー
ハ(比抵抗0001Ω・cIn)を使用した場合にはエ
ビ層に転位が入り、素子製造は不可能となり、従って結
晶基板自体の抵抗値を、0.01Ω・α以下にしたもの
は、実用的ではなかった。Conventionally, this type of Evita quali wafer has been manufactured using a P-type or N-type high concentration substrate (specific resistance 0.01 to 0.02Ω・cr).
It was manufactured by epitaxial growth on ll) and was put into use. If an extremely high concentration P-type wafer (specific resistance 0001Ω・cIn) is used, dislocations will occur in the shrimp layer, making it impossible to manufacture devices. Therefore, the resistance value of the crystal substrate itself should be set to 0.01Ω・α or less What we did was not practical.
上述した結晶基板比抵抗の制限は、特定の素子において
は、不都合が生ずる事が明らかになってきた。すなわち
、素子の回路中の一部において、動作中に伝導型がP型
からN型に反転しない事が必要であり、しかも、この回
路部分がエビ層から基板まで貫通して存在しており、こ
のためには基板のホウ素濃度がl x l Q”cII
L−’以上である事が必要となってきた。従って従来の
P/P エビタキシアルウエーハは、基板比抵抗が0
01〜002Ω・鑵であれば平均ホウ素濃度は6X10
”α′″3であシ、使用する事ができない。また001
Ω・a以下の結晶引上げは、技術的に全く不可能という
わけではないが、歩留りは低く、低価格、大量供給とい
う点については問題がある。It has become clear that the above-mentioned limitation on the specific resistance of the crystal substrate causes problems in certain devices. In other words, it is necessary that the conductivity type of a part of the circuit of the element does not reverse from P type to N type during operation, and furthermore, this circuit part exists penetrating from the shrimp layer to the substrate. For this purpose, the boron concentration of the substrate must be l x l Q”cII
It has become necessary to be at least L-'. Therefore, the conventional P/P epitaxial wafer has a substrate resistivity of 0.
If it is 01~002Ω/metal, the average boron concentration is 6X10
If it is "α'" 3, it cannot be used. Also 001
Although it is not technically impossible to pull crystals of Ω·a or less, the yield is low, and there are problems in terms of low price and mass supply.
本発明のエピタキシアルウェーハ・は、製造上着るしい
困難を伴わない001〜0.020・儂比抵抗のホウ素
添加のP型基板に対し、その全面または特定部分にホウ
素をl x l Q”CrrL−3以上拡散させた後、
エピタキシアル成長させた事を特徴とする。The epitaxial wafer of the present invention is a boron-doped P-type substrate with a specific resistance of 001 to 0.020, which does not cause any difficulty in manufacturing, and boron is added to the entire surface or a specific part of the substrate. - After spreading 3 or more,
It is characterized by epitaxial growth.
すなわち、伝導型の反転を防ぐ必要のある深さまで、ホ
ウ素を高濃度に拡散させれば、充分素子機能上問題は無
く、また回路上必要な特定部分へのみ拡散させるという
方法でも機能上充分である事が明らかになり、本発明に
到ったものである。能率的な拡散には熱拡散法が適して
おり、特定部分への拡散は酸化膜のマスク作用により達
成する事ができる。本発明の副次的な効果として、チョ
クラルスキー法基板のP型窩濃度基板における酸素起因
欠陥抑制のための酸素外方拡散を同時に生じさせる事が
できる。すなわち1200〜1100°Cでの熱拡散中
に、基板から固溶酸素が外方に拡散し、表面付近の酸素
濃度を低下させる事ができる。In other words, if boron is diffused at a high concentration to a depth that is necessary to prevent conduction type reversal, there will be no problem in terms of device functionality, and a method in which boron is diffused only to specific parts necessary for the circuit is also functionally sufficient. This discovery led to the present invention. A thermal diffusion method is suitable for efficient diffusion, and diffusion to a specific portion can be achieved by using the masking effect of an oxide film. As a secondary effect of the present invention, it is possible to simultaneously cause oxygen outward diffusion for suppressing oxygen-induced defects in the P-type cavity concentration substrate of the Czochralski method substrate. That is, during thermal diffusion at 1200 to 1100°C, solid solution oxygen diffuses outward from the substrate, making it possible to reduce the oxygen concentration near the surface.
低酸素濃度の領域は、その後に加えられる製造熱プロセ
ス中において欠陥を発生しにくくなり、素子の劣化を防
ぐ事ができる。拡散させるホウ素濃度及び深ざは、素子
構成に依存するが、かなり高濃度まで可能であり、この
上にエピタキシアル成長を欠陥を生じさせる事なし、行
う事ができる。A region with a low oxygen concentration is less likely to generate defects during the subsequent manufacturing heat process, and can prevent element deterioration. Although the concentration and depth of boron to be diffused depend on the device configuration, it is possible to achieve a considerably high concentration, and epitaxial growth can be performed thereon without causing defects.
面方位(100)、ホウ素添加0.01〜0.02Ω・
1のチョクラフレスキ法による単結晶ウェーハに対し、
ジボランを用いた熱拡散法によって拡散を行なった。ボ
ロンガラス被着後に、1200″Cで64時間アニール
し、ホウ素を約8μm深さまで拡散させた。拡散後に酸
化膜を除去し、2〜3μmのエビ層をジクロロ7ランガ
スを用いて形成した。Plane orientation (100), boron addition 0.01-0.02Ω・
For single-crystal wafers produced by the Czochlafleschi method in No. 1,
Diffusion was performed by thermal diffusion method using diborane. After the boron glass was deposited, it was annealed at 1200''C for 64 hours to diffuse boron to a depth of approximately 8 μm. After the diffusion, the oxide film was removed and a 2-3 μm thick layer was formed using dichloro7rane gas.
第1図は、本発明になるウェーハの断面図である。FIG. 1 is a cross-sectional view of a wafer according to the present invention.
図中の1は0.01〜0.02Ω・a比抵抗のP型基板
、2は1200’Oでホウ素を約8μn1拡散させた拡
散層、3は基板の上に成長させたエビ層を示す。このエ
ピタキシアルウェーハと、従来型のエピタキシアルウェ
ーハを用いて、素子を製造し、特性を比較した。所期の
目的通り、本発明によるエピタキシアルウェーハは伝導
型の反転を生じにくく、またエビ/基板界面での欠陥形
成が抑制された事に起因して、DRAMのホールド時間
(電荷保持時間)は、従来型エビウェーハに比べ3〜4
倍となり、著るしい向上を示した。In the figure, 1 indicates a P-type substrate with a specific resistance of 0.01 to 0.02 Ω・a, 2 indicates a diffusion layer in which approximately 8 μn1 of boron is diffused at 1200'O, and 3 indicates a shrimp layer grown on the substrate. . Devices were manufactured using this epitaxial wafer and a conventional epitaxial wafer, and their characteristics were compared. As intended, the epitaxial wafer according to the present invention is less likely to cause conduction type reversal, and the formation of defects at the shrimp/substrate interface is suppressed, so the hold time (charge retention time) of DRAM is shortened. , 3-4 compared to conventional shrimp wafer
This was a significant improvement.
以上説明したように、本発明は、エビ成長前にあらかじ
めホウ素を拡散することにより、素子の電気的特性の向
上及び欠陥発生抑制に著るしい効果がある。基板として
、製造の容易な範囲の比抵抗の基板を用い、大量処理の
容易な熱拡散法を使用している平から、本発明は次号に
産業上有効な方法を提供するものである。As explained above, the present invention has a significant effect on improving the electrical characteristics of the device and suppressing the occurrence of defects by diffusing boron before shrimp growth. The present invention provides an industrially effective method in which a substrate having a resistivity within a range that is easy to manufacture is used, and a thermal diffusion method that allows easy mass processing is used.
第1図は、本発明によるエピタキシアルウェーハの断面
図である。
1・・・・・・高濃度P型基板、2・・・・・・高濃度
拡散層、3・・・・・・エビ層。FIG. 1 is a cross-sectional view of an epitaxial wafer according to the present invention. 1... High concentration P type substrate, 2... High concentration diffusion layer, 3... Shrimp layer.
Claims (1)
結晶ウェーハに対し、その全面または特定部分にホウ素
を1×10^1^9cm^−^3以上拡散させた後、エ
ピタキシアル成長させたことを特徴とするエピタキシア
ルウェーハの製造方法。Boron is epitaxially grown on a boron-doped silicon single crystal wafer with a resistivity of 0.02 Ω・cm or less after diffusing boron to a depth of 1×10^1^9 cm^-^3 or more over the entire surface or a specific part of the wafer. A method for manufacturing an epitaxial wafer, characterized by:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18066285A JPS6240719A (en) | 1985-08-16 | 1985-08-16 | Manufacture of epitaxial wafer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18066285A JPS6240719A (en) | 1985-08-16 | 1985-08-16 | Manufacture of epitaxial wafer |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6240719A true JPS6240719A (en) | 1987-02-21 |
Family
ID=16087120
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP18066285A Pending JPS6240719A (en) | 1985-08-16 | 1985-08-16 | Manufacture of epitaxial wafer |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6240719A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01258414A (en) * | 1988-04-08 | 1989-10-16 | Nec Corp | Semiconductor device |
KR100579217B1 (en) * | 1999-10-26 | 2006-05-11 | 주식회사 실트론 | Method of manufacturing on p/p+ epitaxial wafers by means of low energy ion implantation |
EP2950339A1 (en) | 2014-05-26 | 2015-12-02 | Renesas Electronics Corporation | Semiconductor device |
-
1985
- 1985-08-16 JP JP18066285A patent/JPS6240719A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01258414A (en) * | 1988-04-08 | 1989-10-16 | Nec Corp | Semiconductor device |
KR100579217B1 (en) * | 1999-10-26 | 2006-05-11 | 주식회사 실트론 | Method of manufacturing on p/p+ epitaxial wafers by means of low energy ion implantation |
EP2950339A1 (en) | 2014-05-26 | 2015-12-02 | Renesas Electronics Corporation | Semiconductor device |
US10062773B2 (en) | 2014-05-26 | 2018-08-28 | Renesas Electronics Corporation | Semiconductor device having a transistor and first and second embedded layers |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP2001127326A (en) | Semiconductor substrate, method of manufacturing the same, solar cell using the same and manufacturing method thereof | |
JPS6240719A (en) | Manufacture of epitaxial wafer | |
JP3156897B2 (en) | Semiconductor substrate and method of manufacturing semiconductor substrate | |
JPS6326541B2 (en) | ||
JPS57115822A (en) | Manufacture of semiconductor device | |
JP7331520B2 (en) | Epitaxial silicon wafer manufacturing method, epitaxial silicon wafer, silicon wafer manufacturing method, and semiconductor device manufacturing method | |
JPS5935421A (en) | Manufacture of semiconductor device | |
JPH0616498B2 (en) | Method for manufacturing epitaxial wafer | |
JPH0247836A (en) | Manufacture of semiconductor device | |
JPS5838930B2 (en) | Manufacturing method of SIS structure | |
JPH0434300B2 (en) | ||
JPS6482615A (en) | Manufacture of semiconductor element | |
JPS6476756A (en) | Semiconductor integrated circuit device and manufacture thereof | |
JPH0294625A (en) | Polycrystalline silicon film, formation of same film, and photovoltaic device using same film | |
JPS6288319A (en) | Manufacture of epitaxial wafer | |
JPS5931068A (en) | Manufacture of semiconductor integrated circuit device | |
JPS62128563A (en) | Semiconductor device and manufacture of the same | |
JPS60198736A (en) | Manufacture of semiconductor device | |
JPS55133577A (en) | Method of fabricating diode | |
JPS62166531A (en) | Manufacture of epitaxial wafer | |
JPS6027175A (en) | Semiconductor element and manufacture thereof | |
JPS6316680A (en) | Gaas solar cell and manufacture thereof | |
JPS61147522A (en) | Manufacture of semiconductor substrate | |
JPH04261069A (en) | Manufacture of solar cell | |
JPH06163556A (en) | Semiconductor device |