JPS5935421A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5935421A
JPS5935421A JP14549882A JP14549882A JPS5935421A JP S5935421 A JPS5935421 A JP S5935421A JP 14549882 A JP14549882 A JP 14549882A JP 14549882 A JP14549882 A JP 14549882A JP S5935421 A JPS5935421 A JP S5935421A
Authority
JP
Japan
Prior art keywords
epitaxial
wafer
layer
wafers
defect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14549882A
Other languages
Japanese (ja)
Inventor
Etsuo Yokota
横田 悦男
Shunichi Kai
開 俊一
Toshio Yonezawa
敏夫 米沢
Shinzaburo Iwabuchi
岩「淵」 眞三郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP14549882A priority Critical patent/JPS5935421A/en
Publication of JPS5935421A publication Critical patent/JPS5935421A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02381Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Thyristors (AREA)

Abstract

PURPOSE:To obtain an epitaxial layer with no defect by a method wherein the surface of an impurity diffused layer is lapped into the mirror face, a predetermined thickness is removed, and then epitaxial growth is performed. CONSTITUTION:A P diffused layer is selectively formed on an N type Si substrate using a normal technique. The exposed surface of the diffused layer is mechanically and chemically lapped into the mirror face using silicic acid powder, whereby the surface is removed in depth of ca. 5mum. An Si epitaxial layer is formed thereon, so that the epitaxial layer with no defect can be obtained. By so doing, it becomes possible to manufacture SCRs for large power from the epitaxial wafers and to improve the yield even in other bipolar elements.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は半導体装置の製造方法に関するものであり、
特に大電力用サイリスタ等に好適な製造方法に関するも
のである。
[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device,
In particular, the present invention relates to a manufacturing method suitable for high-power thyristors and the like.

〔発明の技術的背景〕[Technical background of the invention]

バイポーラ素子用の半導体ウェハとしてハ、一般にエピ
タキシャルウェハが用いられるが、現在のエピタキシャ
ル技術ではエピタキシャル層を完全に無欠陥に形成する
ことができyzVため、エピタキシャル工程後に全く無
欠陥のエピタキシャルウェハが得られる収率は極めて低
い。従って、一枚の半導体ウニ・・を多数の半導体チッ
プとして分割するバイポーラIC等の製造においては、
欠陥のあるチップのみ切除すれば、エピタキシャルウェ
ハを使用しても歩留りが極端に低くなることはないが、
一枚のウエノ・がそのまま−個の素子となる大電力用サ
イリスクの製造においては、エビタキシャルウエノ・を
用いると歩留りが極端に悪くなってしまう。このため、
従来は、一枚の半導体ウェハが一個の素子となる大電力
用サイリスタはエビタキシャルウエノ・を用いて製造す
ることができなかった。
Epitaxial wafers are generally used as semiconductor wafers for bipolar devices, but with the current epitaxial technology it is possible to form an epitaxial layer completely defect-free, so an epitaxial wafer with no defects can be obtained after the epitaxial process. Yield is extremely low. Therefore, in manufacturing bipolar ICs, etc., in which a single semiconductor chip is divided into multiple semiconductor chips,
If only defective chips are removed, the yield will not be extremely low even if epitaxial wafers are used, but
In the production of high-power silices in which a single sheet of wafer is used as individual elements, the yield will be extremely poor if an epitaxial wafer is used. For this reason,
Conventionally, high-power thyristors, in which a single semiconductor wafer constitutes one element, could not be manufactured using epitaxial wafers.

〔背景技術の問題点〕[Problems with background technology]

以下には、バイポーラICや小電力用トランジスタ等の
製造に用いられているエピタキシャルウェハの製造方法
の概要とそれに存する問題点とについて説明する。
Below, an overview of the method for manufacturing epitaxial wafers used for manufacturing bipolar ICs, low-power transistors, etc., and the problems that exist therein will be explained.

従来、エビタキシャルウエノ・は次のような方法で製造
されている。まず、C2法若しくはFZ法等で所定の導
電型の半導体ウェハを製作し、この半導体ウェハの所定
部にアクセプタ不純物若しくはドナー不純物を熱拡散法
によってドープして不純物拡散層を形成する。次に、こ
の不純物拡散層の表面を硫酸、過酸化水素、塩酸等によ
って洗浄した後、純水を滴下しつつ清浄な布で表面スク
ラビングを行ってウェハ表面を清浄にする。そしてこの
清浄化処理後、不純物拡散層の表面にエピタキシャル成
長によって単結晶のエピタキシャル層を成長させている
Conventionally, evitaxial ueno has been manufactured by the following method. First, a semiconductor wafer of a predetermined conductivity type is manufactured by the C2 method or the FZ method, and a predetermined portion of the semiconductor wafer is doped with an acceptor impurity or a donor impurity by a thermal diffusion method to form an impurity diffusion layer. Next, after cleaning the surface of this impurity diffusion layer with sulfuric acid, hydrogen peroxide, hydrochloric acid, etc., the surface of the wafer is scrubbed with a clean cloth while dropping pure water to clean the wafer surface. After this cleaning treatment, a single crystal epitaxial layer is grown on the surface of the impurity diffusion layer by epitaxial growth.

しかしながら、前記の如き従来方法においては、どんな
に表面スクラビングを丁寧に行っても、清浄化処理後の
ウェハ表面に数個程度の微量の残渣が残り、この残渣が
次のエビメキシャル工程でマウンド等の欠陥をエピタキ
シャル層に発生させる原因となるため、従来方法では全
く無欠陥のエピタキシャルウェハを製造することはほと
んど不可能であった。
However, in the conventional method as described above, no matter how carefully the surface scrubbing is performed, a small amount of residue remains on the wafer surface after the cleaning process, and this residue causes defects such as mounds in the next epimexical process. This causes defects to occur in the epitaxial layer, so it has been almost impossible to produce epitaxial wafers with no defects using conventional methods.

従って、従来の方法で製造されたエピタキシャルウェハ
には必ず欠陥が存在する以上、一枚のウェハを一個の素
子として使用する大電力用サイリスタにはエピタキシャ
ルウェハを使用することができず、かかる大電力用サイ
リスクは専ら全拡散法や拡散合金法によって製造されて
いた。
Therefore, since epitaxial wafers manufactured by conventional methods always have defects, epitaxial wafers cannot be used in high-power thyristors that use one wafer as one element; Cyrisk was manufactured exclusively by the total diffusion method or the diffusion alloy method.

〔発明の目的〕[Purpose of the invention]

この発明の目的は、前記従来方法における問題点を解決
して、無欠陥のエビタキシャルウエノ・を得、これを用
いて改良された半導体装置製造方法を提供することであ
り、この発明の他の目的は、大電力用サイリスタをエビ
タキシャルウエノ・によって製造することのできる半導
体装置製造方法を提供することである。
An object of the present invention is to solve the problems in the conventional method, obtain a defect-free epitaxial wafer, and provide an improved semiconductor device manufacturing method using the same. An object of the present invention is to provide a method for manufacturing a semiconductor device that can manufacture a high-power thyristor using an epitaxial process.

〔発明の概要〕[Summary of the invention]

本発明者らは、無欠陥のエピタキシャル層を有するエビ
タキシャルウエノ・を得るために種々の試みを行った結
果、不純物拡散pの形成後、該拡散層表面を機械的力)
つ化学的な鏡面研磨によって5μm厚程魔除去した後に
エピタキシャル成長をさせると、無欠陥のエピタキシャ
ル層が得られること全見出し、これにより従来技術の問
題点を完全に解決できることを確認した。
The present inventors made various attempts to obtain an epitaxial layer having a defect-free epitaxial layer, and as a result, after the formation of impurity diffusion p, the surface of the diffusion layer was subjected to mechanical force).
The inventors have found that a defect-free epitaxial layer can be obtained by epitaxially growing the layer after 5 μm thickness is removed by chemical mirror polishing, thereby confirming that the problems of the prior art can be completely solved.

〔発明の実施例〕[Embodiments of the invention]

ミラー指数(111)、抵抗率150〜200ΩCMの
N形シリコンウェハ全、純水、塩酸、過酸化水素の混合
液で洗浄し7し後、1100℃の乾燥酸素中で30分間
酸化して表面に厚さ950 AのSiO2膜を形成した
A whole N-type silicon wafer with a Miller index (111) and a resistivity of 150 to 200 ΩCM was washed with a mixture of pure water, hydrochloric acid, and hydrogen peroxide, and then oxidized for 30 minutes in dry oxygen at 1100°C to form a surface. A SiO2 film with a thickness of 950 A was formed.

次にこの酸化膜を通して加速電圧140keVでドーズ
量7 X 1014/rdのりんをウェハ内にイオン注
入した後、再び前記混合液で洗浄し、更に洗浄後のウェ
ハ′ff:1100℃で約7時間スチーム酸化法により
酸化し約1.5μm厚さの酸化膜を形成する。この酸化
膜形成後、ウニ・・は前記混合液で1.洗 浄、・し、
洗浄後のウニ・・を窒素と酸素との混合ガス中において
1260℃で約50時間かけてウェハ内にりんを拡散さ
せた。このりんの拡散深さは55μm±4μmである。
Next, phosphorus was ion-implanted into the wafer at a dose of 7 x 1014/rd through this oxide film at an accelerating voltage of 140 keV, and then the wafer was cleaned again with the mixed solution, and the wafer after cleaning was heated at 1100°C for about 7 hours. It is oxidized by a steam oxidation method to form an oxide film with a thickness of about 1.5 μm. After this oxide film is formed, the sea urchin... is treated with the above mixed solution in 1. Washing...
After cleaning, the sea urchin was placed in a mixed gas of nitrogen and oxygen at 1260° C. for about 50 hours to diffuse phosphorus into the wafer. The diffusion depth of this phosphorus is 55 μm±4 μm.

りん拡散後、ウェハ表面の酸化膜は弗酸でエツチングし
てりん拡散層を露出させ、更に前記洗浄液で洗浄した。
After phosphorus diffusion, the oxide film on the wafer surface was etched with hydrofluoric acid to expose the phosphorus diffusion layer, and the wafer was further cleaned with the cleaning solution.

次に前記のようにしてりん拡散層を露出させたウェハの
表面を硅酸パウダーを用いて機械的かつ化学的に鏡面研
磨してりん拡散層の表面を5μm取り除き、鏡面研磨後
のウェハ表面にエピタキシャル成長により厚さ40μm
1比抵抗0.1Ω(7)のN形単結晶のエピタキシャル
層を形成した。
Next, the surface of the wafer with the phosphorus diffusion layer exposed as described above is mechanically and chemically mirror polished using silicate powder to remove 5 μm of the surface of the phosphorus diffusion layer, and the surface of the wafer after mirror polishing is 40μm thick by epitaxial growth
An N-type single crystal epitaxial layer with a specific resistance of 0.1Ω (7) was formed.

以上の如き本発明における方法により100枚のエピタ
キシャルウェハを製作するとともに、前記従来方法(す
なわち洗浄後に清浄布により表面スクラビングを行う方
法)によって同一シリコンウェハを用いて同数のエピタ
キシャルウェハヲ製作し、この二種類のエピタキシャル
ウェハについてそれぞれのマウンド発生率を調査した。
100 epitaxial wafers were manufactured by the method of the present invention as described above, and the same number of epitaxial wafers were manufactured using the same silicon wafer by the conventional method (i.e., the method of scrubbing the surface with a clean cloth after cleaning). The incidence of mounds was investigated for two types of epitaxial wafers.

添付図面は本発明における方法により製造されたエピタ
キシャルウェハのマウンド発生率(ウェハ1枚当りのマ
ウンド発生数)と、従来方法により製造されたエピタキ
シャルウェハのマウンド発生率と比較表示したものであ
り、同図において左側の棒グラフは従来方法によるもの
であり、右側の棒グラフは本発明における方法によるも
のであ同図力)ら明らかなように、本発明における方法
によって製造されたエピタキシャルウェハは、マウンド
のないものが100枚のうち80枚にも達し、またマウ
ンド発生数が1個のウェハは15枚であるのに対して、
従来方法のウェハではマウンドのないものはわずかに一
枚のみであり、マウンド発生数5であるものが全体の4
0%にも達している。
The attached drawings compare the mound occurrence rate (the number of mounds generated per wafer) of epitaxial wafers manufactured by the method of the present invention with those of epitaxial wafers manufactured by the conventional method. In the figure, the bar graph on the left side is the result of the conventional method, and the bar graph on the right side is the result of the method according to the present invention. 80 out of 100 wafers have one mound, and only 15 wafers have one mound.
Only one wafer using the conventional method has no mounds, and 4 of the wafers have 5 mounds.
It has even reached 0%.

上記エピタキシャルウェハに、常法によりベース拡散、
エミッメ拡散、次いで電極形成を行いサイリスク素子を
製作したところ、従来方法のエピタキシャルウェハでは
1つも良品サイリスク素子が得られなかったが、本発明
におけるエピタキシャルウェハではサイリスタ製造プロ
セス良品率は約50%であり、本提案方法が極めて有効
であることがわかった。
The above epitaxial wafer is subjected to base diffusion using a conventional method.
When a thyristor element was fabricated by emitter diffusion and then electrode formation, no good thyristor element was obtained using the epitaxial wafer using the conventional method, but with the epitaxial wafer of the present invention, the thyristor manufacturing process yielded a good product rate of about 50%. The proposed method was found to be extremely effective.

〔発明の効果〕〔Effect of the invention〕

以上の結果から、本発明方法によれば、無欠陥のエピタ
キシャルウェハを製造することができ、従って大電力用
サイリスクヲエビタキシャルウエハによって製作するこ
とが可能となると同時に、その他のバイポーラ素子にお
いても歩留向上が実現されることも明らかである。
From the above results, according to the method of the present invention, it is possible to manufacture defect-free epitaxial wafers, and therefore, it is possible to manufacture high-power silica-free epitaxial wafers, and at the same time, it is possible to manufacture epitaxial wafers with no defects. It is also clear that an improvement in yield is achieved.

【図面の簡単な説明】[Brief explanation of the drawing]

添付図面は本発明における方法により製造されたエピタ
キシャルウェハ1の一枚当りマウンド発生数と、従来方
法により製造されたエピタキシャルウェハの一枚当りマ
ウンド発生数とを比較表示したグラフである。 =95= 7?7−ド宥ビL牧−シ
The accompanying drawing is a graph comparing the number of mounds generated per epitaxial wafer 1 manufactured by the method of the present invention and the number of mounds generated per epitaxial wafer 1 manufactured by the conventional method. =95= 7?7-Do appeasement L Maki-shi

Claims (1)

【特許請求の範囲】[Claims] 1 半導体基板の表面に不純物拡散層を形成した後、該
不純物拡散層の表面を機械的かつ化学的に鏡面研磨して
所要厚さだけを取り除き、鏡面研磨後の該不純物拡散層
の上にエピタキシャル法によって所定厚さのエピタキシ
ャル層を形成する工程を含むことを特徴とする半導体装
置の製造方法。
1. After forming an impurity diffusion layer on the surface of a semiconductor substrate, the surface of the impurity diffusion layer is mechanically and chemically mirror-polished to remove only the required thickness, and an epitaxial layer is formed on the mirror-polished impurity diffusion layer. 1. A method of manufacturing a semiconductor device, comprising the step of forming an epitaxial layer of a predetermined thickness by a method.
JP14549882A 1982-08-24 1982-08-24 Manufacture of semiconductor device Pending JPS5935421A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14549882A JPS5935421A (en) 1982-08-24 1982-08-24 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14549882A JPS5935421A (en) 1982-08-24 1982-08-24 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5935421A true JPS5935421A (en) 1984-02-27

Family

ID=15386644

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14549882A Pending JPS5935421A (en) 1982-08-24 1982-08-24 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5935421A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61147522A (en) * 1984-12-20 1986-07-05 Sanyo Electric Co Ltd Manufacture of semiconductor substrate
JPS61282505A (en) * 1985-06-07 1986-12-12 豊和工業株式会社 Cleaning vehicle for road surface
EP0617456A2 (en) * 1993-03-08 1994-09-28 Gi Corporation Low cost method of fabricating epitaxial semiconductor devices
JP2010141099A (en) * 2008-12-11 2010-06-24 Shin Etsu Handotai Co Ltd Method of manufacturing silicon epitaxial wafer

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61147522A (en) * 1984-12-20 1986-07-05 Sanyo Electric Co Ltd Manufacture of semiconductor substrate
JPS61282505A (en) * 1985-06-07 1986-12-12 豊和工業株式会社 Cleaning vehicle for road surface
EP0617456A2 (en) * 1993-03-08 1994-09-28 Gi Corporation Low cost method of fabricating epitaxial semiconductor devices
JP2010141099A (en) * 2008-12-11 2010-06-24 Shin Etsu Handotai Co Ltd Method of manufacturing silicon epitaxial wafer

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