JPH01186669A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To realize a structure which is hardly chipped by noises by forming a thick oxide film onto a one-conductivity semiconductor substrate, by forming an opposite conductivity region on a substrate surface of a selectively provided opening, and by growing an opposite conductivity single crystal layer thereon. CONSTITUTION:A P<+>-type silicon layer 12 of high concentration is provided under a P-type well 13, and an N<+>-type silicon layer 15 of high concentration is provided under an N-type well 16 to decrease resistance values under the wells 13, 16 and not to generate a voltage to trigger a parasitic thyristor. Moreover, since the P-type well 13 and the N-type well 16 are isolated by insulating oxide 8, a parasitic thyristor is hardly made by a parasitic NPN transistor and a parasitic PNP transistor. In this way, latchup is hardly caused by noises.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device including a step of forming wells and element isolation regions.

[Conventional technology]

Up until now, semiconductor devices have been becoming more densely integrated.
Various problems have arisen as the density of integration has increased.

FIGS. 3(a) to 3(f) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an example of a conventional method for manufacturing a semiconductor device.

First, as shown in FIG. 3(a), an N-type silicon substrate 1
is thermally oxidized at 950° C. to form a thermal oxide film 2 with a thickness of 50 nm on the surface. Next, a resist layer 3 is formed on the thermal oxide film 2. Next, the resist layer in the area where the first well is to be formed is removed to provide an opening 4a. Using the resist layer 3 as a mask, boron ions are implanted at a dose of 2.times.10"cm".sup.-2.

Next, as shown in FIG. 3(b), the resist layer 3 is removed, and the temperature is 1200° C. in a nitrogen field containing several percent of oxygen.
, heat treatment is performed for 8 hours to form the first well and the seventh P-type well 5.

Next, the thermal oxide film 2 is removed and thermal oxidation is performed again at 950° C. to form a thermal oxide film 6b with a thickness of 50 nm on the same surface.

Next, as shown in FIG. 3(c), a resist layer is formed on the thermal oxide film 6b, and then the resist layer in the area where the second well is to be formed is selectively removed. Open the window. Next, a dose of 5X is applied to the N-type silicon substrate 1 through the window.
Phosphorus ions are implanted at 10"cm-2. Next, after removing the resist layer, heat treatment is performed at 1150° C. to form an N-type well 7 as a second well. Next, the thermal oxide film 6b is removed. Then, thermal oxidation was performed again at 950°C to obtain a thickness of 50°C.
A thermally oxidized M6c of nm thickness is formed.

Next, as shown in FIG. 3(d), a nitride film 9 having a thickness of 150 nm is formed on the thermal oxide film 6C by low pressure CVD, and a resist layer 10 is further formed on the nitride film 9.

Next, the resist layer 10 and the nitride film 9 in the region where the field oxide film is to be formed are selectively removed to form an opening. Next, using the resist layer 10 as a mask, boron ions are implanted into the opening at a dose of 5×10 13 cm −2 to form a channel stopper 11 .

Next, as shown in FIG. 3(e), the resist layer 10 is removed and thermally oxidized at 1000° C. in a mixed atmosphere of hydrogen and oxygen to form a field oxide film 17 with a thickness of 600 nm. , the thermal oxide film 6C is removed.

After this, as shown in Figure 3(f), the normal CMO3
An N-type channel transistor 20 is formed in the P-type well 5 and a P-type channel transistor 19 is formed in the N-type well 7 using the manufacturing method described above.

[Problem that the invention seeks to solve]

CMOS type semiconductor devices manufactured by the above-described method have a problem in that latch-up occurs due to power supply noise and the like.

FIG. 4 is a schematic cross-sectional view for explaining latch-up in a CMOS type semiconductor device.

N of the N-type channel transistor 20 in the P-type well 5
++ A parasitic NPN transistor 22 is formed by the source region 26, the P-type well 5, and the N-type silicon substrate 1, and the NPN
P of the P-type channel transistor 19 in the type well 7
A parasitic PNP transistor 21 is formed by the + type source region 23, the N type well 7, the N type silicon substrate 1, and the P type well 5.

Furthermore, the base of the parasitic PNP transistor 21 is a parasitic NP transistor.
N) The collector of the transistor 21 is connected to the base of the N-type silicon substrate 1 via the node G, and is surrounded by a dotted line. This means that the parasitic thyristor 28 is formed in the area where the thyristor is removed.

Here, when noise 27 enters from the output terminal OUT through the N+ type drain region 25 of the N type channel transistor 20, the parasitic NPN) is generated by the resistor R2 in the P type well 5.
A bias voltage is generated between the emitter and base of the transistor 22, and a base current ins flows from node G, causing parasitic NP
N) Collector current i amplified by current i EN flowing between the base and emitter when transistor 22 operates. N
flows.

This current iCN becomes the base current iBp of the parasitic PNP transistor 21.

This base current tap is a parasitic PNP transistor 21
The collector current i cp is amplified by
cp flows through node G to the base of NPN transistor 22.

Due to this thyristor effect, an emitter current flows from the power supply terminal VDD to the emitter of the parasitic PNP transistor 21, from the emitter to the collector, from the collector via node G to the base of the parasitic NPN transistor 22, and from the base to the emitter to the power supply terminal VSS. This causes a so-called latch-up phenomenon due to noise.

As described above, the semiconductor device manufactured by the above-described semiconductor device manufacturing method has the problem of latch-up due to minute noise.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that has a structure that is unlikely to latch up due to noise.

[Means for solving problems]

The method for manufacturing a semiconductor device of the present invention includes the steps of: - forming a thick oxide film on one main surface of a conductive type semiconductor substrate; selectively forming an opening in the oxide film; forming an opposite conductivity type region; growing a reverse conductivity type single crystal layer on the opposite conductivity type region by low pressure epitaxial growth; and forming a thin oxide film on the surface of the opposite conductivity type single crystal layer. It consists of a process.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1A to 1F are cross-sectional views of a semiconductor chip shown in order of steps for explaining a first embodiment of the present invention.

First, as shown in FIG. 1(a), an N-type silicon substrate 1
is thermally oxidized at 950° C. to form a thermal oxide film 2 with a thickness of 50 nm on the surface, and a dose amount I is applied to the surface of the N-type silicon substrate 1.
Channel stopper 11 is formed by implanting boron ions at x 1013 cm-''.

Next, as shown in FIG. 1(b), the thermal oxide film 2 is removed, and a thermal oxide film 6a with a thickness of 50 nm is formed on the same surface again by the thermal oxidation method, and further on the thermal oxide film 6a. A CVD oxide film 8 having a thickness of 3 μm is grown by atmospheric pressure CVD. Next, heat treatment is performed at 1000° C. for about 2 hours in a mixture of hydrogen and oxygen to make the CVD oxide film 8 dense.

Next, as shown in FIG. 1(C), the area where the first well is to be formed is subjected to CVD using the photolithographic soy method and the reactive ion etching method using a mixed gas of carbon tetrafluoride and hydrogen. Oxide film 8 and thermal oxide film 6a are selectively removed to form opening 4b. Next, boron ions were implanted into the opening 4b at a dose of 5 x 1015 cm-'', and heat treatment was performed at 950°C for 10 minutes in a nitrogen atmosphere.
Form mold 9937 layer 12.

Next, as shown in FIG. 1(d), P+ type 9937 layer 1
A P-type epitaxial layer with an impurity concentration of about 5×10 16 cm −′ is grown on the substrate 2 by a low-pressure epitaxial growth method to form a P-type well 13 as a first well. Furthermore, a film with a thickness of 5 mm is formed on the surface of the P-type well 13 by thermal oxidation.
A thermal oxide film 14 with a thickness of 0 nm is formed.

Next, as shown in FIG. 1(e), the CVD oxide film 8. in the region where the second well is to be formed is formed by photolithography and reactive ion etching. Thermal oxide film 6
A is selectively removed to provide an opening 4C.

Next, a dose amount of 5×1015c m− is applied to the opening 4C.
In step 2, phosphorus ions were implanted and heated at 950°C in a nitrogen atmosphere.
A heat treatment is performed for 10 minutes to form an N+ type silicon layer 15.

Next, as shown in FIG. 1(f), an N-type epitaxial layer having an impurity concentration of about 5.times.10@16 cm'' is grown by a low-pressure epitaxial growth method to form an N-type well 16 as a second well. Next, the thermal oxide film 14 is removed using hydrofluoric acid.

Next, as described in the conventional example, an N-type channel transistor is formed in the P-type well, and a P-type channel transistor is formed in the N-type well.

In this example, P+ type 993 located below each well.
Since the seventh layer 12 and the N+ type silicon layer 15 are highly concentrated, it is possible to suppress the generation of a bias voltage that triggers the parasitic thyristor due to noise, and to prevent latch-up of the parasitic thyristor. Furthermore, since the P+ type 9937 layer 12 and the N+ type silicon layer 15 are separated from each other,
A parasitic thyristor formed by a parasitic PNP transistor and a parasitic NPN transistor is less likely to be formed.

Conventionally, since the well was formed by ion implantation, the concentration in the lower part of the well was lower than that in the upper part, and the resistance in the lower part of the well could not be made sufficiently low.

In this example, the epitaxial growth method was used, so the impurity concentration can be uniform, and the impurity concentration can be controlled during well formation to make the concentration higher in the lower part, which further reduces the generation of bias voltage. The latch-up phenomenon can be prevented.

FIGS. 2(a) to 2(d) are cross-sectional views of a semiconductor chip shown in order of steps for explaining a second embodiment of the present invention.

Up to the steps explained using FIGS. 1(a) to (b),
This is done in the same manner as in the example.

Next, as shown in FIG. 2(a), the thermal oxide film 6a and the CVD oxide film 8 in the area where the first well is to be formed are selectively removed by photolithography and reactive ion etching, and an opening is formed. A portion 4b is formed. Next, the opening 4b
The impurity concentration is reduced to I at the bottom of the
X 1019cn+-' P+ type 9932 layer 29 is 1μ
Grow to a thickness of m.

Next, as shown in FIG. 2(b), a P type epitaxial layer with an impurity concentration of about 5 x 1016 cm-3 is grown on the P+ type 9932 layer 29 by a low pressure epitaxial growth method, and a P type well is formed as the first well. A mold well 13 is formed.

Next, as shown in FIG. 2(c), a thermal oxide film 14 having a thickness of 50 nm is formed on the P-type well 13 by a thermal oxidation method. Next, by photolithography and reactive ion etching, the CVD oxide film 8 and thermal oxide film 6a in the region where the second well is to be formed are selectively removed to form an opening 4C.

Next, a layer of N+ type opening 932 with an impurity concentration of about I x 1019 cm-3 is grown to a thickness of 301 μm at the bottom of the opening 4C by low pressure epitaxial growth.

Next, as shown in FIG. 2(d), an N-type epitaxial layer with an impurity concentration of about 5X1016 cm-3 is grown on the N+ type opening 932 layer 30 by epitaxial growth, and an N-type epitaxial layer is grown as a second well. A mold well 16 is formed. Next, the thermally oxidized Jli14 is removed with hydrofluoric acid.

After that, the process is carried out in the same manner as in the first embodiment.

This second embodiment has the same effect as the first embodiment, and has a P+ type 9937 layer 12 and 9 in the first embodiment.
and N+ type 9937 layer 15 are formed on the surface of N type silicon substrate 1, so when heat treated, lateral diffusion occurs and the P+ type 9937 layer 12 and N+ type 9937 layer 15 are formed on the surface of N+ type silicon substrate 1.
In contrast, in the second embodiment, a P+ type thyristor is formed on the surface of an N type silicon substrate 1 by epitaxial growth.
Since the two layers 29 and the N+ type opening 932 layer 30 are formed, insulation isolation is more advantageous than in the first embodiment, so parasitic thyristors are less likely to form, and latch-up phenomena are suppressed. I can do it.

〔Effect of the invention〕

As explained above, the present invention provides a high concentration P+ type silicon layer under the P type well and a high concentration N++ silicon layer under the N type well, thereby reducing the resistance value at the bottom of each well. The parasitic NPN
Since a parasitic thyristor formed by a transistor and a parasitic PNP (parasitic PNP) transistor is less likely to be formed, it is possible to manufacture a semiconductor device in which latch-up due to noise is less likely to occur.

[Brief explanation of the drawing]

1(a) to (f) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining the first embodiment of the present invention, and FIGS. 2(a) to (d) are cross-sectional views of a semiconductor chip of the second embodiment of the present invention. FIG. 3(a) is a cross-sectional view of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention.
-(f) are cross-sectional views of a semiconductor chip for explaining an example of a conventional method for manufacturing a semiconductor device, and FIG. 4 is a schematic cross-sectional view for explaining latch-up in a CMO3 type semiconductor device. 1...N-type silicon substrate, 2...thermal oxide film, 3...
・Resist layer, 4a, 4b, '4c...opening, 5・
...P-type well, 6a, 6b, 6C...thermal oxide film, 7
...N type well, 8...CVD oxide film, 9...nitride film, 10...resist layer, 11...channel stopper, 12...P+ type silicon layer, 13...P Type well, 14... Thermal oxide film, 15... N++ silicon layer, 16... N type well, 17... Field oxide film, 18... Electrode, 19... P type channel transistor, 20... N-type channel transistor, 21.
... Parasitic PNP) transistor, 22... Parasitic NPN transistor, 23... P1 type source region, 24...
P+ type drain region, 25... N+ type drain region 26... N++ source region, 27... Noise, 28
...parasitic silicon risk, 29...P+ type silicon layer,
30...N+ type silicon layer.

Claims (1)

[Claims] forming a thick oxide film on one main surface of a semiconductor substrate of one conductivity type; selectively forming an opening in the oxide film and forming an opposite conductivity type region on the surface of the semiconductor substrate in the opening; A semiconductor characterized by comprising the steps of growing a reverse conductivity type single crystal layer on the opposite conductivity type region by a low pressure epitaxial growth method, and forming a thin oxide film on the surface of the opposite conductivity type single crystal layer. Method of manufacturing the device.