JPS60236243A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60236243A JPS60236243A JP59092443A JP9244384A JPS60236243A JP S60236243 A JPS60236243 A JP S60236243A JP 59092443 A JP59092443 A JP 59092443A JP 9244384 A JP9244384 A JP 9244384A JP S60236243 A JPS60236243 A JP S60236243A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- type
- polished
- mirror
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 238000000034 method Methods 0.000 claims description 14
- 238000009792 diffusion process Methods 0.000 claims description 7
- 238000010438 heat treatment Methods 0.000 abstract description 4
- 238000005498 polishing Methods 0.000 abstract description 3
- 230000003746 surface roughness Effects 0.000 abstract description 3
- 238000005530 etching Methods 0.000 abstract description 2
- 230000001105 regulatory effect Effects 0.000 abstract 1
- 239000012535 impurity Substances 0.000 description 6
- 230000007547 defect Effects 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
- H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Bipolar Transistors (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
（発明の技術分野〕
本発明は、内部に埋込み層を有する半導体基板の製造方
法に関する。DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a method for manufacturing a semiconductor substrate having a buried layer therein.
（発明の技術的背景とその問題点）
バイポーラＩＣのように、素子基板の内部に不純物や濃
度の異なる埋込み層を必要とするものは多い。第１図は
その様な一例として、一般的なバイポーラＩＣを示して
いる。この製造工程は次の通りである。先ず、ｐ形Ｓｉ
基板１１に選択拡散によりコレクタ埋込み層となるｎ“
層１２を形成する。次いてこの基板上にエピタキシャル
成長法によってｎ一層１３を形成する。こうして（ｑら
れたエピタキシャル基板にｐベース層１４．ｎ＋ソース
層１５を順次拡散形成してトランジスタを得る。１６は
素子分離用のｐ＋拡散層であり、１７はコレクタ電極取
出しのためのｎ＋拡散層である。(Technical Background of the Invention and Problems thereof) Many ICs, such as bipolar ICs, require buried layers with different impurities or concentrations inside the element substrate. FIG. 1 shows a typical bipolar IC as one such example. This manufacturing process is as follows. First, p-type Si
n" which becomes a collector buried layer by selective diffusion on the substrate 11
Form layer 12. Next, an n-layer 13 is formed on this substrate by epitaxial growth. In this way, a p base layer 14 and an n+ source layer 15 are successively diffused into the (q) epitaxial substrate to obtain a transistor. 16 is a p+ diffusion layer for element isolation, and 17 is an n+ diffusion layer for taking out the collector electrode. It is.
従来のこの様な方法では、埋込み層の深さはエピタキシ
ャル成長層の厚みで決まる。しかしながら、エピタキシ
ャル法では成長速度に限界があるため、厚い層を得るた
めには極めて長時間を要（る。しかも高度の技術を必要
とし、制御が難しいために欠陥等を生じ易い。また長時
間の１ビタキシヤル成長工程で埋込み層の不純物が再拡
散するため、埋込み層上のエピタキシャル層の厚み制御
も難しい。In such conventional methods, the depth of the buried layer is determined by the thickness of the epitaxially grown layer. However, the epitaxial method has a limited growth rate, so it takes an extremely long time to obtain a thick layer.Moreover, it requires advanced technology and is difficult to control, which tends to cause defects. Since impurities in the buried layer are re-diffused during the first bitaxial growth step, it is also difficult to control the thickness of the epitaxial layer on the buried layer.
本発明は上記の点に鑑みてなされたもので、簡単な工程
で制御性よく埋込み層を形成するように（、た＋−導体
塁恢の製造方法を提供することを目的とりる。The present invention has been made in view of the above points, and it is an object of the present invention to provide a method for manufacturing a conductor base so as to form a buried layer with good controllability in a simple process.
本発明は、２枚の半導体基板を直接接合させて一枚の半
導体基板を得るという方法を利用する。The present invention utilizes a method of directly bonding two semiconductor substrates to obtain one semiconductor substrate.
このような半導体同士の接合によって不純物濃度の異な
る層を内部に形成する方法自体は、合金形半導体接合法
として古くから知られた技術である。The method of forming internal layers with different impurity concentrations by bonding semiconductors together is a technique that has been known for a long time as an alloy semiconductor bonding method.
しかしこの方法は坦在一般に利用されていない。However, this method is not generally used.
その理由は、この方法では、１３００℃という、半導体
の融点に近い＾瀧まで加熱し加圧する必要があり、その
結果、半導体結晶に多くの欠陥や変成層が形成されるた
めである。The reason is that this method requires heating and pressurizing to 1300° C., which is close to the melting point of the semiconductor, and as a result, many defects and metamorphosed layers are formed in the semiconductor crystal.
これに対し、本発明者らは、半導体基板の表面を充分に
鏡面研磨して、その研磨面どうしを充分ｉ′ｌＩｉ浄な
雰囲気下で密着させることにより、強固な接合体が得ら
れることを見出した。この接合体は２００’Ｃ以上の温
度で熱処理すれば、接合がより強固なものとなる。この
接合のメカニズムは未だ不明な点が多いが、鏡面研磨面
に形成される自然酸化膜が重要な役割を果たしているら
しいことが推測される。In contrast, the present inventors have discovered that a strong bonded body can be obtained by sufficiently mirror-polishing the surface of a semiconductor substrate and bringing the polished surfaces into close contact with each other in a sufficiently clean atmosphere. I found it. If this bonded body is heat treated at a temperature of 200'C or higher, the bond will become stronger. Although many aspects of this bonding mechanism are still unclear, it is speculated that the natural oxide film formed on the mirror-polished surface seems to play an important role.
本発明は、この新しい技術を利用して、先ず鏡面研磨さ
れた第１の半導体基板の表面に選択的に拡散層を形成し
、これを鏡面研磨された第２の半導体基板と研磨面同士
を対向させてｍ浄な雰囲気下で接合させ、１３００℃を
超えない範囲で熱処理することにより、埋込み層を有す
る半導体基板を得る。鏡面研磨面の表面粗さは１１００
Ａ、下であることが望ましい。熱処理温度は２００℃程
度以上であればよく、望ましくは１０００℃程度である
が、１３００″Ｃ程度まで高くすると結晶欠陥などの発
生があるため、ここまで高くすることは出来ない。The present invention utilizes this new technology to first selectively form a diffusion layer on the surface of a mirror-polished first semiconductor substrate, and then to connect the polished surfaces to a mirror-polished second semiconductor substrate. A semiconductor substrate having a buried layer is obtained by facing each other and bonding in a clean atmosphere, and heat-treating at a temperature not exceeding 1300°C. Surface roughness of mirror polished surface is 1100
A: It is desirable that it be lower. The heat treatment temperature may be about 200° C. or higher, preferably about 1000° C., but if it is raised to about 1300″C, crystal defects will occur, so it cannot be made this high.
本発明によれば、長時間のエピタキシトル成長等を要せ
ず、簡単に埋込み層を持つ半導体基板を得ることができ
る。しかも熱処理は高温を要しないから、埋込み層が高
不純物濃度層である場合にも不純物の再拡散は最少限に
押えられ、埋込み層の深さや濃度を制御性よく設定する
ことができる。According to the present invention, a semiconductor substrate having a buried layer can be easily obtained without requiring long-term epitaxial growth. Furthermore, since the heat treatment does not require high temperatures, re-diffusion of impurities can be suppressed to a minimum even when the buried layer is a layer with high impurity concentration, and the depth and concentration of the buried layer can be set with good controllability.
従ってＩＣその他の素子製造の工程短縮化や素子性能ｐ
向上を図ることができる。Therefore, it is possible to shorten the process of manufacturing ICs and other elements, and increase the performance of the elements.
You can improve your performance.
以下本発明をバイポーラＩ Ｃ’に適用した実施例につ
いて第２図（ａ）〜′（ｅ）を用いて説明する。An embodiment in which the present invention is applied to a bipolar IC' will be described below with reference to FIGS. 2(a) to 2'(e).
第２図（ａ）は、表面粗さ５００Å以下に充分平滑に鏡
面研磨されたｐ型３ｉ基板（第１の半導体基板）２１の
表面にｎ＋型層２２を選択的に拡散形成した状態を示し
ている。ｎ＋型層２２はコレクタ埋込み層どなるもので
ある。第２図（ｂ）は同様に鏡面研磨されたｎ−型Ｓｉ
ｌ板（第２の半導体基板）２３であり、その表面にコレ
クタ取出し層となるｎ＋型層２４及び素子分離層となる
ｐ′″型層２５が拡散形成された状態を示している。FIG. 2(a) shows a state in which an n+ type layer 22 is selectively diffused and formed on the surface of a p-type 3i substrate (first semiconductor substrate) 21 which has been mirror-polished to a sufficiently smooth surface with a surface roughness of 500 Å or less. ing. The n+ type layer 22 is a collector buried layer. Figure 2(b) shows n-type Si that has been mirror-polished in the same way.
The figure shows a state in which an n+ type layer 24 serving as a collector extraction layer and a p'' type layer 25 serving as an element isolation layer are diffused and formed on the surface of an L plate (second semiconductor substrate) 23.
これらの基板を充分に洗浄し、乾燥させた後、ゴミなど
の異物が介在しない清浄な雰囲気中で第２図（Ｃ）に示
すように研磨面どうしを密着させて接合する。この接合
体は熱処理をしなくてもかなりの接合強度が得られるが
、２００℃以上、好ましくは１０００℃程度で熱処理し
て接合強度を充分強固なものとする。こうしてｎ１型１
１２２が埋め込まれ、素子分離層とコレクタ取出し層が
形成されただＩＣ基板が１りられる。この基板はそのま
ま用いてもよいが、必要に応じて第２図（ｄ）に示すよ
うに、研磨やエツチングにより厚みを調整し、その後第
２図（ｅ）に示すようにｐ型ベース＠２６．ｎ＋型エミ
ッタ層２７を形成する。After thoroughly cleaning and drying these substrates, the polished surfaces are brought into close contact with each other and bonded in a clean atmosphere free from foreign matter such as dust, as shown in FIG. 2(C). Although this bonded body can have a considerable bonding strength without being heat-treated, it is heat-treated at 200° C. or higher, preferably about 1000° C., to make the bonding strength sufficiently strong. Thus n1 type 1
122 is buried, an element isolation layer and a collector extraction layer are formed, and an IC substrate is removed. This substrate may be used as it is, but if necessary, the thickness may be adjusted by polishing or etching as shown in FIG. 2(d), and then the p-type base@26 ．． An n+ type emitter layer 27 is formed.
こｔして本実施例によれば、エピタキシャル基板を用い
ることなく、極めて簡単な工程で浸れた素子特性を示す
バイポーラＩＣが得られる。According to this embodiment, a bipolar IC exhibiting excellent device characteristics can be obtained through an extremely simple process without using an epitaxial substrate.
上記実施例では、埋込み層が高濃度不純物層の場合を説
明したが、本発明はこれに限られるものではなく、導電
型や導電度が上記実施例とは異なる神々の埋込み層を必
要とする基板に適用して同様の効果が得られる。In the above embodiment, the case where the buried layer is a high concentration impurity layer has been explained, but the present invention is not limited to this, and requires a buried layer with a different conductivity type and degree from those in the above embodiment. A similar effect can be obtained by applying it to a substrate.
第１図はバイポーラＩＣの一般的な構造を示す図、第２
図（ａ）〜（ｅ）は本発明の一実施例によるバイポーラ
ＩＣの製造１碇を示す図である。
２１・・・ｐ＋＋Ｓ１基板（第１の半導体基板）、２２
・・・ｎ＋型型数散層埋込み層）、２３・・・ｎ−型３
ｉ基板（第２の半導体基板）、２４・・・ｎ＋型拡敞層
、２５・・・ｐ＋型型数散層２６・・・ｐ型ヘース層２
７・・・ｎ＋＋エミッタ層。
（ａ）
（ｂ）
第１は
第２０
２Figure 1 shows the general structure of a bipolar IC, Figure 2 shows the general structure of a bipolar IC.
Figures (a) to (e) are diagrams showing one anchor for manufacturing a bipolar IC according to an embodiment of the present invention. 21...p++S1 substrate (first semiconductor substrate), 22
...n+ type scattered buried layer), 23...n- type 3
i substrate (second semiconductor substrate), 24...n+ type diffusion layer, 25...p+ type scattering layer 26...p type Hess layer 2
7...n++ emitter layer. (a) (b) 1st is 20th 2nd
Claims (1)
って、鏡面研磨された第１の半導体基板の表面に選択的
に拡散層を形成する工程と、鏡面Ｆ＋ＩＩＩＩされた第
２の半導体基板を前記第１の半導体基板と研磨面どうし
を対向させて清浄な雰囲気下で接合させる工程とを備え
たことを特徴とづ−る半導体基板の製造方法。A method for manufacturing a semiconductor substrate having a buried layer therein, comprising the steps of selectively forming a diffusion layer on the surface of a mirror-polished first semiconductor substrate; A method for manufacturing a semiconductor substrate, comprising the step of bonding a first semiconductor substrate and polished surfaces facing each other in a clean atmosphere.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59092443A JPH071791B2 (en) | 1984-05-09 | 1984-05-09 | Method for manufacturing semiconductor substrate |
| DE8585300953T DE3583183D1 (en) | 1984-05-09 | 1985-02-13 | METHOD FOR PRODUCING A SEMICONDUCTOR SUBSTRATE. |
| EP85300953A EP0161740B1 (en) | 1984-05-09 | 1985-02-13 | Method of manufacturing semiconductor substrate |
| US06/701,516 US4638552A (en) | 1984-05-09 | 1985-02-14 | Method of manufacturing semiconductor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59092443A JPH071791B2 (en) | 1984-05-09 | 1984-05-09 | Method for manufacturing semiconductor substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60236243A true JPS60236243A (en) | 1985-11-25 |
| JPH071791B2 JPH071791B2 (en) | 1995-01-11 |
Family
ID=14054550
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59092443A Expired - Lifetime JPH071791B2 (en) | 1984-05-09 | 1984-05-09 | Method for manufacturing semiconductor substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH071791B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62128532A (en) * | 1985-11-30 | 1987-06-10 | Toshiba Corp | Semiconductor device and manufacture thereof |
| JPS62229820A (en) * | 1986-03-31 | 1987-10-08 | Toshiba Corp | Manufacture of semiconductor device |
| JPS6376485A (en) * | 1986-09-19 | 1988-04-06 | Komatsu Ltd | Manufacture of semiconductor device |
| WO2020084782A1 (en) * | 2018-10-26 | 2020-04-30 | ウルトラメモリ株式会社 | Semiconductor device and method of manufacturing same |
-
1984
- 1984-05-09 JP JP59092443A patent/JPH071791B2/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62128532A (en) * | 1985-11-30 | 1987-06-10 | Toshiba Corp | Semiconductor device and manufacture thereof |
| JPH0473615B2 (en) * | 1985-11-30 | 1992-11-24 | ||
| JPS62229820A (en) * | 1986-03-31 | 1987-10-08 | Toshiba Corp | Manufacture of semiconductor device |
| JPS6376485A (en) * | 1986-09-19 | 1988-04-06 | Komatsu Ltd | Manufacture of semiconductor device |
| WO2020084782A1 (en) * | 2018-10-26 | 2020-04-30 | ウルトラメモリ株式会社 | Semiconductor device and method of manufacturing same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH071791B2 (en) | 1995-01-11 |
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