JPH071791B2 - Method for manufacturing semiconductor substrate - Google Patents
Method for manufacturing semiconductor substrateInfo
- Publication number
- JPH071791B2 JPH071791B2 JP59092443A JP9244384A JPH071791B2 JP H071791 B2 JPH071791 B2 JP H071791B2 JP 59092443 A JP59092443 A JP 59092443A JP 9244384 A JP9244384 A JP 9244384A JP H071791 B2 JPH071791 B2 JP H071791B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- layer
- substrate
- polished
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 title claims description 34
- 239000004065 semiconductor Substances 0.000 title claims description 25
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 238000000034 method Methods 0.000 title description 16
- 238000009792 diffusion process Methods 0.000 claims description 11
- 238000010438 heat treatment Methods 0.000 claims description 11
- 238000005498 polishing Methods 0.000 claims description 5
- 238000003825 pressing Methods 0.000 claims description 3
- 239000012535 impurity Substances 0.000 description 6
- 230000007547 defect Effects 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 238000000605 extraction Methods 0.000 description 2
- 238000005304 joining Methods 0.000 description 2
- 230000003746 surface roughness Effects 0.000 description 2
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
- H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Bipolar Transistors (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Recrystallisation Techniques (AREA)
Description
【発明の詳細な説明】 〔発明の技術分野〕 本発明は、内部に埋込み層を有する半導体基板の製造方
法に関する。TECHNICAL FIELD OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor substrate having a buried layer therein.
バイポーラICのように、素子基板の内部に不純物や濃度
の異なる埋込み層を必要とするものは多い。第１図はそ
の様な一例として、一般的なバイポーラICを示してい
る。この製造工程は次の通りである。先ず、ｐ形Si基板
11に選択拡散によりコレクタ埋込み層となるn+層12を形
成する。次いでこの基板上にエピタキシャル成長法によ
ってn-層13を形成する。こうして得られたエピタキシャ
ル基板にｐベース層14,n+ソース層15を順次拡散形成し
てトランジスタを得る。16は素子分離用のp+拡散層であ
り、17はコレクタ電極取出しのためのn+拡散層である。Many devices, such as bipolar ICs, require buried layers with different impurities or concentrations inside the element substrate. FIG. 1 shows a general bipolar IC as such an example. This manufacturing process is as follows. First, p-type Si substrate
An n + layer 12 to be a collector buried layer is formed on 11 by selective diffusion. Then, an n − layer 13 is formed on this substrate by an epitaxial growth method. A p base layer 14 and an n + source layer 15 are sequentially diffused and formed on the thus obtained epitaxial substrate to obtain a transistor. Reference numeral 16 is a p + diffusion layer for element isolation, and 17 is an n + diffusion layer for extracting a collector electrode.
従来のこの様な方法では、埋込み層の深さはエピタキシ
ャル成長層の厚みで決まる。しかしながら、エピタキシ
ャル法では成長速度に限界があるため、厚い層を得るた
めには極めて長時間を要する。しかも高度の技術を必要
とし、制御が難しいために欠陥等を生じ易い。また長時
間のエピタキシャル成長工程で埋込み層の不純物が再拡
散するため、埋込み層上のエピタキシャル層の厚み制御
も難しい。In such a conventional method, the depth of the buried layer is determined by the thickness of the epitaxial growth layer. However, since the growth rate is limited in the epitaxial method, it takes a very long time to obtain a thick layer. In addition, since it requires a high level of technology and is difficult to control, defects or the like are likely to occur. In addition, since the impurities in the buried layer are re-diffused in the epitaxial growth process for a long time, it is difficult to control the thickness of the epitaxial layer on the buried layer.
本発明は上記の点に鑑みてなされたもので、簡単な工程
で制御性よく埋込み層を形成するようにした半導体基板
の製造方法を提供することを目的とする。The present invention has been made in view of the above points, and an object of the present invention is to provide a method for manufacturing a semiconductor substrate in which a buried layer is formed with good controllability in a simple process.
本発明は、２枚の半導体基板を直接接合させて一枚の半
導体基板を得るという方法を利用する。このような半導
体同士の接合によって不純物濃度の異なる層を内部に形
成する方法自体は、合金形半導体接合法として古くから
知られた技術である。しかしこの方法は現在一般に利用
されていない。その理由は、この方法では、1300℃とい
う、半導体の融点に近い高温まで加熱し加圧する必要が
あり、その結果、半導体結晶に多くの欠陥や変成層が形
成されるためである。The present invention utilizes a method of directly bonding two semiconductor substrates to obtain one semiconductor substrate. The method itself for forming layers having different impurity concentrations by joining such semiconductors is a technique known from old times as an alloy type semiconductor joining method. However, this method is not commonly used at present. The reason is that this method requires heating and pressing to a high temperature of 1300 ° C., which is close to the melting point of the semiconductor, and as a result, many defects and metamorphic layers are formed in the semiconductor crystal.
これに対し、本発明者らは、半導体基板の表面を充分に
鏡面研磨して、その研磨面どうしを充分清浄な雰囲気下
で密着させるだけ、特に加圧や加熱を行なわなくても、
強固な接合体が得られることを見出した。この接合体は
200℃以上の温度で熱処理すれば、接合がより強固なも
のとなる。この接合のメカニズムは未だ不明な点が多い
が、鏡面研磨面に形成される自然酸化膜が重要な役割を
果たしているらしいことが推測される。On the other hand, the present inventors have sufficiently mirror-polished the surface of the semiconductor substrate and brought the polished surfaces into close contact with each other in a sufficiently clean atmosphere, without particularly applying pressure or heating,
It was found that a strong joined body can be obtained. This zygote
If the heat treatment is performed at a temperature of 200 ° C or higher, the bond becomes stronger. There are still many unclear points regarding the mechanism of this bonding, but it is assumed that the natural oxide film formed on the mirror-polished surface seems to play an important role.
本発明は、この新しい技術を利用して、先ず鏡面研磨さ
れた第１の半導体基板の表面に選択的に拡散層を形成
し、これを鏡面研磨された第２の半導体基板と研磨面同
士を対向させて清浄な雰囲気下で密着させて接合するこ
とにより、埋込み層を有する半導体基板を得る。ここ
で、熱処理を行なわなくても強固な接合体を得られる
が、熱処理を施すことにより、更に強固な接合体が得ら
れる。熱処理温度は、200℃程度以上であればよく、望
ましくは1000℃程度であるが、1300℃程度まで高くする
と結晶欠陥などの発生があるため、ここまで高くするこ
とは出来ない。また、鏡面研磨面の表面粗さは100オン
グストローム以下であることが望ましい。熱処理温度は
200℃程度以上であればよく、望ましくは1000℃程度で
あるが、1300℃程度まで高くすると結晶欠陥などの発生
があるため、ここまで高くすることは出来ない。The present invention utilizes this new technique to selectively form a diffusion layer on the surface of a first semiconductor substrate that has been mirror-polished, and to form a diffusion layer between the second semiconductor substrate that has been mirror-polished and the polishing surface. The semiconductor substrates having a buried layer are obtained by facing each other and closely contacting each other in a clean atmosphere to bond them. Here, a strong joined body can be obtained without performing heat treatment, but a stronger joined body can be obtained by performing heat treatment. The heat treatment temperature may be about 200 ° C. or higher, preferably about 1000 ° C., but if it is raised to about 1300 ° C., crystal defects may occur, so it cannot be raised to this level. Further, the surface roughness of the mirror-polished surface is preferably 100 angstroms or less. Heat treatment temperature
It may be about 200 ° C or higher, preferably about 1000 ° C, but if it is raised to about 1300 ° C, crystal defects may occur, so it cannot be raised to this level.
本発明によれば、長時間のエピタキシャル成長等を要せ
ず、簡単に埋込み層を持つ半導体基板を得ることができ
る。しかも熱処理は基本的に不要なので、埋込み層が高
不純物濃度層である場合にも不純物の再拡散は最少限に
押えられ、埋込み層の深さや濃度を制御性よく設定する
ことができる。従ってICその他の素子製造の工程短縮化
や素子性能の向上を図ることができる。According to the present invention, a semiconductor substrate having a buried layer can be easily obtained without requiring epitaxial growth for a long time. Moreover, since the heat treatment is basically unnecessary, the re-diffusion of impurities is suppressed to a minimum even when the buried layer is a high impurity concentration layer, and the depth and the concentration of the buried layer can be set with good controllability. Therefore, it is possible to shorten the process of manufacturing the IC and other elements and improve the element performance.
以下本発明をバイポーラICに適用した実施例について第
２図（ａ）〜（ｅ）を用いて説明する。An embodiment in which the present invention is applied to a bipolar IC will be described below with reference to FIGS.
第２図（ａ）は、表面粗さ500Å以下に充分平滑に鏡面
研磨されたｐ型Si基板（第１の半導体基板）21の表面に
n+型層22を選択的に拡散形成した状態を示している。n+
型層22はコレクタ埋込み層となるものである。第２図
（ｂ）は同様に鏡面研磨されたn-Si基板（第２の半導体
基板）23であり、その表面にコレクタ取出し層となるn+
型層24及び素子分離層となるp+型層25が拡散形成された
状態を示している。これらの基板を充分に洗浄し、乾燥
させた後、ゴミなどの異物が介在しない清浄な雰囲気中
で第２図（ｃ）に示すように研磨面どうしを密着させて
接合する。この接合体は熱処理をしなくてもかなりの接
合強度が得られるが、200℃以上、好ましくは1000℃程
度で熱処理して接合強度を充分強固なものとする。こう
してn+型層22が埋め込まれ、素子分離層とコレクタ取出
し層が形成されたIC基板が得られる。この基板はそのま
ま用いてもよいが、必要に応じて第２図（ｄ）に示すよ
うに、研磨やエッチングにより厚みを調整し、その後第
２図（ｅ）に示すようにｐ型ベース層26,n+型エミッタ
層27を形成する。FIG. 2 (a) shows a surface of a p-type Si substrate (first semiconductor substrate) 21 which is sufficiently smooth and mirror-polished to have a surface roughness of 500 Å or less.
The state where the n + type layer 22 is selectively diffused and formed is shown. n +
The mold layer 22 serves as a buried layer of the collector. FIG. 2B shows an n − Si substrate (second semiconductor substrate) 23 similarly mirror-polished, and has n + serving as a collector extraction layer on its surface.
The figure shows a state in which the mold layer 24 and the p + type layer 25 serving as an element isolation layer are formed by diffusion. After thoroughly cleaning and drying these substrates, the polishing surfaces are brought into close contact with each other and bonded in a clean atmosphere in which no foreign matter such as dust intervenes, as shown in FIG. 2 (c). Although this bonded body can obtain a considerable bonding strength without heat treatment, it is heat-treated at 200 ° C. or higher, preferably about 1000 ° C. to make the bonding strength sufficiently strong. In this way, the n + type layer 22 is buried, and an IC substrate in which the element isolation layer and the collector extraction layer are formed is obtained. This substrate may be used as it is, but if necessary, the thickness is adjusted by polishing or etching as shown in FIG. 2 (d), and then the p-type base layer 26 is formed as shown in FIG. 2 (e). , n + -type emitter layer 27 is formed.
こうして本実施例によれば、エピタキシャル基板を用い
ることなく、極めて簡単な工程で優れた素子特性をバイ
ポーラICが得られる。Thus, according to the present embodiment, a bipolar IC having excellent device characteristics can be obtained by an extremely simple process without using an epitaxial substrate.
上記実施例では、埋込み層が高濃度不純物層の場合を説
明したが、本発明はこれに限られるものではなく、導電
型や導電度が上記実施例とは異なる種々の埋込み層を必
要とする基板に適用して同様の効果が得られる。In the above embodiments, the case where the buried layer is a high concentration impurity layer has been described, but the present invention is not limited to this, and various buried layers having different conductivity types and conductivity from those of the above embodiments are required. The same effect can be obtained when applied to a substrate.
第１図はバイポーラICの一般的な構造を示す図、第２図
（ａ）〜（ｅ）は本発明の一実施例によるバイポーラIC
の製造工程を示す図である。 21……p+型Si基板（第１の半導体基板）、22……n+型拡
散層（埋込み層）、23……n-型Si基板（第２の半導体基
板）、24……n+型拡散層、25……p+型拡散層、26……ｐ
型ベース層、27……n+型エミッタ層。FIG. 1 is a diagram showing a general structure of a bipolar IC, and FIGS. 2 (a) to (e) are bipolar ICs according to an embodiment of the present invention.
It is a figure which shows the manufacturing process of. 21 …… p + type Si substrate (first semiconductor substrate), 22 …… n + type diffusion layer (buried layer), 23 …… n − type Si substrate (second semiconductor substrate), 24 …… n + Type diffusion layer, 25 …… p + type diffusion layer, 26 …… p
Type base layer, 27 …… n + type emitter layer.
フロントページの続き (72)発明者 大和田 義明 神奈川県川崎市幸区小向東芝町１番地 株 式会社東芝多摩川工場内 (56)参考文献 特開 昭56−13773（ＪＰ，Ａ) 特公 昭46−8013（ＪＰ，Ｂ１) 特公 昭49−26455（ＪＰ，Ｂ１) 特公 昭39−17869（ＪＰ，Ｂ１) 特公 昭50−2357（ＪＰ，Ｂ１) 特公 昭50−13155（ＪＰ，Ｂ１)Front page continuation (72) Inventor Yoshiaki Owada, No. 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Inside the Tamagawa Factory, Toshiba Corporation (56) Reference JP-A-56-13773 (JP, A) JP-B-46 -8013 (JP, B1) JP-B 49-26455 (JP, B1) JP-B 39-17869 (JP, B1) JP-B 50-2357 (JP, B1) JP-B 50-13155 (JP, B1) )
Claims (1)
する方法であって、鏡面研磨された第１の半導体基板の
表面に選択的に拡散層を形成する工程と、鏡面研磨され
た第２の半導体基板を前記第１の半導体基板と研磨面ど
うしを対向させて清浄な雰囲気下で密着させて接合する
接合工程と、前記接合工程の後に加圧することなく加熱
することで接合強度を上昇する加熱工程とを備えたこと
を特徴とする半導体基板の製造方法。1. A method of manufacturing a semiconductor substrate having a buried layer therein, comprising a step of selectively forming a diffusion layer on the surface of a mirror-polished first semiconductor substrate and a mirror-polished second surface. And a bonding step of bonding the semiconductor substrate of the first semiconductor substrate to the first semiconductor substrate such that the polishing surfaces of the semiconductor substrate and the polishing surfaces are in close contact with each other in a clean atmosphere, and the bonding strength is increased by heating without pressing after the bonding step. A method of manufacturing a semiconductor substrate, comprising: a heating step.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59092443A JPH071791B2 (en) | 1984-05-09 | 1984-05-09 | Method for manufacturing semiconductor substrate |
| DE8585300953T DE3583183D1 (en) | 1984-05-09 | 1985-02-13 | METHOD FOR PRODUCING A SEMICONDUCTOR SUBSTRATE. |
| EP85300953A EP0161740B1 (en) | 1984-05-09 | 1985-02-13 | Method of manufacturing semiconductor substrate |
| US06/701,516 US4638552A (en) | 1984-05-09 | 1985-02-14 | Method of manufacturing semiconductor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59092443A JPH071791B2 (en) | 1984-05-09 | 1984-05-09 | Method for manufacturing semiconductor substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60236243A JPS60236243A (en) | 1985-11-25 |
| JPH071791B2 true JPH071791B2 (en) | 1995-01-11 |
Family
ID=14054550
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59092443A Expired - Lifetime JPH071791B2 (en) | 1984-05-09 | 1984-05-09 | Method for manufacturing semiconductor substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH071791B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62128532A (en) * | 1985-11-30 | 1987-06-10 | Toshiba Corp | Semiconductor device and manufacture thereof |
| JPH07107924B2 (en) * | 1986-03-31 | 1995-11-15 | 株式会社東芝 | Method for manufacturing semiconductor device |
| JPS6376485A (en) * | 1986-09-19 | 1988-04-06 | Komatsu Ltd | Manufacture of semiconductor device |
| WO2020084782A1 (en) * | 2018-10-26 | 2020-04-30 | ウルトラメモリ株式会社 | Semiconductor device and method of manufacturing same |
-
1984
- 1984-05-09 JP JP59092443A patent/JPH071791B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60236243A (en) | 1985-11-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH05251292A (en) | Manufacture of semiconductor device | |
| JPH01315159A (en) | Dielectric-isolation semiconductor substrate and its manufacture | |
| JPH0783050B2 (en) | Method for manufacturing semiconductor device | |
| JPS60121715A (en) | Bonding method for semiconductor wafer | |
| JPH0246722A (en) | Manufacture of semiconductor device | |
| JPH071791B2 (en) | Method for manufacturing semiconductor substrate | |
| JPH05109678A (en) | Manufacture of soi substrate | |
| JPH0691006B2 (en) | Method for joining semiconductor wafers | |
| JPH02237121A (en) | Manufacture of semiconductor device | |
| JP2930194B2 (en) | SOI wafer and method for manufacturing the same | |
| JPS61182216A (en) | Bonding method of semiconductor device | |
| JPH03181115A (en) | Manufacture of semiconductor substrate | |
| JP2621851B2 (en) | Semiconductor substrate bonding method | |
| JP2766992B2 (en) | Method for manufacturing semiconductor device | |
| JPH01305534A (en) | Manufacture of semiconductor substrate | |
| JPH04199632A (en) | Soi wafer and manufacture thereof | |
| JPH01226166A (en) | Manufacture of semiconductor device substrate | |
| JPS6271214A (en) | Jointing method for semiconductor substrate | |
| JPH0479209A (en) | Manufacture of soi substrate | |
| JP3795150B2 (en) | Oxide film bonded substrate and manufacturing method thereof | |
| JPH06338604A (en) | Manufacture of semiconductor substrate | |
| JPH0212920A (en) | Manufacture of semiconductor device | |
| JPH01115143A (en) | Manufacture of semiconductor substrate | |
| JPH07193203A (en) | Manufacture of semiconductor substrate | |
| JP2811006B2 (en) | Method for manufacturing semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |