JPH04199632A - Soi wafer and manufacture thereof - Google Patents
Soi wafer and manufacture thereofInfo
- Publication number
- JPH04199632A JPH04199632A JP32597290A JP32597290A JPH04199632A JP H04199632 A JPH04199632 A JP H04199632A JP 32597290 A JP32597290 A JP 32597290A JP 32597290 A JP32597290 A JP 32597290A JP H04199632 A JPH04199632 A JP H04199632A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- semiconductor
- film
- active layer
- soi wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 239000004065 semiconductor Substances 0.000 claims abstract description 91
- 239000000758 substrate Substances 0.000 claims abstract description 51
- 238000000034 method Methods 0.000 claims abstract description 32
- 239000012535 impurity Substances 0.000 claims abstract description 19
- 235000012431 wafers Nutrition 0.000 claims description 36
- 238000005247 gettering Methods 0.000 claims description 25
- 229910001385 heavy metal Inorganic materials 0.000 claims description 9
- 238000005229 chemical vapour deposition Methods 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- 239000012212 insulator Substances 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 150000001412 amines Chemical class 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000008119 colloidal silica Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
- H01L21/3226—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering of silicon on insulator
Abstract
Description
【発明の詳細な説明】
〔概要〕
ＳＯＩうエバ及びそれを製造する方法の改良に関し、
簡単な手段を採ることに依り、不′ＩｋＴｈをゲッタリ
ングする為のシンクをもったＳＯＩウエノ＼が得られる
ようにすることを目的とし、
半導体支持基板上に第二の絶縁膜とゲ・ンタリングのシ
ンク膜と第一の絶縁膜と半導体活性層とが順に積層され
てなるよう構成する。[Detailed Description of the Invention] [Summary] Regarding the improvement of the SOI Eva and its manufacturing method, an SOI Eva with a sink for gettering inactive IkTh can be obtained by taking simple measures. A second insulating film, a gaintering sink film, a first insulating film, and a semiconductor active layer are laminated in this order on a semiconductor supporting substrate.
［産業上の利用分野］
本発明は、ＳＯＩ （ｓｉｌｉｃｏｎ ｏｎ １
ｎｓｕｌａｔｏｒ）ウェハ及びその製造方法の改良に関
する。[Industrial Application Field] The present invention is directed to SOI (silicon on 1
nsulator) wafer and its manufacturing method.
ＳＯＩ構造を利用した半導体装置は、接合容量及び配線
容量を低減することができ、従って、素子特性は向上す
る。A semiconductor device using an SOI structure can reduce junction capacitance and wiring capacitance, and therefore improve device characteristics.
ＳＯＩ構造のなかでも、素子が作り込まれる活性層の結
晶性、或いは、従来からの半導体装置の製造プロセスと
の整合性などの面から貼り合わせＳＯＩウェハが注目さ
れているが、未だ、解消されなければならない問題を抱
えている。Among SOI structures, bonded SOI wafers are attracting attention because of the crystallinity of the active layer in which elements are built, and their compatibility with conventional semiconductor device manufacturing processes, but there are still unresolved issues. I have a problem that I have to deal with.
第７図は従来のＳＯＩウェハを説明する為の要部切断側
面図を表している。FIG. 7 shows a cutaway side view of a main part for explaining a conventional SOI wafer.
図に於いて、１はＳｉ活性層、２はＳｉＯ□からなる絶
縁膜、３はＳｔ半導体支持基板をそれぞれ示している。In the figure, 1 indicates a Si active layer, 2 an insulating film made of SiO□, and 3 an St semiconductor supporting substrate.
図示のＳＯＩウェハを作成するには、次のような工程を
採る。To create the illustrated SOI wafer, the following steps are taken.
（１）Ｓｉ活性層１の母体となるＳｉ半導体基板にｍ縁
ＷＡ２を形成する。尚、絶縁膜２はＳｉ半導体支持基板
３側に形成したり、或いは、それ等の両方に形成しても
良い。(1) An m-edge WA2 is formed on the Si semiconductor substrate that is the base of the Si active layer 1. Note that the insulating film 2 may be formed on the Si semiconductor support substrate 3 side, or may be formed on both of them.
（２）絶縁膜２で覆われたＳｉ半導体基板とＳｔ半導体
支持基板３とを貼り合わせる。(2) The Si semiconductor substrate covered with the insulating film 2 and the St semiconductor support substrate 3 are bonded together.
（３）Ｓｉ半導体基板を研削及び研磨を行って薄膜化さ
れたＳｉ活性層ｌとする。(3) Grind and polish the Si semiconductor substrate to form a thin Si active layer l.
一般に、半導体装置の製造プロセス中では、製造装置や
雰囲気からウェハに重金属などの不純物が入り込んでく
る。その不純物は、半導体装置に於けるリーク電流を増
大させるなど、特性に悪影響を及ぼす為、製造歩留りを
低下させる。Generally, during the manufacturing process of semiconductor devices, impurities such as heavy metals enter the wafer from the manufacturing equipment or the atmosphere. The impurities adversely affect the characteristics of the semiconductor device, such as increasing leakage current, thereby reducing manufacturing yield.
通常、前記のようなことが起こらないように、重金属な
どの不純物をウェハのデバイス作成領域外に閉じ込める
、所謂、ゲッタリングを行う。例えば、バルク・ウェハ
の場合、その裏面や中央部分をゲッタリングのシンクと
して用いるようにしている。Normally, so-called gettering is performed to confine impurities such as heavy metals outside the device formation region of the wafer to prevent the above-mentioned occurrence. For example, in the case of a bulk wafer, its back surface or central portion is used as a gettering sink.
然しなから、第７図について説明したＳＯＩウェハの場
合には、絶縁膜２上のＳｉ活性層ｌは全てデバイス作成
領域となるので、ゲッタリングのシンクを設けることが
できない。However, in the case of the SOI wafer described with reference to FIG. 7, the entire Si active layer 1 on the insulating film 2 becomes a device formation region, and therefore no gettering sink can be provided.
従って、不純物はＳｉ活性層１と絶縁膜２との界面に残
り、デバイスの特性を劣化させることになる。Therefore, the impurities remain at the interface between the Si active layer 1 and the insulating film 2, deteriorating the characteristics of the device.
本発明は、簡単な手段を採ることに依り、不純物をゲッ
タリングする為のシンクをもったＳＯＩウェハが得られ
るようにする。The invention makes it possible to obtain SOI wafers with sinks for gettering impurities by taking simple measures.
第１図は本発明の詳細な説明する為のＳＯＩウェハの要
部切断側面図を表している。FIG. 1 shows a cutaway side view of a main part of an SOI wafer for explaining the present invention in detail.
図に於いて、１１は半導体活性層、１２は第一の絶縁膜
、１３は重金属などの不純物に対するシンク膜、１４は
第二の絶縁膜、１５は半導体支持基板をそれぞれ示す。In the figure, 11 is a semiconductor active layer, 12 is a first insulating film, 13 is a sink film for impurities such as heavy metals, 14 is a second insulating film, and 15 is a semiconductor support substrate.
図示のＳＯ■ウェハに於ける第一の絶縁膜１２の膜厚は
半導体活性層ｌｌ中の不純物が半導体装置の製造プロセ
ス中の熱処理でシンク膜１３にまで拡散し得る程度の厚
さとし、また、第二の絶縁膜１２の膜厚はＳＯＩウェハ
としてソフト・エラーや雑音などに対する耐性を充分に
発揮し得る程度にする。The thickness of the first insulating film 12 in the illustrated SO2 wafer is set to such a degree that impurities in the semiconductor active layer 11 can be diffused into the sink film 13 during heat treatment during the manufacturing process of the semiconductor device, and The thickness of the second insulating film 12 is set to such an extent that the SOI wafer can exhibit sufficient resistance to soft errors, noise, and the like.
前記したところから、本発明に依るＳＯＩウェハ及びそ
の製造方法に於いては、
（１）半導体支持基板（例えばＳｉ半導体支持基板１５
）上に第二の絶縁膜（例えばＳｉｎ、からなる第二の絶
縁膜１４）とゲッタリングのシンク膜（例えば多結晶Ｓ
ｉからなるゲッタリングのシンク膜１３）と第一の絶縁
膜（例えばＳｉＯ□からなる第一の絶縁膜１２）と半導
体活性層（例えばＳｉ活性Ｎ１１）とが順に積層されて
なること
を特徴とするか、或いは、
（２）前記（１）に於いて、第一の絶縁膜は半導体装置
を製造するプロセス中に半導体活性層に侵入する重金属
等の不純物が通り抜けてゲッタリングのシンク膜に達し
得る厚さ（例えば１１００（ｎ〕以下）であること
を特徴とするか、或いは、
（３）半導体基板に第一の絶縁膜とゲッタリングのシン
ク膜と第二の絶縁膜とを順に形成し、次いで、前記半導
体基板に於ける第二の絶縁膜に半導体支持基板を対向さ
せて貼り合わせ、次いで、前記半導体基板を薄膜化し半
導体活性層とする工程
が含まれてなるか、或いは、
（４）表面に第一の絶縁膜とゲッタリングのシンク膜と
を順に形成した半導体基板並びに表面に第二の絶縁膜を
形成した半導体支持基板とを用意し、次いで、前記半導
体基板に於けるゲッタリングのシンク膜と前記半導体支
持基板に於ける第二の絶縁膜とを対向させて貼り合わせ
、次いで、前記半導体基板を薄膜化し半導体活性層とす
る工程
が含まれてなるか、或いは、
（５）表面に第一の絶縁膜を形成した半導体基板並びに
表面に第二の絶縁膜とゲッタリングのシンク膜とを順に
形成した半導体支持基板とを用意し、次いで、前記半導
体基板に於ける第一の絶縁膜と前記半導体支持基板に於
けるゲッタリングのシンク膜とを対向させて貼り合わせ
、次いで、前記半導体基板を薄膜化し半導体活性層とす
る工程
、が含まれてなるか、或いは、
（６）前記（３）、或いは（４）、或いは（５）に於い
て、半導体基板に半導体装置を製造するプロセス中に半
導体活性層に侵入する重金属などの不純物が通り抜けて
ゲッタリングのシンク膜に達し得る厚さの第一の絶縁膜
を形成すること
が含まれてなるか、或いは、
（７）前記（３）、或いは（４）、或いは（５）、或い
は（６）に於いて、半導体基板がＳｔであってＳｉＯ□
からなる第一の絶縁膜が熱酸化法を適用して生成され、
また、第二の絶縁膜が化学気相堆積法を適用して形成さ
れること
を特徴とする。As described above, in the SOI wafer and the manufacturing method thereof according to the present invention, (1) a semiconductor support substrate (for example, a Si semiconductor support substrate 15);
) on which a second insulating film (e.g. second insulating film 14 made of Sin) and a gettering sink film (e.g. polycrystalline S) are formed.
A gettering sink film 13) made of i, a first insulating film (for example, the first insulating film 12 made of SiO□), and a semiconductor active layer (for example, Si active N11) are laminated in this order. or (2) In (1) above, the first insulating film allows impurities such as heavy metals that invade the semiconductor active layer during the process of manufacturing the semiconductor device to pass through and reach the gettering sink film. (3) forming a first insulating film, a gettering sink film, and a second insulating film in order on a semiconductor substrate; Then, the step of bonding a semiconductor support substrate to the second insulating film of the semiconductor substrate so as to face it, and then thinning the semiconductor substrate to form a semiconductor active layer, or (4) ) Prepare a semiconductor substrate on which a first insulating film and a gettering sink film are formed in order, and a semiconductor support substrate on which a second insulating film is formed, and then perform gettering on the semiconductor substrate. (5) The sink film and the second insulating film of the semiconductor support substrate are bonded together so as to face each other, and then the semiconductor substrate is thinned to form a semiconductor active layer, or (5) A semiconductor substrate having a first insulating film formed on its surface and a semiconductor supporting substrate having a second insulating film and a gettering sink film formed in this order on its surface are prepared, and then the first insulating film on the semiconductor substrate is prepared. (6) The step of bonding an insulating film and a gettering sink film on the semiconductor support substrate so as to face each other, and then thinning the semiconductor substrate to form a semiconductor active layer, or (6) In (3), (4), or (5) above, impurities such as heavy metals that invade the semiconductor active layer during the process of manufacturing a semiconductor device on a semiconductor substrate may pass through and reach the gettering sink film. or (7) in (3), (4), (5), or (6) above, the semiconductor substrate is St and SiO□
A first insulating film consisting of is produced by applying a thermal oxidation method,
Further, the second insulating film is formed by applying a chemical vapor deposition method.
前記手段を採ることに依り、半導体装置の製造プロセス
中に於いて半導体活性層１１に侵入した不純物は、第一
の絶縁Ｍ１２を通り抜けてシンク膜１３に達し、そこに
閉じ込められてしまうがらＳＯＩウェハを用いた半導体
装置の特性を大きく向上させることが可能であり、しか
も、第一の絶縁Ｗｉ！１２並びに第二の絶縁膜１４が存
在することから、α線などの放射線に対する耐性が充分
に高くなり、また、ＳＯＩウェハの一般的な効果、例え
ば、表面から第二絶縁膜１４に達す゛る絶縁領域を形成
することで雑音に対する耐性が高くなる、などの効果も
当然に発揮することができる。By adopting the above method, impurities that have entered the semiconductor active layer 11 during the manufacturing process of the semiconductor device pass through the first insulating layer M12 and reach the sink film 13, and are trapped there, while the impurities are removed from the SOI wafer. It is possible to greatly improve the characteristics of a semiconductor device using the first insulating Wi! 12 and the second insulating film 14, the resistance to radiation such as alpha rays is sufficiently high. Naturally, by forming the region, effects such as increased resistance to noise can also be achieved.
第２図乃至第６図は第１図に示した本発明のＳＯ■ウェ
ハを作成する工程を説明するための工程要所に於けるＳ
ＯＩウェハの要部切断側面図を表し、以下、これ等の図
を参照しつつ詳細に解説する。尚、第１図に於いて用い
た記号と同記号は同部分を表すか或いは同じ意味を持つ
ものとする。FIGS. 2 to 6 show S at important points in the process for explaining the process of creating the SO wafer of the present invention shown in FIG. 1.
It shows a cutaway side view of the main part of the OI wafer, and will be described in detail below with reference to these figures. Note that the same symbols as those used in FIG. 1 represent the same parts or have the same meaning.
第２図参照
熱酸化法を適用することに依り、Ｓｉ半導体基板１１’
に厚さが例えば２０（ｎｍ）程度のＳｉＯ□からなる絶
縁膜１２を形成する。By applying the thermal oxidation method (see FIG. 2), the Si semiconductor substrate 11'
An insulating film 12 made of SiO□ and having a thickness of, for example, about 20 (nm) is formed thereon.
第３図参照 化学気相堆積（ｃｈｅｍｉｃａｌ ｖａｐ。See Figure 3 chemical vapor deposition (chemical vapor deposition)
ｕｒ ｄｅｐｏｓｉｔｉｏｎ：ＣＶＤ）法を適用する
ことに依り、絶縁膜１２上に厚さが例えば５００（ｎｍ
）程度の多結晶Ｓｉからなるシンク）ｌ！１３を形成す
る。By applying the ur deposition (CVD) method, a film having a thickness of, for example, 500 (nm) is formed on the insulating film 12.
) l! form 13.
第４図参照
ＣＶＤ法を適用することに依り、多結晶Ｓｉからなるシ
ンク膜１３上に厚さが例えばｌ（μｍ〕程度のＳｉｎ、
からなる第二の絶縁膜１４を形成する。By applying the CVD method as shown in FIG.
A second insulating film 14 is formed.
第５図参照
Ｓｉ半導体支持基板１５を用意し、Ｓｉ半導体基板１１
′に於ける第二の絶縁膜１４と対向させ、貼り合わせる
。Refer to FIG. 5, a Si semiconductor support substrate 15 is prepared, and a Si semiconductor substrate 11 is prepared.
1 and the second insulating film 14 in step 1 and bonded to each other.
この貼り合わせは、Ｓｉ半導体支持基板１５とＳｉ半導
体基板１１′の第二の絶縁膜１４とを温度７００［”Ｃ
）の雰囲気で密着させ、次いで、温度を１０００（”Ｃ
）とした窒素雰囲気で３０［分］間の熱処理を施すこと
に依って行う。In this bonding process, the Si semiconductor support substrate 15 and the second insulating film 14 of the Si semiconductor substrate 11' are heated at a temperature of 700°C.
), and then the temperature was increased to 1000 ("C
) in a nitrogen atmosphere for 30 minutes.
第６図参照
アミンの水溶液にコロイダル・シリカを僅かに混入した
研磨剤、及び、不織布を用い、Ｓｉ半導体基板１１′の
表面を研磨して厚さ例えば１［μｍ］のＳｉ活性層１１
とする。Refer to FIG. 6. The surface of the Si semiconductor substrate 11' is polished using a polishing agent prepared by mixing a slight amount of colloidal silica in an aqueous solution of amine, and a non-woven cloth to form a Si active layer 11 with a thickness of, for example, 1 [μm].
shall be.
このようにして作成したＳＯＩウェハでは、そのＳｉ活
性１１１に半導体装置を作り込むプロセス中に重金属な
どの不純物が侵入しても、第一の絶縁ｆｆ１２を通り抜
けて多結晶Ｓｔからなるシンク膜１３に達する。多結晶
Ｓｉからなるシンク膜１３に於いては、多結晶Ｓｉの粒
界がゲッタリングのシンクとなり得るので、不純物を充
分に閉じ込めることができるものである。In the SOI wafer created in this manner, even if impurities such as heavy metals enter the Si active layer 111 during the process of fabricating semiconductor devices, they will pass through the first insulation ff12 and enter the sink film 13 made of polycrystalline St. reach In the sink film 13 made of polycrystalline Si, the grain boundaries of polycrystalline Si can serve as sinks for gettering, so impurities can be sufficiently confined.
本発明に於いて、ゲッタリングのシンク膜の材料として
は、多結晶Ｓｉのみならず、例えばアモルファスＳｔ膜
、或いは、アモルファスＳｉ窒化膜などを用いることが
できる。In the present invention, as the material for the gettering sink film, not only polycrystalline Si but also, for example, an amorphous St film or an amorphous Si nitride film can be used.
本発明に依るＳＯＩウェハ及びその製造方法に於いては
、半導体支持基板上に第二の絶縁膜とゲッタリングのシ
ンク膜と第一の絶縁膜と半導体活性層とが順に積層され
る。In the SOI wafer and the method for manufacturing the same according to the present invention, the second insulating film, the gettering sink film, the first insulating film, and the semiconductor active layer are laminated in this order on a semiconductor support substrate.
前記構成を採ることに依って、半導体装置の製造プロセ
ス中に於いて半導体活性層に侵入した不純物は、第一の
絶縁膜を通り抜けてシンク膜に達し、そこに閉じ込めら
れてしまうからＳＯＩウェハを用いた半導体装置の特性
を大きく向上させることが可能であり、しかも、第一の
絶縁膜並びに第二の絶縁膜が存在することから、α線な
どの放射線に対する耐性が充分に高くなり、また、ＳＯ
Ｉウェハの一般的な効果、例えば、表面から第二絶縁膜
に達する絶縁領域を形成することで雑音に対する耐性が
高（なる、などの効果も当然に発揮することができる。By employing the above structure, impurities that invade the semiconductor active layer during the manufacturing process of the semiconductor device pass through the first insulating film, reach the sink film, and are trapped there, making it difficult to use the SOI wafer. It is possible to greatly improve the characteristics of the semiconductor device used, and since the first insulating film and the second insulating film are present, the resistance to radiation such as alpha rays is sufficiently high, and S.O.
The general effects of I-wafers, such as high resistance to noise, can be naturally achieved by forming an insulating region extending from the surface to the second insulating film.
第１図は本発明の詳細な説明する為のＳＯ■ウェハの要
部切断側面図、第２図乃至第６図は第１図に示した本発
明のＳＯＩウェハを作成する工程 。
を説明するための工程要所に於けるＳ○■ウェハの要部
切断側面図、第７図は従来のＳＯＩウェハを説明する為
の要部切断側面図を表している。
図に於いて、１１は半導体活性層、１２は第一の絶縁膜
、１３は重金属などの不純物に対するシンク膜、１４は
第二の絶縁膜、１５は半導体支持基板をそれぞれ示す。
特許出願人 富士通株式会社
代理人弁理士 相 谷 昭 司
代理人弁理士 渡 邊 弘 −
１３シンク膜
原理を説明する為のＳＯＩウェハの要部切断側面図第１
図
工程要所に於けるＳＯＩウェハの要部切断側面図工程要
所に於けるＳＯＩウェハの要部切断側面図第３図
１４・第二の絶縁膜
工程要所に於けるＳＯＩウェハの要部切断側面図工程要
所に於けるＳＯＩウェハの要部切断側面図第５図
工程要所に於けるＳＯＩウェハの要部切断側面図第６図
従来のＳｏ１ウェハの要部切断側面図
第７図FIG. 1 is a cross-sectional side view of an essential part of an SOI wafer for explaining the present invention in detail, and FIGS. 2 to 6 show steps for producing the SOI wafer of the present invention shown in FIG. FIG. 7 shows a cutaway side view of a main part of an SOI wafer at key points in the process for explaining the process. FIG. 7 shows a cutaway side view of a main part of a conventional SOI wafer. In the figure, 11 is a semiconductor active layer, 12 is a first insulating film, 13 is a sink film for impurities such as heavy metals, 14 is a second insulating film, and 15 is a semiconductor support substrate. Patent Applicant: Fujitsu Ltd. Representative Patent Attorney: Akira Aitani Representative Patent Attorney: Hiroshi Watanabe - 13 Cutaway side view of essential parts of an SOI wafer to explain the sink film principle 1st
Figure 3 Cutaway side view of the main part of the SOI wafer at the key point in the process Cutting side view of the main part of the SOI wafer at the key point in the process Figure 3 14 Main part of the SOI wafer at the key point in the second insulating film process Cutaway side view A cutaway side view of the main part of an SOI wafer at a key point in the process FIG. 5 A cutaway side view of the main part of an SOI wafer at a key point in the process FIG.
Claims (1)
のシンク膜と第一の絶縁膜と半導体活性層とが順に積層
されてなること を特徴とするＳＯＩウェハ。 （２）第一の絶縁膜は半導体装置を製造するプロセス中
に半導体活性層に侵入する重金属などの不純物が通り抜
けてゲッタリングのシンク膜に達し得る厚さであること を特徴とする請求項１記載のＳＯＩウェハ。（３）半導
体基板に第一の絶縁膜とゲッタリングのシンク膜と第二
の絶縁膜とを順に形成し、 次いで、前記半導体基板に於ける第二の絶縁膜に半導体
支持基板を対向させて貼り合わせ、次いで、前記半導体
基板を薄膜化し半導体活性層とする工程 が含まれてなることを特徴とするＳＯＩウェハの製造方
法。 （４）表面に第一の絶縁膜とゲッタリングのシンク膜と
を順に形成した半導体基板並びに表面に第二の絶縁膜を
形成した半導体支持基板とを用意し、 次いで、前記半導体基板に於けるゲッタリングのシンク
膜と前記半導体支持基板に於ける第二の絶縁膜とを対向
させて貼り合わせ、 次いで、前記半導体基板を薄膜化し半導体活性層とする
工程 が含まれてなることを特徴とするＳＯＩウェハの製造方
法。 （５）表面に第一の絶縁膜を形成した半導体基板並びに
表面に第二の絶縁膜とゲッタリングのシンク膜とを順に
形成した半導体支持基板とを用意し、 次いで、前記半導体基板に於ける第一の絶縁膜と前記半
導体支持基板に於けるゲッタリングのシンク膜とを対向
させて貼り合わせ、 次いで、前記半導体基板を薄膜化し半導体活性層とする
工程 が含まれてなることを特徴とするＳＯＩウェハの製造方
法。 （６）半導体基板に半導体装置を製造するプロセス中に
半導体活性層に侵入する重金属などの不純物が通り抜け
てゲッタリングのシンク膜に達し得る厚さの第一の絶縁
膜を形成すること が含まれてなることを特徴とする請求項３或いは４或い
は５記載のＳＯＩウェハの製造方法。（７）半導体基板
がＳｉであってＳｉＯ＿２からなる第一の絶縁膜が熱酸
化法を適用して生成され、また、第二の絶縁膜が化学気
相堆積法を適用して形成されること を特徴とする請求項３或いは４或いは５或いは６記載の
ＳＯＩウェハの製造方法。[Scope of Claims] (1) An SOI wafer characterized in that a second insulating film, a gettering sink film, a first insulating film, and a semiconductor active layer are laminated in this order on a semiconductor support substrate. (2) The first insulating film has a thickness that allows impurities such as heavy metals that invade the semiconductor active layer during the process of manufacturing the semiconductor device to pass through and reach the gettering sink film. SOI wafer as described. (3) Forming a first insulating film, a gettering sink film, and a second insulating film on a semiconductor substrate in order, and then placing a semiconductor supporting substrate opposite to the second insulating film on the semiconductor substrate. A method for manufacturing an SOI wafer, comprising the steps of bonding, and then thinning the semiconductor substrate to form a semiconductor active layer. (4) Prepare a semiconductor substrate on which a first insulating film and a gettering sink film are sequentially formed, and a semiconductor support substrate on which a second insulating film is formed; The method is characterized by including a step of bonding a gettering sink film and a second insulating film of the semiconductor support substrate so as to face each other, and then thinning the semiconductor substrate to form a semiconductor active layer. Method for manufacturing SOI wafers. (5) Prepare a semiconductor substrate on which a first insulating film is formed and a semiconductor support substrate on which a second insulating film and a gettering sink film are sequentially formed; The method is characterized by including a step of bonding a first insulating film and a gettering sink film on the semiconductor support substrate so as to face each other, and then thinning the semiconductor substrate to form a semiconductor active layer. Method for manufacturing SOI wafers. (6) Forming a first insulating film on a semiconductor substrate with a thickness that allows impurities such as heavy metals that invade the semiconductor active layer during the process of manufacturing a semiconductor device to pass through and reach the gettering sink film. 6. The method for manufacturing an SOI wafer according to claim 3, characterized in that: (7) The semiconductor substrate is Si, the first insulating film made of SiO_2 is produced by applying a thermal oxidation method, and the second insulating film is formed by applying a chemical vapor deposition method. 7. The method for manufacturing an SOI wafer according to claim 3, 4, 5, or 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32597290A JPH04199632A (en) | 1990-11-29 | 1990-11-29 | Soi wafer and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32597290A JPH04199632A (en) | 1990-11-29 | 1990-11-29 | Soi wafer and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04199632A true JPH04199632A (en) | 1992-07-20 |
Family
ID=18182653
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32597290A Pending JPH04199632A (en) | 1990-11-29 | 1990-11-29 | Soi wafer and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04199632A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0710980A2 (en) * | 1994-11-07 | 1996-05-08 | Nec Corporation | Soi substrate |
| JPH0963911A (en) * | 1995-08-29 | 1997-03-07 | Mitsubishi Materials Shilicon Corp | Laminated wafer and manufacture thereof |
| US5773152A (en) * | 1994-10-13 | 1998-06-30 | Nec Corporation | SOI substrate having a high heavy metal gettering effect for semiconductor device |
| JP2004320050A (en) * | 2004-06-29 | 2004-11-11 | Sumitomo Mitsubishi Silicon Corp | Soi substrate and method for manufacturing same |
| WO2011148434A1 (en) * | 2010-05-24 | 2011-12-01 | パナソニック株式会社 | Semiconductor substrate, and process for production of solid-state imaging device using same |
-
1990
- 1990-11-29 JP JP32597290A patent/JPH04199632A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5773152A (en) * | 1994-10-13 | 1998-06-30 | Nec Corporation | SOI substrate having a high heavy metal gettering effect for semiconductor device |
| EP0710980A2 (en) * | 1994-11-07 | 1996-05-08 | Nec Corporation | Soi substrate |
| EP0710980A3 (en) * | 1994-11-07 | 1998-09-30 | Nec Corporation | Soi substrate |
| JPH0963911A (en) * | 1995-08-29 | 1997-03-07 | Mitsubishi Materials Shilicon Corp | Laminated wafer and manufacture thereof |
| JP2004320050A (en) * | 2004-06-29 | 2004-11-11 | Sumitomo Mitsubishi Silicon Corp | Soi substrate and method for manufacturing same |
| WO2011148434A1 (en) * | 2010-05-24 | 2011-12-01 | パナソニック株式会社 | Semiconductor substrate, and process for production of solid-state imaging device using same |
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