JP2004320050A - Soi substrate and method for manufacturing same - Google Patents

Soi substrate and method for manufacturing same Download PDF

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JP2004320050A
JP2004320050A JP2004190578A JP2004190578A JP2004320050A JP 2004320050 A JP2004320050 A JP 2004320050A JP 2004190578 A JP2004190578 A JP 2004190578A JP 2004190578 A JP2004190578 A JP 2004190578A JP 2004320050 A JP2004320050 A JP 2004320050A
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layer
silicon
wafer
insulating layer
soi
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Shunichiro Ishigami
俊一郎 石神
Etsuro Morita
悦郎 森田
Hisashi Furuya
久 降屋
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Sumco Corp
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Sumitomo Mitsubishi Silicon Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide an SOI substrate in which a getter property is provided so that a SOI layer is not contaminated by heavy metals, adverse effects on device characteristics caused by a substrate structure are relaxed and warp of the substrate is prevented, and adhesiveness between two wafers and continuity of an interface between an insulating layer and the interface is excellent, and provide a method for manufacturing the substrate. <P>SOLUTION: An insulating layer 13 is formed on a surface of a wafer 12 that is an active layer, a silicon nitride layer 14 and a poly-crystalline silicon layer 15 are formed in this order on the insulating layer 13 by CVD respectively, and each of surfaces of the wafer 12 on which the poly-crystalline silicon layer is formed and a wafer 12 that is a support substrate is washed using a SCI washing liquid mixed with NH<SB>4</SB>OH solution and H<SB>2</SB>O<SB>2</SB>solution, thereby activating each surface. The wafer 12, on which the poly-crystalline silicon layer, silicon nitride layer, and insulating layer are formed, is directly bonded with an active surface of the wafer 11 using an active surface of the poly-crystalline silicon layer as a bonding surface, and then laminated through heat treatment, and then the wafer 12 is ground and polished into a fixed thickness to form a SOI layer 12a for device formation. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は絶縁層上にシリコン層（以下、ＳＯＩ層という）を形成したＳＯＩ（Silicon-On-Insulator）基板及び２枚のシリコンウェーハを絶縁層、窒化珪素層及び多結晶シリコン層を介して貼り合わせるＳＯＩ基板の製造方法に関するものである。   According to the present invention, an SOI (Silicon-On-Insulator) substrate in which a silicon layer (hereinafter, referred to as an SOI layer) is formed on an insulating layer and two silicon wafers are bonded via an insulating layer, a silicon nitride layer, and a polycrystalline silicon layer. The present invention relates to a method for manufacturing an SOI substrate to be combined.

近年、高集積ＣＭＯＳ（Complementary Metal Oxide Semiconductor）、ＩＣ、高耐圧素子などがＳＯＩ基板を利用して製作されるようになってきている。絶縁層の上にデバイス作製領域として使用される単結晶シリコン層を形成したＳＯＩ基板は、高集積ＣＭＯＳの場合にはラッチアップ（寄生回路による異常発振現象）の防止に、また高耐圧素子の場合にはベース基板との絶縁分離にそれぞれ有効である。このＳＯＩ基板の製造方法には、シリコンウェーハ同士を二酸化シリコン層（以下、シリコン酸化層という）、即ち絶縁層を介して貼り合わせる方法、絶縁性基板又は絶縁性薄膜を表面に有する基板の上にまず多結晶シリコン薄膜をＣＶＤ（Chemical Vapor Deposition）法により堆積させ、次いでレーザーアニールによって単結晶化するＺＭＲ法、シリコン基板内部に高濃度の酸素イオンを注入した後、高温でアニール処理してこのシリコン基板表面から所定の深さの領域に埋込みシリコン酸化層（絶縁層）を形成し、その表面側のシリコン層を活性領域とするＳＩＭＯＸ法などがある。これらの方法の中でも、貼り合わせ法により作製されたＳＯＩ基板は、ＳＯＩ層の結晶性が極めて良好であることから、有望視されて来ている。   In recent years, highly integrated CMOS (Complementary Metal Oxide Semiconductor), ICs, high withstand voltage elements, and the like have been manufactured using SOI substrates. An SOI substrate in which a single crystal silicon layer used as a device fabrication region is formed on an insulating layer prevents latch-up (abnormal oscillation due to a parasitic circuit) in the case of a highly integrated CMOS, and in the case of a high breakdown voltage element. Is effective for insulating and separating from the base substrate. This SOI substrate manufacturing method includes a method in which silicon wafers are bonded to each other via a silicon dioxide layer (hereinafter, referred to as a silicon oxide layer), that is, an insulating layer, an insulating substrate or a substrate having an insulating thin film on its surface. First, a polycrystalline silicon thin film is deposited by a CVD (Chemical Vapor Deposition) method, then a single crystal is formed by laser annealing, and a high concentration oxygen ion is implanted into a silicon substrate. There is a SIMOX method in which a buried silicon oxide layer (insulating layer) is formed in a region at a predetermined depth from the substrate surface, and the silicon layer on the surface side is used as an active region. Among these methods, an SOI substrate manufactured by a bonding method is promising because the SOI layer has extremely good crystallinity.

このシリコンウェーハの貼り合わせ法は、具体的にはそれぞれ約６００μｍの２枚のシリコンウェーハをシリコン酸化層からなる絶縁層を介して接合し、酸素雰囲気中、１１００℃で２時間貼り合わせ熱処理した後、２枚のシリコンウェーハの一方のシリコンウェーハの表面を砥石で研削し、更に研磨布で研磨してこのシリコンウェーハの厚さを約１〜１０μｍの範囲にし、この研磨した側の厚さ約１〜１０μｍのシリコン層をデバイス形成用のＳＯＩ層としている。
しかし、このＳＯＩ基板のＳＯＩ層がデバイスプロセス中に重金属不純物により汚染された場合には、埋込みシリコン酸化層（絶縁層）がゲッタリング源となって重金属不純物を捕捉した後で、熱処理の進行に伴って結晶化した絶縁層が一旦捕捉した重金属不純物をＳＯＩ層中に放出し再分布を生じ易く、これに起因してＳＯＩ層の汚染による品質劣化が生じることがあった。 Specifically, the bonding method of the silicon wafers is such that two silicon wafers each having a thickness of about 600 μm are bonded via an insulating layer made of a silicon oxide layer, and are bonded and heat-treated at 1100 ° C. for 2 hours in an oxygen atmosphere. The surface of one of the two silicon wafers is ground with a grindstone and further polished with a polishing cloth so that the thickness of the silicon wafer is in the range of about 1 to 10 μm, and the thickness of the polished side is about 1 μm. A silicon layer of 10 to 10 μm is used as an SOI layer for device formation.
However, when the SOI layer of this SOI substrate is contaminated with heavy metal impurities during the device process, the embedded silicon oxide layer (insulating layer) serves as a gettering source to capture the heavy metal impurities, and then the heat treatment proceeds. Accordingly, the heavy metal impurities once trapped by the crystallized insulating layer are released into the SOI layer and are likely to be redistributed. As a result, quality deterioration due to contamination of the SOI layer may occur.

従来、この点を解決したＳＯＩ基板として、デバイス形成用のＳＯＩ層内にゲッタリング源を有するもの（例えば、特許文献１）や、支持基板内にゲッタリング源を有するもの（例えば、特許文献２）が提案されている。前者のＳＯＩ基板はデバイス形成用のＳＯＩ層と絶縁層との間に多結晶シリコン層が設けられる。また後者のＳＯＩ基板は支持基板となるシリコンウェーハの両面に多結晶シリコン、非晶質シリコン等からなるゲッタリング層を形成し、両面のゲッタリング層上に絶縁層を形成し、一方の絶縁層に別の活性層となるシリコンウェーハを接合した後、このシリコンウェーハを研削研磨してデバイス形成用のＳＯＩ層を形成したものである。
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特開平６−２７５５２５号公報 特開平７−２９９１１号公報 Conventionally, as an SOI substrate that solves this problem, one having a gettering source in an SOI layer for device formation (for example, Patent Document 1) and one having a gettering source in a supporting substrate (for example, Patent Document 2) ) Has been proposed. In the former SOI substrate, a polycrystalline silicon layer is provided between an SOI layer for device formation and an insulating layer. In the latter SOI substrate, a gettering layer made of polycrystalline silicon, amorphous silicon, or the like is formed on both sides of a silicon wafer serving as a supporting substrate, an insulating layer is formed on the gettering layers on both sides, and one insulating layer is formed. Then, after bonding a silicon wafer to be another active layer, the silicon wafer is ground and polished to form an SOI layer for device formation.
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JP-A-6-275525 JP-A-7-29911

しかし、特許文献１に示されるＳＯＩ基板には、単結晶シリコンよりも熱膨張係数がともに小さい絶縁層（ＳｉＯ2層）及び多結晶シリコン層が支持基板となるシリコンウェーハ上に形成されるため、支持基板がデバイス形成用のＳＯＩ層側で凸状に反りを生じ、次工程のパターン形成のための露光工程において所望の素子パターンを形成しにくい問題点があった。
また、特許文献２に示されるＳＯＩ基板には、第一にその表面に吸着したＯＨ基の少ない絶縁層を接合面として支持基板となるシリコンウェーハを活性層となるシリコンウェーハに接合するため、両ウェーハの接着性が悪く、また第二に絶縁層とＳＯＩ層との界面の連続性が熱酸化によるＳｉと絶縁層との界面に比較して劣る等の問題点があった。 However, in the SOI substrate disclosed in Patent Document 1, an insulating layer (SiO 2 layer) and a polycrystalline silicon layer each having a smaller coefficient of thermal expansion than single crystal silicon are formed on a silicon wafer serving as a support substrate. The supporting substrate warps in a convex shape on the SOI layer side for device formation, and there is a problem that it is difficult to form a desired element pattern in an exposure step for forming a pattern in the next step.
In addition, the SOI substrate disclosed in Patent Document 2 has a structure in which a silicon wafer serving as a support substrate is bonded to a silicon wafer serving as an active layer by using an insulating layer having a small amount of OH groups adsorbed on its surface as a bonding surface. Second, there are problems such as poor adhesion of the wafer and secondly, the continuity of the interface between the insulating layer and the SOI layer is inferior to the interface between Si and the insulating layer due to thermal oxidation.

本発明の目的は、ゲッタリング能力を有しＳＯＩ層を重金属で汚染させないＳＯＩ基板及びその製造方法を提供することにある。
本発明の別の目的は、基板の構造から生じるデバイス特性への悪影響を緩和し、
かつ基板の反りを防止するＳＯＩ基板及びその製造方法を提供することにある。
本発明の更に別の目的は、２枚のシリコンウェーハの接着性及び絶縁層とＳＯＩ層との界面の連続性が良好なＳＯＩ基板及びその製造方法を提供することにある。 An object of the present invention is to provide an SOI substrate having a gettering ability and not contaminating an SOI layer with heavy metals, and a method for manufacturing the same.
Another object of the present invention is to mitigate adverse effects on device characteristics resulting from the structure of the substrate,
Another object of the present invention is to provide an SOI substrate that prevents warpage of the substrate and a method of manufacturing the same.
Still another object of the present invention is to provide an SOI substrate having good adhesion between two silicon wafers and good continuity at the interface between the insulating layer and the SOI layer, and a method of manufacturing the same.

図１（ａ）〜図１（ｆ）に示すように、本発明のＳＯＩ基板１０の製造方法は、活性層となる第２シリコンウェーハ１２の表面に絶縁層１３を形成する工程と、この絶縁層１３上に窒化珪素層１４をＣＶＤ法により形成する工程と、この窒化珪素層１４上に多結晶シリコン層１５をＣＶＤ法により形成する工程と、この多結晶シリコン層１５を形成した第２シリコンウェーハ１２と支持基板となる第１シリコンウェーハ１１の各表面をＮＨ4ＯＨの水溶液とＨ2Ｏ2水溶液とを混合して調製したＳＣ１の洗浄液で洗浄して各表面を活性化する工程と、この多結晶シリコン層１５と窒化珪素層１４と絶縁層１３とが形成された第２シリコンウェーハ１２を多結晶シリコン層１５の活性化した表面を接合面として支持基板となる第１シリコンウェーハ１１の活性化した表面と直接接合する工程と、接合した第１及び第２シリコンウェーハ１１，１２を熱処理して貼り合わせる工程と、第２シリコンウェーハ１２を所定の厚さに研削研磨してデバイス形成用のＳＯＩ層１２ａとする工程とを含む方法である。
図１（ｆ）に示すように、本発明のＳＯＩ基板１０は上記方法により製造されたものであって、支持基板となるシリコンウェーハ１１上に多結晶シリコン層１５と窒化珪素層１４と絶縁層１３とがこの順に形成され、この絶縁層１３上にデバイス形成用のＳＯＩ層１２ａが形成され、ＳＣ１洗浄液による洗浄でシリコンウェーハ１１の活性化した表面にこのウェーハと同程度の数のＯＨ基を有する多結晶シリコン層１５の活性化した表面が直接接合されたものである。 As shown in FIGS. 1A to 1F, in the method for manufacturing an SOI substrate 10 of the present invention, a step of forming an insulating layer 13 on a surface of a second silicon wafer 12 to be an active layer, A step of forming a silicon nitride layer 14 on the layer 13 by a CVD method, a step of forming a polycrystalline silicon layer 15 on the silicon nitride layer 14 by a CVD method, and a step of forming a second silicon layer on which the polycrystalline silicon layer 15 is formed. Activating each surface by cleaning each surface of the wafer 12 and the first silicon wafer 11 serving as a support substrate with a SC1 cleaning solution prepared by mixing an aqueous solution of NH 4 OH and an aqueous solution of H 2 O 2 ; The second silicon wafer 12 on which the polycrystalline silicon layer 15, the silicon nitride layer 14, and the insulating layer 13 are formed is converted into a first silicon wafer to be a support substrate by using the activated surface of the polycrystalline silicon layer 15 as a bonding surface. A step of directly bonding to the activated surface of c, a step of heat-treating and bonding the bonded first and second silicon wafers 11 and 12, and a step of grinding and polishing the second silicon wafer 12 to a predetermined thickness. And forming a SOI layer 12a for device formation.
As shown in FIG. 1 (f), the SOI substrate 10 of the present invention is manufactured by the above-described method, and a polycrystalline silicon layer 15, a silicon nitride layer 14, and an insulating layer are formed on a silicon wafer 11 serving as a supporting substrate. 13 are formed in this order, an SOI layer 12a for device formation is formed on the insulating layer 13, and the same number of OH groups as the number of OH groups on the activated surface of the silicon wafer 11 by the cleaning with the SC1 cleaning liquid. The activated surface of the polycrystalline silicon layer 15 is directly bonded.

本発明によれば、絶縁層を有するシリコンウェーハを窒化珪素層及び多結晶シリコン層を介して支持基板となるシリコンウェーハと直接接合することにより、多結晶シリコン層がゲッタリング源として作用し、デバイスプロセス中に生じた重金属不純物は多結晶シリコン層に捕捉される。このとき多結晶シリコン層が絶縁層を挟んでＳＯＩ層の反対側にあるため、重金属不純物がＳＯＩ層に再分布せず、高品質のデバイス形成用のＳＯＩ層が絶縁層上に得られる。
また本発明の方法により製造されたＳＯＩ基板は、窒化珪素層の存在により反りが防止される。更に特開平７−２９９１１号公報に示されるＳＯＩ基板において、その表面に吸着したＯＨ基の少ない絶縁層を接合面として支持基板となるシリコンウェーハを活性層となるシリコンウェーハに接合するため、両ウェーハの接着性が悪かったものが、本発明の方法により製造されたＳＯＩ基板は、支持基板のシリコンウェーハと同程度の数のＯＨ基を有する多結晶シリコン層を介して活性層となるシリコンウェーハを支持基板となるシリコンウェーハと接合するため、両ウェーハの接着性が良好となり、絶縁層とＳＯＩ層との連続性に優れる。 According to the present invention, by directly bonding a silicon wafer having an insulating layer to a silicon wafer serving as a support substrate via a silicon nitride layer and a polycrystalline silicon layer, the polycrystalline silicon layer acts as a gettering source, Heavy metal impurities generated during the process are captured in the polycrystalline silicon layer. At this time, since the polycrystalline silicon layer is on the opposite side of the SOI layer with the insulating layer interposed therebetween, heavy metal impurities are not redistributed to the SOI layer, and a high-quality SOI layer for device formation is obtained on the insulating layer.
The warpage of the SOI substrate manufactured by the method of the present invention is prevented by the presence of the silicon nitride layer. Further, in the SOI substrate disclosed in Japanese Patent Application Laid-Open No. 7-29911, a silicon wafer serving as a support substrate is bonded to a silicon wafer serving as an active layer by using an insulating layer having a small amount of OH groups adsorbed on the surface thereof as a bonding surface. However, the SOI substrate manufactured by the method of the present invention has a silicon wafer that becomes an active layer via a polycrystalline silicon layer having the same number of OH groups as the silicon wafer of the supporting substrate. Since it is bonded to a silicon wafer serving as a support substrate, the adhesion between the two wafers is good, and the continuity between the insulating layer and the SOI layer is excellent.

本発明の第１及び第２シリコンウェーハはＣＺ法、ＦＺ法等の方法で、ともに同一の方法により得られたシリコン単結晶棒から作製される。図１（ａ）に示すように、絶縁層１３は第２シリコンウェーハ１２の片面に形成される。絶縁層１３の厚さは約０．５〜約１．０μｍの範囲、好ましくは約０．５〜約０．６μｍの範囲にある。この絶縁層１３はシリコン酸化層（ＳｉＯ2層）であって、シリコンウェーハ１２を熱酸化することにより、或いはＣＶＤ法によりウェーハ１２の片面に形成される。
次に、図１（ｂ）に示すように絶縁層１３上には窒化珪素（Ｓｉ3Ｎ4）層１４がＣＶＤ法により形成される。この窒化珪素層１４の厚さは約０．０１〜約０．５μｍの範囲、好ましくは約０．０５〜約０．１μｍの範囲にある。また図１（ｃ）に示すように窒化珪素層１４上には多結晶シリコン層１５がＣＶＤ法により形成される。この多結晶シリコン層１５の厚さは約０．５〜約２．０μｍの範囲、好ましくは約０．５〜約１．０μｍの範囲にある。 The first and second silicon wafers of the present invention are manufactured from a silicon single crystal rod obtained by the same method using a CZ method, an FZ method or the like. As shown in FIG. 1A, the insulating layer 13 is formed on one surface of the second silicon wafer 12. The thickness of the insulating layer 13 ranges from about 0.5 to about 1.0 μm, preferably from about 0.5 to about 0.6 μm. The insulating layer 13 is a silicon oxide layer (SiO 2 layer) and is formed on one surface of the wafer 12 by thermally oxidizing the silicon wafer 12 or by a CVD method.
Next, as shown in FIG. 1B, a silicon nitride (Si 3 N 4 ) layer 14 is formed on the insulating layer 13 by a CVD method. The thickness of this silicon nitride layer 14 is in the range of about 0.01 to about 0.5 μm, preferably in the range of about 0.05 to about 0.1 μm. As shown in FIG. 1C, a polycrystalline silicon layer 15 is formed on the silicon nitride layer 14 by a CVD method. The thickness of this polycrystalline silicon layer 15 is in the range of about 0.5 to about 2.0 μm, preferably in the range of about 0.5 to about 1.0 μm.

次いで図１（ｄ）及び（ｅ）に示すように、この第２シリコンウェーハ１２が多結晶シリコン層１５を接合面として、支持基板となる第１シリコンウェーハ１１と直接接合される。接合しようとする表面を活性化するためにＮＨ4ＯＨの水溶液とＨ2Ｏ2水溶液とを混合して調製したＳＣ１の洗浄液でシリコンウェーハ１１，１２を洗浄しておく。図１（ｅ）に示すように接合した後の第１及び第２シリコンウェーハ１１，１２を乾燥酸素（ｄｒｙＯ2）雰囲気又は窒素（Ｎ2）雰囲気中で１１００℃の温度下、１〜３時間、好ましくは２時間程度行う。
図１（ｆ）に示すように、一体化した２枚のシリコンウェーハ１１，１２が放冷され室温になった後に、支持基板となる第２シリコンウェーハ１２を砥石で研削し、その後研磨布で研磨して、約１〜１０μｍの厚さの薄膜に加工する。これにより厚さ約１〜１０μｍのデバイス形成用のＳＯＩ層１２ａが絶縁層１３上に得られる。 Next, as shown in FIGS. 1D and 1E, the second silicon wafer 12 is directly bonded to the first silicon wafer 11 serving as a support substrate using the polycrystalline silicon layer 15 as a bonding surface. The silicon wafers 11 and 12 are cleaned with an SC1 cleaning solution prepared by mixing an aqueous solution of NH 4 OH and an aqueous solution of H 2 O 2 in order to activate the surface to be bonded. After bonding as shown in FIG. 1E, the first and second silicon wafers 11 and 12 are placed in a dry oxygen (dryO 2 ) atmosphere or a nitrogen (N 2 ) atmosphere at a temperature of 1100 ° C. for 1 to 3 hours. , Preferably for about 2 hours.
As shown in FIG. 1 (f), after the two integrated silicon wafers 11 and 12 are allowed to cool to room temperature, the second silicon wafer 12 serving as a support substrate is ground with a grindstone, and then is polished with a polishing cloth. It is polished and processed into a thin film having a thickness of about 1 to 10 μm. As a result, an SOI layer 12 a for device formation having a thickness of about 1 to 10 μm is obtained on the insulating layer 13.

２枚のシリコンウェーハの接合界面に絶縁層１３と窒化珪素層１４と多結晶シリコン層１５が積層されるため、ＳＯＩ基板１０のＳＯＩ層１２ａがデバイスプロセス中に重金属不純物により汚染された場合には、多結晶シリコン層１５がゲッタリング源として作用する。即ち、ＳＯＩ層１２ａ中の重金属不純物が絶縁層１３及び窒化珪素層１４を通過して多結晶シリコン層１５に捕捉される。
重金属不純物を捕捉した多結晶シリコン層１５は絶縁層１３を挟んでＳＯＩ層１２ａの反対側にあるため、この重金属不純物はＳＯＩ層１２ａ中に再分布しない。 Since the insulating layer 13, the silicon nitride layer 14, and the polycrystalline silicon layer 15 are stacked on the bonding interface between the two silicon wafers, if the SOI layer 12 a of the SOI substrate 10 is contaminated by heavy metal impurities during the device process, The polycrystalline silicon layer 15 functions as a gettering source. That is, heavy metal impurities in the SOI layer 12a pass through the insulating layer 13 and the silicon nitride layer 14 and are captured by the polycrystalline silicon layer 15.
Since the polycrystalline silicon layer 15 capturing the heavy metal impurities is on the opposite side of the SOI layer 12a with the insulating layer 13 interposed therebetween, the heavy metal impurities do not redistribute in the SOI layer 12a.

また図２（ａ）に示すように、単結晶シリコンからなるウェーハ１２上にこれよりも熱膨張係数が小さい絶縁層（ＳｉＯ2層）１３を積層して室温まで冷却すると、基板結晶格子中の絶縁層側で引張応力が働いてウェーハ１２が凸状に反る傾向がある。図２（ｂ）に示すように、ウェーハ１２上に窒化珪素（Ｓｉ3Ｎ4）層１４を積層して室温まで冷却すると、基板結晶格子中の窒化珪素層側で圧縮応力が働いてウェーハ１２が凹状に反る傾向がある。また図２（ｃ）に示すように、ウェーハ１２上にこれよりも熱膨張係数が小さい多結晶シリコン層１５を積層して室温まで冷却すると、多結晶シリコン層側で引張応力が働いてウェーハ１２が凸状に反る傾向がある。この結果、図２（ｄ）及び図１（ｃ）に示すように、ウェーハ１２上で絶縁層１３と窒化珪素（Ｓｉ3Ｎ4）層１４と多結晶シリコン層１５とをこの順に積層した後熱処理すると、ウェーハ１２上での引張応力と圧縮応力が相殺されてウェーハ１２は反らずに平坦になる。 Further, as shown in FIG. 2A, an insulating layer (SiO 2 layer) 13 having a smaller coefficient of thermal expansion is laminated on a wafer 12 made of single crystal silicon and cooled to room temperature. The tensile stress acts on the insulating layer side, and the wafer 12 tends to warp in a convex shape. As shown in FIG. 2 (b), when a silicon nitride (Si 3 N 4 ) layer 14 is laminated on the wafer 12 and cooled to room temperature, a compressive stress acts on the silicon nitride layer side in the substrate crystal lattice, and the wafer 12 Tend to be concavely warped. Further, as shown in FIG. 2C, when a polycrystalline silicon layer 15 having a smaller thermal expansion coefficient is laminated on the wafer 12 and cooled to room temperature, a tensile stress acts on the polycrystalline silicon layer side, so that the wafer 12 Tend to warp convexly. As a result, as shown in FIG. 2D and FIG. 1C, after the insulating layer 13, the silicon nitride (Si 3 N 4 ) layer 14 and the polycrystalline silicon layer 15 are laminated on the wafer 12 in this order. When the heat treatment is performed, the tensile stress and the compressive stress on the wafer 12 are offset, and the wafer 12 becomes flat without warping.

更に本発明のＳＯＩ基板１０は、ＯＨ基の数が単結晶シリコンウェーハ上の場合と同程度である多結晶シリコン層１５を介して活性層となるシリコンウェーハ１２を支持基板となるシリコンウェーハ１１と接合するため、絶縁層との貼り合わせに比較して両ウェーハの接着性が良好となる。また絶縁層１３とＳＯＩ層１２ａとの界面は接合界面でないため、これらの層の連続性に優れる。   Further, the SOI substrate 10 of the present invention is configured such that a silicon wafer 12 serving as an active layer is connected to a silicon wafer 11 serving as a support substrate through a polycrystalline silicon layer 15 having the same number of OH groups as on a single crystal silicon wafer. Since the bonding is performed, the adhesion between the two wafers is improved as compared with the bonding with the insulating layer. Further, since the interface between the insulating layer 13 and the SOI layer 12a is not a bonding interface, the continuity of these layers is excellent.

次に、本発明の実施例を図面に基づいて詳しく説明する。
(a) サンプルの準備と絶縁膜の形成
ＣＺ法で引上げられたシリコン単結晶棒から切断され研削研磨されたばかりの次の特性の２枚のシリコンウェーハを用意した。
直径： ５インチ
面方位： ＜１００＞
伝導型： Ｐ型（ドーパントとしてボロンを添加）
抵抗率： 約１０Ωｃｍ
厚さ： 約６２０μｍ
初期格子間酸素濃度：約１．５×１０18／ｃｍ3（旧ＡＳＴＭ）
図１（ａ）に示すように、その内の１枚のシリコンウェーハ１２の片面にウェーハ１２を湿潤酸素（ｗｅｔＯ2）雰囲気中、１０００℃で３時間熱処理して厚さ０．５μｍのシリコン酸化層からなる絶縁層１３を形成した。
(b) 窒化珪素層の形成
図１（ｂ）に示すように絶縁層１３上に次の条件で窒化珪素（Ｓｉ3Ｎ4）層１４をＣＶＤ法により形成した。
雰囲気： ０．４Ｔｏｒｒの減圧雰囲気
使用ガス（流量）： ＳｉＨ2Ｃｌ2（０．０７５リットル／分）
ＮＨ3 （１．０リットル／分）
温度： ７７５℃
堆積速度： ３０オングストローム／分
窒化珪素層１４は絶縁層１３上に約０．１μｍの厚さで形成された。
(c) 多結晶シリコン層の形成
図１（ｃ）に示すように窒化珪素層１４上に次の条件で多結晶シリコン層１５をＣＶＤ法により形成した。
雰囲気： ０．１Ｔｏｒｒの減圧雰囲気
使用ガス（流量）： ＳｉＨ4（０．１リットル／分）
温度： ６２０℃
堆積速度： ６５オングストローム／分
多結晶シリコン層１５は窒化珪素層１４上に約０．５μｍの厚さで形成された。
(d) 接合
図１（ｃ）及び（ｄ）に示すように、絶縁層１３と窒化珪素層１４と多結晶シリコン層１５を積層したシリコンウェーハ１２ともう１枚のシリコンウェーハ１１とをそれぞれ比重０．９のＮＨ4ＯＨの水溶液と比重１．１のＨ2Ｏ2水溶液とＨ2ＯとをＮＨ4ＯＨ：Ｈ2Ｏ2：Ｈ2Ｏ＝１：２：７の容量比で混合して調製したＳＣ１（Standard Cleaning 1）の洗浄液で洗浄した後、両ウェーハ１１，１２を多結晶シリコン層１５を接合面として重ね合せ接合した。
(e) 貼り合わせ熱処理と研削研磨
図１（ｅ）に示すように、室温から８００℃に設定された熱処理炉中に１０〜１５ｃｍ／分の速度で挿入し、窒素雰囲気中で８００℃から１０℃／分の速度で昇温し、１１００℃に達したところで２時間維持し、次いで４℃／分の速度で降温し、８００℃まで冷却した後、１０〜１５ｃｍ／分の速度で炉から室温中に取出した。更に図１（ｆ）に示すように、シリコンウェーハ１２の表面を砥石で研削し、次いで柔らかい研磨布で研磨し、絶縁層１３上に厚さ１〜１０μｍのＳＯＩ層１２ａを形成した。 Next, embodiments of the present invention will be described in detail with reference to the drawings.
(a) Preparation of Sample and Formation of Insulating Film Two silicon wafers having the following characteristics, which were cut from a silicon single crystal rod pulled up by the CZ method and were just ground and polished, were prepared.
Diameter: 5 inches
Plane orientation: <100>
Conduction type: P type (boron is added as a dopant)
Resistivity: about 10Ωcm
Thickness: about 620 μm
Initial interstitial oxygen concentration: about 1.5 × 10 18 / cm 3 (former ASTM)
As shown in FIG. 1A, one of the silicon wafers 12 is heat-treated at 1000 ° C. for 3 hours in a wet oxygen (wetO 2 ) atmosphere on one side of the silicon wafer 12 to form a silicon oxide having a thickness of 0.5 μm. An insulating layer 13 composed of a layer was formed.
(b) Formation of Silicon Nitride Layer As shown in FIG. 1B, a silicon nitride (Si 3 N 4 ) layer 14 was formed on the insulating layer 13 under the following conditions by a CVD method.
Atmosphere: 0.4 Torr reduced pressure atmosphere
Working gas (flow rate): SiH 2 Cl 2 (0.075 l / min)
NH 3 (1.0 liter / min)
Temperature: 775 ° C
Deposition rate: 30 Å / min The silicon nitride layer 14 was formed on the insulating layer 13 to a thickness of about 0.1 μm.
(c) Formation of Polycrystalline Silicon Layer As shown in FIG. 1C, a polycrystalline silicon layer 15 was formed on the silicon nitride layer 14 under the following conditions by a CVD method.
Atmosphere: 0.1 Torr reduced pressure atmosphere
Working gas (flow rate): SiH 4 (0.1 liter / min)
Temperature: 620 ° C
Deposition rate: 65 Å / min. Polycrystalline silicon layer 15 was formed on silicon nitride layer 14 to a thickness of about 0.5 μm.
(d) Bonding As shown in FIGS. 1C and 1D, the specific gravity of the silicon wafer 12 on which the insulating layer 13, the silicon nitride layer 14, and the polycrystalline silicon layer 15 are laminated and the other silicon wafer 11 are respectively determined. An aqueous solution of NH 4 OH of 0.9, an aqueous solution of H 2 O 2 having a specific gravity of 1.1 and H 2 O are mixed in a volume ratio of NH 4 OH: H 2 O 2 : H 2 O = 1: 2: 7. After washing with the cleaning solution of SC1 (Standard Cleaning 1) prepared as described above, both wafers 11 and 12 were overlapped and joined using the polycrystalline silicon layer 15 as a joining surface.
(e) Laminating heat treatment and grinding and polishing As shown in FIG. 1 (e), it is inserted into a heat treatment furnace set at room temperature to 800 ° C. at a speed of 10 to 15 cm / min, and is heated at 800 ° C. to 10 ° C. The temperature was increased at a rate of 1 ° C./min, and when the temperature reached 1100 ° C., the temperature was maintained for 2 hours. Then, the temperature was decreased at a rate of 4 ° C./min. Taken out inside. Further, as shown in FIG. 1 (f), the surface of the silicon wafer 12 was ground with a grindstone and then polished with a soft polishing cloth to form an SOI layer 12 a having a thickness of 1 to 10 μm on the insulating layer 13.

本発明のＳＯＩ基板の製造方法を示す部分断面図。FIG. 4 is a partial cross-sectional view illustrating a method for manufacturing an SOI substrate of the present invention. 活性層となるシリコンウェーハの片面に絶縁層、窒化珪素層又は多結晶シリコン層を積層したときのウェーハの反り状況を示す部分断面図。FIG. 3 is a partial cross-sectional view showing a warp state of a silicon wafer serving as an active layer when an insulating layer, a silicon nitride layer, or a polycrystalline silicon layer is stacked on one surface of the silicon wafer.

符号の説明Explanation of reference numerals

１０ ＳＯＩ基板
１１ 第１シリコンウェーハ
１２ 第２シリコンウェーハ
１２ａ ＳＯＩ層
１３ 絶縁層（シリコン酸化層）
１４ 窒化珪素層（Ｓｉ3Ｎ4層）
１５ 多結晶シリコン層 Reference Signs List 10 SOI substrate 11 First silicon wafer 12 Second silicon wafer 12a SOI layer 13 Insulating layer (silicon oxide layer)
14 Silicon nitride layer (Si 3 N 4 layer)
15 Polycrystalline silicon layer

Claims (2)

活性層となる第２シリコンウェーハ(12)の表面に絶縁層(13)を形成する工程と、
前記絶縁層(13)上に窒化珪素層(14)をＣＶＤ法により形成する工程と、
前記窒化珪素層(14)上に多結晶シリコン層(15)をＣＶＤ法により形成する工程と、
前記多結晶シリコン層(15)を形成した第２シリコンウェーハ(12)と支持基板となる第１シリコンウェーハ(11)の各表面をＮＨ4ＯＨの水溶液とＨ2Ｏ2水溶液とを混合して調製したＳＣ１の洗浄液で洗浄して前記各表面を活性化する工程と、
前記多結晶シリコン層(15)と窒化珪素層(14)と絶縁層(13)とが形成された第２シリコンウェーハ(12)を前記多結晶シリコン層(15)の活性化した表面を接合面として前記第１シリコンウェーハ(11)の活性化した表面と直接接合する工程と、
前記接合した第１及び第２シリコンウェーハ(11,12)を熱処理して貼り合わせる工程と、
前記第２シリコンウェーハ(12)を所定の厚さに研削研磨してデバイス形成用のＳＯＩ層(12a)とする工程と
を含むＳＯＩ基板の製造方法。 Forming an insulating layer (13) on the surface of the second silicon wafer (12) to be an active layer;
Forming a silicon nitride layer (14) on the insulating layer (13) by a CVD method;
Forming a polycrystalline silicon layer (15) on the silicon nitride layer (14) by a CVD method;
The surfaces of the second silicon wafer (12) on which the polycrystalline silicon layer (15) is formed and the first silicon wafer (11) serving as a support substrate are mixed by mixing an aqueous solution of NH 4 OH and an aqueous solution of H 2 O 2. Activating each surface by washing with the prepared washing solution of SC1;
The second silicon wafer (12) on which the polycrystalline silicon layer (15), the silicon nitride layer (14), and the insulating layer (13) are formed is bonded to the activated surface of the polycrystalline silicon layer (15) by a bonding surface. Directly bonding to the activated surface of the first silicon wafer (11),
A step of heat-treating and bonding the bonded first and second silicon wafers (11, 12);
Grinding and polishing the second silicon wafer (12) to a predetermined thickness to form an SOI layer (12a) for device formation. 請求項１記載の方法により製造されたＳＯＩ基板。
An SOI substrate manufactured by the method according to claim 1.
JP2004190578A 2004-06-29 2004-06-29 Soi substrate and method for manufacturing same Pending JP2004320050A (en)

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JP2021190660A (en) * 2020-06-04 2021-12-13 株式会社Sumco Support substrate for bonded wafers

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