JPH06275525A - Soi substrate and manufacture thereof - Google Patents
Soi substrate and manufacture thereofInfo
- Publication number
- JPH06275525A JPH06275525A JP8403693A JP8403693A JPH06275525A JP H06275525 A JPH06275525 A JP H06275525A JP 8403693 A JP8403693 A JP 8403693A JP 8403693 A JP8403693 A JP 8403693A JP H06275525 A JPH06275525 A JP H06275525A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- layer
- polycrystalline silicon
- soi substrate
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 40
- 238000000034 method Methods 0.000 claims abstract description 19
- 239000004065 semiconductor Substances 0.000 claims abstract description 7
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 35
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- 230000003647 oxidation Effects 0.000 claims description 9
- 238000007254 oxidation reaction Methods 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 5
- 238000005229 chemical vapour deposition Methods 0.000 claims 1
- 238000005247 gettering Methods 0.000 abstract description 7
- 230000001590 oxidative effect Effects 0.000 abstract description 5
- 239000012298 atmosphere Substances 0.000 abstract description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 8
- 229910052681 coesite Inorganic materials 0.000 abstract 4
- 229910052906 cristobalite Inorganic materials 0.000 abstract 4
- 239000000377 silicon dioxide Substances 0.000 abstract 4
- 235000012239 silicon dioxide Nutrition 0.000 abstract 4
- 229910052682 stishovite Inorganic materials 0.000 abstract 4
- 229910052905 tridymite Inorganic materials 0.000 abstract 4
- 235000012431 wafers Nutrition 0.000 description 90
- 239000010410 layer Substances 0.000 description 53
- 239000010408 film Substances 0.000 description 40
- 238000005498 polishing Methods 0.000 description 10
- 230000000694 effects Effects 0.000 description 5
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 4
- 238000004140 cleaning Methods 0.000 description 3
- 238000011109 contamination Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 229910001385 heavy metal Inorganic materials 0.000 description 3
- 230000003746 surface roughness Effects 0.000 description 3
- 229910021529 ammonia Inorganic materials 0.000 description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
- H01L21/3226—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering of silicon on insulator
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、絶縁層上に単結晶シリ
コン層を設けたＳＯＩ（Silicon On Insula-tor ）基板
における、改良された構造の基板と、その製造方法に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an SOI (Silicon On Insula-tor) substrate having a single crystal silicon layer on an insulating layer, which has an improved structure, and a manufacturing method thereof.
【０００２】[0002]
【従来の技術】従来、ＳＯＩ基板の製造方法の一例とし
て、単結晶シリコンからなるボンドウエーハ（ＳＯＩ基
板となったときＳＯＩ層を形成するウエーハ、以下ボン
ドウエーハと記載する）と、ベースウエーハ（ＳＯＩ基
板となったとき、ＳＯＩ層の支持体を形成するウエー
ハ、以下ベースウエーハと記載する）とを用意し、ボン
ドウエーハを熱酸化してＳｉＯ2 膜を形成し、これらボ
ンドウエーハとベースウエーハとを直接重ね合わせ酸化
性雰囲気中で熱処理することにより、前記ＳｉＯ2膜を
介して両者を結合する方法が知られている。2. Description of the Related Art Conventionally, as an example of a method for manufacturing an SOI substrate, a bond wafer made of single crystal silicon (a wafer that forms an SOI layer when it becomes an SOI substrate, hereinafter referred to as a bond wafer) and a base wafer (SOI A wafer that forms a support for the SOI layer when it becomes a substrate, hereinafter referred to as a base wafer) is prepared, and the bond wafer is thermally oxidized to form a SiO 2 film, and the bond wafer and the base wafer are formed. A method is known in which both layers are bonded together through the SiO 2 film by heat treatment in an overlapping oxidizing atmosphere.
【０００３】[0003]
【発明が解決しようとする課題】ところが、上記従来の
方法では、ＳＯＩ基板のＳＯＩ層内にゲッタリングサイ
トを形成することができないため、半導体装置の製造工
程における重金属による汚染に対応できないという問題
があった。また、上記方法によるＳＯＩ基板おいて、Ｓ
ｉＯ2 膜（埋込酸化膜）とＳＯＩ層との界面ではゲッタ
リング効果が殆どないため、前記結合工程における熱酸
化処理時に重金属汚染に起因するとみられるＯＳＦ（酸
化誘起積層欠陥）が多発する問題があった。However, in the above-mentioned conventional method, since the gettering site cannot be formed in the SOI layer of the SOI substrate, there is a problem that it is not possible to cope with the contamination by the heavy metal in the manufacturing process of the semiconductor device. there were. In the SOI substrate manufactured by the above method, S
Since there is almost no gettering effect at the interface between the iO 2 film (buried oxide film) and the SOI layer, OSF (oxidation-induced stacking fault), which is considered to be caused by heavy metal contamination during the thermal oxidation treatment in the bonding step, frequently occurs. was there.
【０００４】本発明は、上記の点を解決しようとするも
ので、その目的は、ＳＯＩ層内にゲッタリングサイトを
有するＳＯＩ基板及び、このようなＳＯＩ基板を簡単な
プロセスで製造することができる方法を提供することに
ある。The present invention is intended to solve the above problems, and an object thereof is to manufacture an SOI substrate having a gettering site in an SOI layer and such an SOI substrate by a simple process. To provide a method.
【０００５】[0005]
【課題を解決するための手段】請求項１に記載のＳＯＩ
基板は、半導体素子を形成せしめるためのＳＯＩ層と、
絶縁層との間に多結晶シリコンの薄層を設けてなること
を特徴とする。An SOI according to claim 1
The substrate has an SOI layer for forming a semiconductor element,
It is characterized in that a thin layer of polycrystalline silicon is provided between the insulating layer and the insulating layer.
【０００６】請求項２に記載のＳＯＩ基板の製造方法
は、単結晶シリコンからなるボンドウエーハの表面にＣ
ＶＤ法により膜厚０．５〜２μｍの多結晶シリコン層を
堆積させた後、該多結晶シリコン層の上層を熱酸化して
ＳｉＯ2 膜となし、このボンドウエーハをシリコンから
なるベースウエーハと、前記ＳｉＯ2 膜を介して結合す
るか、または前記ボンドウエーハの多結晶シリコン層は
酸化せず、シリコンからなるベースウエーハを熱酸化し
てＳｉＯ2 膜を形成し、このベースウエーハを前記多結
晶シリコン層を設けたボンドウエーハと、前記ＳｉＯ2
膜を介して結合することを特徴とする。ここに、前記ベ
ースウエーハはその材質がシリコンであれば良く、必ず
しも完全な単結晶シリコンであることを必要としない。In the method of manufacturing an SOI substrate according to a second aspect, C is formed on the surface of a bond wafer made of single crystal silicon.
After depositing a polycrystalline silicon layer having a film thickness of 0.5 to 2 μm by the VD method, the upper layer of the polycrystalline silicon layer is thermally oxidized to form a SiO 2 film, and this bond wafer is used as a base wafer made of silicon. Bonding via the SiO 2 film, or the polycrystalline silicon layer of the bond wafer is not oxidized, but a base wafer made of silicon is thermally oxidized to form an SiO 2 film, and the base wafer is formed of the polycrystalline silicon. A bond wafer provided with a layer and the above-mentioned SiO 2
It is characterized by binding through a membrane. Here, the base wafer only needs to be made of silicon and does not necessarily need to be completely single crystal silicon.
【０００７】請求項３に記載のＳＯＩ基板の製造方法
は、前記多結晶シリコン層の上層、またはシリコンから
なるベースウエーハの熱酸化を、９００〜１２００℃の
条件で行い、ＳｉＯ2 膜の膜厚を０．１〜２μｍとする
ことを特徴とする。According to a third aspect of the present invention, in the method of manufacturing an SOI substrate, thermal oxidation of the upper layer of the polycrystalline silicon layer or the base wafer made of silicon is performed at a temperature of 900 to 1200 ° C. to obtain a film thickness of a SiO 2 film. Is 0.1 to 2 μm.
【０００８】[0008]
【作用】本発明（請求項１のＳＯＩ基板、請求項２のＳ
ＯＩ基板の製造方法）においては、２枚のシリコンウエ
ーハの結合界面に多結晶シリコン層とＳｉＯ2 膜が重層
・介在した形態で形成され、多結晶シリコン層がＳＯＩ
層に対して、エクストリンシックゲッタリング作用をな
すＳＯＩ基板が得られる。The present invention (the SOI substrate according to claim 1 and the S substrate according to claim 2)
In the method of manufacturing an OI substrate), a polycrystal silicon layer and a SiO 2 film are formed in a form of a multi-layer / interposition at a bonding interface of two silicon wafers, and the polycrystal silicon layer is an SOI.
An SOI substrate is obtained which has an extrinsic gettering effect on the layers.
【０００９】なお、多結晶または単結晶のシリコン層は
熱酸化によりＳｉＯ2 となる時、その厚さは約２倍に増
加する。従って、請求項３において多結晶シリコン層を
熱酸化して０．１〜２μｍのＳｉＯ2 膜を形成させる時
に費消される多結晶シリコン層は、その約１／２の０．
０５〜１μｍに相当するので、残された多結晶シリコン
層がエクストリンシックゲッタリング作用をなす。When a polycrystalline or single-crystal silicon layer is converted to SiO 2 by thermal oxidation, its thickness is about doubled. Therefore, in claim 3, the polycrystalline silicon layer consumed at the time of thermally oxidizing the polycrystalline silicon layer to form the SiO 2 film having a thickness of 0.1 to 2 μm has a half of the .0.
Since it corresponds to 05 to 1 μm, the remaining polycrystalline silicon layer has an extrinsic gettering function.
【００１０】[0010]
【実施例】次に、本発明の実施例を図面に基づいて説明
する。 実施例１ この実施例は、ボンドウエーハ上に形成した多結晶シリ
コン層上にＳｉＯ2 膜を設け、該ＳｉＯ2 膜を介してベ
ースウエーハと結合するものである。まず、鏡面研磨さ
れた単結晶シリコンウエーハであるボンドウエーハ１
と、ベースウエーハ２とを用意し〔図１（ａ）〕、前記
鏡面研磨面を結合面とする。この結合面の表面粗さはＲ
ａ＝０．４μｍ以下とすることが好ましく、後記する結
合ウエーハ３１の結合強度が十分となる。鏡面研磨後の
ウエーハ１，２には研磨時の接着剤、研磨剤等が残留し
ており、これらを除去するためにアンモニア／過酸化水
素、フッ酸系の洗浄液等により洗浄する。Embodiments of the present invention will now be described with reference to the drawings. Example 1 In this example, a SiO 2 film is provided on a polycrystalline silicon layer formed on a bond wafer, and the SiO 2 film is bonded to the base wafer via the SiO 2 film. First, a bond wafer 1 which is a mirror-polished single crystal silicon wafer
And a base wafer 2 are prepared [FIG. 1 (a)], and the mirror-polished surface is used as a bonding surface. The surface roughness of this bonding surface is R
It is preferable that a = 0.4 μm or less, and the bonding strength of the bonding wafer 31 described later will be sufficient. The wafers 1 and 2 after mirror-polishing have residual adhesives, polishing agents, etc. at the time of polishing, and in order to remove them, they are cleaned with ammonia / hydrogen peroxide, hydrofluoric acid-based cleaning liquid, etc.
【００１１】その後、ボンドウエーハ１の全表面（また
は片面）に、減圧ＣＶＤ法による多結晶シリコン層を温
度６２０℃、圧力０．３ｔｏｒｒ、成長速度８０Å／分
の条件で膜厚１．５μｍの多結晶シリコン層１１を堆積
させる〔図１（ｂ）〕。次に、ボンドウエーハ１の全表
面（または多結晶シリコン層１１面）について請求項３
に記載の条件で熱酸化を行い、多結晶シリコン層１１の
上層をＳｉＯ2膜（酸化膜）１２とする〔図１
（ｃ）〕。ついで、ボンドウエーハ１とベースウエーハ
２のそれぞれの結合面を充分、清浄にした後、直ちにボ
ンドウエーハ１とベースウエーハ２とを直接重ね合わせ
て一体化し〔図１（ｄ）〕、この一体化ウエーハ２１を
酸化性雰囲気中（または場合によりＮ2雰囲気中）、約
１１００℃の温度で約１２０分間、加熱処理することに
よって一体化ウエーハ２１の結合強度を高めると共に、
その全表面に厚さ約０．５〜１．０μｍのＳｉＯ2 膜
（酸化膜）１３を形成して結合ウエーハ３１となし、前
記多結晶シリコン層１１およびＳｉＯ2 膜１２をボンド
ウエーハ１とベースウエーハ２との境界部に埋め込んだ
形態とする〔図１（ｅ）〕。さらに、結合ウエーハ３１
のボンドウエーハ側を１次研磨して、ボンドウエーハ１
側に厚さｔ1 （例えば６μｍ）の単結晶シリコン層を残
した後〔図１（ｆ）〕、２次研磨してボンドウエーハ１
側に厚さｔ2 （例えば３μｍ）の単結晶シリコン層を残
して薄膜化し、目的のＳＯＩ基板４１を得る〔図１
（ｇ）〕。After that, a polycrystalline silicon layer formed by the low pressure CVD method is formed on the entire surface (or one side) of the bond wafer 1 at a temperature of 620 ° C., a pressure of 0.3 torr, and a growth rate of 80 Å / min. A crystalline silicon layer 11 is deposited [FIG. 1 (b)]. Next, the entire surface of the bond wafer 1 (or the surface of the polycrystalline silicon layer 11) is claimed in claim 3.
Thermal oxidation is carried out under the conditions described in 1. to form an upper layer of the polycrystalline silicon layer 11 as a SiO 2 film (oxide film) 12 [FIG.
(C)]. Then, after thoroughly cleaning the bonding surfaces of the bond wafer 1 and the base wafer 2 respectively, the bond wafer 1 and the base wafer 2 are immediately superposed and integrated [FIG. 1 (d)], and the integrated wafer is formed. 21 is heated in an oxidizing atmosphere (or N 2 atmosphere in some cases) at a temperature of about 1100 ° C. for about 120 minutes to increase the bonding strength of the integrated wafer 21 and
A SiO 2 film (oxide film) 13 having a thickness of about 0.5 to 1.0 μm is formed on the entire surface to form a bonded wafer 31, and the polycrystalline silicon layer 11 and the SiO 2 film 12 are bonded to the bond wafer 1 and a base. It is embedded in the boundary with the wafer 2 [FIG. 1 (e)]. Furthermore, the bonded wafer 31
Bond wafer 1 is first polished to the bond wafer 1 side.
After leaving a single-crystal silicon layer having a thickness t 1 (for example, 6 μm) on the side [FIG. 1 (f)], secondary polishing is performed to bond wafer 1
A single crystal silicon layer having a thickness t 2 (for example, 3 μm) is left on the side to form a thin film, thereby obtaining an intended SOI substrate 41 [FIG.
(G)].
【００１２】なお、減圧ＣＶＤ法による多結晶シリコン
層１１の堆積は温度５８０〜６５０℃、圧力０．１〜
０．５ｔｏｒｒ、多結晶シリコン成長速度を５０〜２５
０Å／分の条件で行い、多結晶シリコン層１１の層厚を
０．５〜２μｍとすることにより、粒径がそろい表面粗
さが小さく、その後の結合工程において支障がない程度
の滑らかな多結晶シリコン表面層を形成することができ
る。The deposition of the polycrystalline silicon layer 11 by the low pressure CVD method is performed at a temperature of 580 to 650 ° C. and a pressure of 0.1 to 650.
0.5 torr, polycrystalline silicon growth rate 50 to 25
By setting the thickness of the polycrystalline silicon layer 11 to 0.5 to 2 μm under the condition of 0 Å / min, the surface roughness is uniform and the grain size is small, and the smooth and smooth surface is not disturbed in the subsequent bonding step. A crystalline silicon surface layer can be formed.
【００１３】また、ＳｉＯ2 膜形成条件を請求項３に記
載のとおりに設定し、該ＳｉＯ2 膜の厚さを０．１〜２
μｍとすることにより、ＳＯＩ基板の埋込み絶縁膜を形
成することができる。この場合、熱酸化温度を１１００
℃、ＳｉＯ2 膜の厚さを０．５μｍとするのが好まし
い。Further, the conditions for forming the SiO 2 film are set as described in claim 3, and the thickness of the SiO 2 film is 0.1 to 2
By setting the thickness to be μm, the embedded insulating film of the SOI substrate can be formed. In this case, the thermal oxidation temperature is set to 1100.
It is preferable that the temperature of the SiO 2 film is 0.5 μm.
【００１４】実施例２ この実施例は、ベースウエーハ上にＳｉＯ2 膜を設け、
該ＳｉＯ2 膜を介して、多結晶シリコン層を有するボン
ドウエーハと結合するものである。まず、鏡面研磨され
た単結晶シリコンウエーハであるボンドウエーハ１と、
ベースウエーハ２とを用意し〔図２（ａ）〕、前記鏡面
研磨面を結合面とする。この結合面の表面粗さは実施例
１と同様とし、鏡面研磨後のウエーハ１，２は同様にア
ンモニア／過酸化水素、フッ酸系の洗浄液等により洗浄
する。Example 2 In this example, a SiO 2 film was provided on a base wafer,
It is to be bonded to a bond wafer having a polycrystalline silicon layer through the SiO 2 film. First, bond wafer 1 which is a mirror-polished single crystal silicon wafer,
A base wafer 2 is prepared [FIG. 2 (a)], and the mirror-polished surface is used as a bonding surface. The surface roughness of this bonding surface is the same as in Example 1, and the wafers 1 and 2 after mirror-polishing are similarly cleaned with an ammonia / hydrogen peroxide, hydrofluoric acid-based cleaning liquid, or the like.
【００１５】その後、ボンドウエーハ１の全表面（また
は片面）に、実施例１と同じ条件で減圧ＣＶＤ法による
多結晶シリコン層１１を堆積させ、ベースウエーハ２で
は、その全表面（または片面）について９００〜１２０
０℃の条件で熱酸化を行い、ＳｉＯ2 膜（酸化膜）１２
を形成する〔図２（ｂ）〕。ついで、実施例１と同じ要
領でボンドウエーハ１とベースウエーハ２の結合面を充
分清浄にした後、した後、直ちにボンドウエーハ１とベ
ースウエーハ２とを直接重ね合わせて一体化し〔図２
（ｃ）〕、この一体化ウエーハ６１を酸化性雰囲気中
（または場合によりＮ2 雰囲気中）、約１１００℃の温
度で約１２０分間、加熱処理することによって一体化ウ
エーハ６１の結合強度を高めると共に、その全表面に厚
さ約０．５〜１．０μｍのＳｉＯ2 膜（酸化膜）１３を
形成して結合ウエーハ７１となし、前記多結晶シリコン
層１１およびＳｉＯ2 膜１２をボンドウエーハ１とベー
スウエーハ２との境界部に埋め込んだ形態とする〔図２
（ｄ）〕。さらに、結合ウエーハ７１のボンドウエーハ
側を１次研磨して、ボンドウエーハ１側に厚さｔ1 （例
えば６μｍ）の単結晶シリコン層を残した後〔図２
（ｅ）〕、２次研磨してボンドウエーハ１側に厚さｔ2
（例えば３μｍ）の単結晶シリコン層を残して薄膜化
し、目的のＳＯＩ基板８１を得る〔図２（ｆ）〕。After that, a polycrystalline silicon layer 11 is deposited on the entire surface (or one surface) of the bond wafer 1 by the low pressure CVD method under the same conditions as in Example 1, and the entire surface (or one surface) of the base wafer 2 is deposited. 900-120
Thermal oxidation is performed under the condition of 0 ° C., and SiO 2 film (oxide film) 12
Are formed [FIG. 2 (b)]. Then, the bonding surfaces of the bond wafer 1 and the base wafer 2 were sufficiently cleaned in the same manner as in Example 1, and immediately thereafter, the bond wafer 1 and the base wafer 2 were directly superposed and integrated (see FIG. 2).
(C)], the integrated wafer 61 is heated in an oxidizing atmosphere (or N 2 atmosphere in some cases) at a temperature of about 1100 ° C. for about 120 minutes to increase the bonding strength of the integrated wafer 61. A SiO 2 film (oxide film) 13 having a thickness of about 0.5 to 1.0 μm is formed on the entire surface thereof to form a bonded wafer 71, and the polycrystalline silicon layer 11 and the SiO 2 film 12 are bonded to the bonded wafer 1. It is configured to be embedded at the boundary with the base wafer 2 [Fig. 2
(D)]. Further, the bond wafer side of the bonded wafer 71 is primarily polished to leave a single crystal silicon layer having a thickness t 1 (for example, 6 μm) on the bond wafer 1 side [FIG.
(E)] Secondary polishing is performed to obtain a thickness t 2 on the bond wafer 1 side.
The target SOI substrate 81 is obtained by thinning the single crystal silicon layer (for example, 3 μm) to leave it (FIG. 2F).
【００１６】ベースウエーハ２のＳｉＯ2 膜１２の膜厚
は０．１〜２μｍの範囲とすることが好ましく、これに
よりＳＯＩ基板の埋込み絶縁膜を形成することができ
る。この場合、ベースウエーハ２の熱酸化温度を１１０
０℃、ＳｉＯ2 膜１２の膜厚を０．５μｍとするのが好
ましい。The thickness of the SiO 2 film 12 of the base wafer 2 is preferably in the range of 0.1 to 2 μm, whereby the buried insulating film of the SOI substrate can be formed. In this case, the thermal oxidation temperature of the base wafer 2 is set to 110.
At 0 ° C., the thickness of the SiO 2 film 12 is preferably 0.5 μm.
【００１７】[0017]
【発明の効果】以上の説明で明かなように、請求項１に
記載のＳＯＩ基板は、半導体素子を形成せしめるために
ＳＯＩ層と絶縁層との間に多結晶シリコンの薄層を設け
てなるものであり、また、請求項２に記載のＳＯＩ基板
の製造方法は、ボンドウエーハとベースウエーハとの結
合界面に埋込多結晶シリコン層と、埋込ＳｉＯ2 膜とを
重層して設けるものである。そして、請求項１のＳＯＩ
基板および請求項２の製造方法によるＳＯＩ基板では、
多結晶シリコン層の多結晶シリコン粒界により大きなゲ
ッター機能が得られるので、ボンドウエーハとベースウ
エーハとを一体化し熱酸化して結合ウエーハとする際に
ＯＳＦが発生することはなくなり、また、このＳＯＩ基
板を使用して半導体装置を製造する工程での重金属汚染
に対しても前記多結晶シリコン粒界が同様のゲッター機
能を発揮するため、その製造歩留りが著しく向上する効
果がある。さらに、請求項２の製造方法によれば、上記
ＳＯＩ基板を簡単なプロセスで製造することができる効
果がある。請求項３に記載のＳＯＩ基板の製造方法によ
れば、多結晶シリコン層の上層にＳｉＯ2 酸化膜を形成
する条件を所定範囲に設定することで、ＳＯＩ基板の埋
込み絶縁膜を形成することができる効果がある。As is apparent from the above description, the SOI substrate according to claim 1 has a thin layer of polycrystalline silicon provided between the SOI layer and the insulating layer in order to form a semiconductor element. The method for manufacturing an SOI substrate according to claim 2 is one in which an embedded polycrystalline silicon layer and an embedded SiO 2 film are provided at the bonding interface between a bond wafer and a base wafer as a multilayer. is there. The SOI of claim 1
In the substrate and the SOI substrate according to the manufacturing method of claim 2,
Since a large getter function can be obtained by the polycrystalline silicon grain boundaries of the polycrystalline silicon layer, OSF is not generated when the bond wafer and the base wafer are integrated and thermally oxidized to form a bonded wafer. Since the polycrystalline silicon grain boundaries also exhibit the same getter function against heavy metal contamination in the process of manufacturing a semiconductor device using a substrate, there is an effect of significantly improving the manufacturing yield. Further, according to the manufacturing method of the second aspect, there is an effect that the SOI substrate can be manufactured by a simple process. According to the method for manufacturing an SOI substrate of claim 3, the embedded insulating film of the SOI substrate can be formed by setting the condition for forming the SiO 2 oxide film on the upper layer of the polycrystalline silicon layer within a predetermined range. There is an effect that can be done.
【図１】本発明の実施例１をウエーハの断面図で示す工
程説明図であって、（ａ）はボンドウエーハおよびベー
スウエーハを、（ｂ）は多結晶シリコン層堆積後のボン
ドウエーハを、（ｃ）はＳｉＯ2 膜形成後のボンドウエ
ーハを、（ｄ）は一体化ウエーハを、（ｅ）は結合ウエ
ーハを、（ｆ）は１次研磨後の結合ウエーハを、（ｇ）
は２次研磨後の結合ウエーハすなわちＳＯＩ基板を、そ
れぞれ示す。FIG. 1 is a process explanatory view showing a cross-sectional view of a wafer in Example 1 of the present invention, in which (a) shows a bond wafer and a base wafer, (b) shows a bond wafer after deposition of a polycrystalline silicon layer, (C) is a bond wafer after the SiO 2 film is formed, (d) is an integrated wafer, (e) is a bonded wafer, (f) is a bonded wafer after primary polishing, and (g) is a bonded wafer.
Indicates a bonded wafer after secondary polishing, that is, an SOI substrate, respectively.
【図２】本発明の実施例２をウエーハの断面図で示す工
程説明図であって、（ａ）はボンドウエーハおよびベー
スウエーハを、（ｂ）は多結晶シリコン層堆積後のボン
ドウエーハおよび、ＳｉＯ2 膜形成後のベースウエーハ
を、（ｃ）は一体化ウエーハを、（ｄ）は結合ウエーハ
を、（ｅ）は１次研磨後の結合ウエーハを、（ｆ）は２
次研磨後の結合ウエーハすなわちＳＯＩ基板を、それぞ
れ示す。FIG. 2 is a process explanatory view showing a cross-sectional view of a wafer in Example 2 of the present invention, in which (a) is a bond wafer and a base wafer, (b) is a bond wafer after deposition of a polycrystalline silicon layer, and The base wafer after the formation of the SiO 2 film, (c) the integrated wafer, (d) the bonded wafer, (e) the bonded wafer after the primary polishing, and (f) 2
The bonded wafer after the next polishing, that is, the SOI substrate is shown.
１ ボンドウエーハ ２ ベースウエーハ １１ 多結晶シリコン層 １２，１３ ＳｉＯ2 膜 ２１，６１ 一体化ウエーハ ３１，７１ 結合ウエーハ ４１，８１ ＳＯＩ基板1 Bond Wafer 2 Base Wafer 11 Polycrystalline Silicon Layer 12, 13 SiO 2 Film 21, 61 Integrated Wafer 31, 71 Bonded Wafer 41, 81 SOI Substrate
───────────────────────────────────────────────────── フロントページの続き (72)発明者 中野 正剛 群馬県安中市磯部２丁目13番１号 信越半 導体株式会社半導体磯部研究所内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masago Nakano 2-13-1, Isobe, Annaka-shi, Gunma Shin-Etsu Semiconductor Co., Ltd.
Claims (3)
シリコン層（以下、ＳＯＩ層という）と、絶縁層との間
に多結晶シリコンの薄層を設けてなるＳＯＩ基板。1. An SOI substrate in which a thin layer of polycrystalline silicon is provided between a single crystal silicon layer for forming a semiconductor element (hereinafter referred to as an SOI layer) and an insulating layer.
（ＳＯＩ基板となったとき、ＳＯＩ層を形成するウエー
ハ）の表面にＣＶＤ法により膜厚０．５〜２μｍの多結
晶シリコン層を堆積させた後、該多結晶シリコン層の上
層を熱酸化してＳｉＯ2 膜となし、このボンドウエーハ
をシリコンからなるベースウエーハ（ＳＯＩ基板となっ
たとき、ＳＯＩ層の支持体を形成するウエーハ）と、前
記ＳｉＯ2 膜を介して結合するか、または前記ボンドウ
エーハの多結晶シリコン層は酸化せず、シリコンからな
るベースウエーハを熱酸化してＳｉＯ2 膜を形成し、こ
のベースウエーハを前記多結晶シリコン層を設けたボン
ドウエーハと、前記ＳｉＯ2 膜を介して結合することを
特徴とするＳＯＩ基板の製造方法。2. After depositing a polycrystalline silicon layer having a film thickness of 0.5 to 2 μm by a CVD method on the surface of a bond wafer made of single crystal silicon (a wafer which forms an SOI layer when it becomes an SOI substrate). An upper layer of the polycrystalline silicon layer is thermally oxidized to form a SiO 2 film, and this bond wafer is formed of a base wafer made of silicon (a wafer that forms a support for the SOI layer when it becomes an SOI substrate); or linked via the 2 film or the polycrystalline silicon layer of the bond wafer is not oxidized, the base wafer made of silicon is thermally oxidized to form a SiO 2 film, the the base wafer the polycrystalline silicon layer A method of manufacturing an SOI substrate, comprising bonding the provided bond wafer through the SiO 2 film.
リコンからなるベースウエーハの熱酸化を、９００〜１
２００℃の条件で行い、ＳｉＯ2 膜の膜厚を０．１〜２
μｍとすることを特徴とする請求項２に記載のＳＯＩ基
板の製造方法。3. The thermal oxidation of the upper layer of the polycrystalline silicon layer or the base wafer made of silicon is performed by 900-1.
It is performed under the condition of 200 ° C. and the thickness of the SiO 2 film is 0.1 to 2
3. The method for manufacturing an SOI substrate according to claim 2, wherein the SOI substrate has a thickness of μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8403693A JPH06275525A (en) | 1993-03-18 | 1993-03-18 | Soi substrate and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8403693A JPH06275525A (en) | 1993-03-18 | 1993-03-18 | Soi substrate and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06275525A true JPH06275525A (en) | 1994-09-30 |
Family
ID=13819301
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8403693A Pending JPH06275525A (en) | 1993-03-18 | 1993-03-18 | Soi substrate and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06275525A (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5665631A (en) * | 1995-05-11 | 1997-09-09 | Samsung Electronics Co., Ltd. | SOI substrate manufacturing method |
| FR2777115A1 (en) * | 1998-04-07 | 1999-10-08 | Commissariat Energie Atomique | PROCESS FOR TREATING SEMICONDUCTOR SUBSTRATES AND STRUCTURES OBTAINED BY THIS PROCESS |
| KR100274072B1 (en) * | 1997-12-30 | 2000-12-15 | 김영환 | Manufacturing method of single crystal soi wafer |
| JP2004503942A (en) * | 2000-06-16 | 2004-02-05 | エス オー イ テク シリコン オン インシュレータ テクノロジース | Substrate manufacturing method and substrate obtained by the method |
| JP2004320050A (en) * | 2004-06-29 | 2004-11-11 | Sumitomo Mitsubishi Silicon Corp | Soi substrate and method for manufacturing same |
| JP2006303218A (en) * | 2005-04-21 | 2006-11-02 | Sumco Corp | Manufacturing method of soi substrate |
| WO2007072624A1 (en) | 2005-12-19 | 2007-06-28 | Shin-Etsu Handotai Co., Ltd. | Method for manufacturing soi substrate, and soi substrate |
| WO2007125771A1 (en) | 2006-04-27 | 2007-11-08 | Shin-Etsu Handotai Co., Ltd. | Soi wafer manufacturing method |
| KR100850119B1 (en) * | 2006-12-26 | 2008-08-04 | 동부일렉트로닉스 주식회사 | Soi sunstrate and method of manufacturong thereof |
| US7589023B2 (en) | 2000-04-24 | 2009-09-15 | Sumitomo Mitsubishi Silicon Corporation | Method of manufacturing semiconductor wafer |
| JP2010118420A (en) * | 2008-11-12 | 2010-05-27 | Semiconductor Energy Lab Co Ltd | Method for manufacturing soi substrate |
-
1993
- 1993-03-18 JP JP8403693A patent/JPH06275525A/en active Pending
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5665631A (en) * | 1995-05-11 | 1997-09-09 | Samsung Electronics Co., Ltd. | SOI substrate manufacturing method |
| KR100274072B1 (en) * | 1997-12-30 | 2000-12-15 | 김영환 | Manufacturing method of single crystal soi wafer |
| FR2777115A1 (en) * | 1998-04-07 | 1999-10-08 | Commissariat Energie Atomique | PROCESS FOR TREATING SEMICONDUCTOR SUBSTRATES AND STRUCTURES OBTAINED BY THIS PROCESS |
| WO1999052145A1 (en) * | 1998-04-07 | 1999-10-14 | Commissariat A L'energie Atomique | Heat treatment method for semiconductor substrates |
| US7589023B2 (en) | 2000-04-24 | 2009-09-15 | Sumitomo Mitsubishi Silicon Corporation | Method of manufacturing semiconductor wafer |
| US8283252B2 (en) | 2000-04-24 | 2012-10-09 | Sumitomo Mitsubishi Silicon Corporation | Method of manufacturing semiconductor wafer |
| JP2004503942A (en) * | 2000-06-16 | 2004-02-05 | エス オー イ テク シリコン オン インシュレータ テクノロジース | Substrate manufacturing method and substrate obtained by the method |
| JP2004320050A (en) * | 2004-06-29 | 2004-11-11 | Sumitomo Mitsubishi Silicon Corp | Soi substrate and method for manufacturing same |
| JP2006303218A (en) * | 2005-04-21 | 2006-11-02 | Sumco Corp | Manufacturing method of soi substrate |
| US7749861B2 (en) | 2005-12-19 | 2010-07-06 | Shin-Etsu Handotai Co., Ltd. | Method for manufacturing SOI substrate and SOI substrate |
| WO2007072624A1 (en) | 2005-12-19 | 2007-06-28 | Shin-Etsu Handotai Co., Ltd. | Method for manufacturing soi substrate, and soi substrate |
| WO2007125771A1 (en) | 2006-04-27 | 2007-11-08 | Shin-Etsu Handotai Co., Ltd. | Soi wafer manufacturing method |
| US7910455B2 (en) | 2006-04-27 | 2011-03-22 | Shin-Etsu Handotai Co., Ltd. | Method for producing SOI wafer |
| KR100850119B1 (en) * | 2006-12-26 | 2008-08-04 | 동부일렉트로닉스 주식회사 | Soi sunstrate and method of manufacturong thereof |
| JP2010118420A (en) * | 2008-11-12 | 2010-05-27 | Semiconductor Energy Lab Co Ltd | Method for manufacturing soi substrate |
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