JP2927280B2 - Method for manufacturing SOI substrate - Google Patents

Method for manufacturing SOI substrate

Info

Publication number
JP2927280B2
JP2927280B2 JP25223197A JP25223197A JP2927280B2 JP 2927280 B2 JP2927280 B2 JP 2927280B2 JP 25223197 A JP25223197 A JP 25223197A JP 25223197 A JP25223197 A JP 25223197A JP 2927280 B2 JP2927280 B2 JP 2927280B2
Authority
JP
Japan
Prior art keywords
oxide film
film
substrate
crystal silicon
silicon substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP25223197A
Other languages
Japanese (ja)
Other versions
JPH1197320A (en
Inventor
研也 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP25223197A priority Critical patent/JP2927280B2/en
Publication of JPH1197320A publication Critical patent/JPH1197320A/en
Application granted granted Critical
Publication of JP2927280B2 publication Critical patent/JP2927280B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Element Separation (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明はSOI基板の製造方
法に関し、特にSOI基板の反り防止に有効な製造方法
に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an SOI substrate, and more particularly to a method of manufacturing an SOI substrate effective for preventing warpage.

【0002】[0002]

【従来の技術】ウェーハ貼り合わせ技術を用いて作製さ
れるSilicon−On−Insulator(SO
I)基板は、埋込絶縁膜(通常は酸化膜)の厚さを、形
成プロセスが許す範囲内で任意に決定することができ、
高耐圧デバイス用には一般に1〜3μmといった厚さの
埋込酸化膜を有するSOI基板が使用される。また、例
えば6インチ径のSOI基板では全体の厚さは600〜
700μmであるが、それに対してSOI層は厚くても
10〜20μm程度で全体の厚さと比較して非常に薄
い。このような構造のSOI基板では、酸化膜とシリコ
ンの熱膨張率の違いから、基板表面と裏面とでの応力の
差が大きくなり、反りが生じてしまう。この反りは、デ
バイスの製造歩留まりを悪くする、あるいは製造装置の
許容量を越えるような場合工程を進められない、といっ
た弊害を引き起こすことになるため、通常は基板裏面
に、ある厚さの酸化膜を形成し反りを緩和している。そ
のような反りを低減する製造方法は、特公平7−955
05号公報(第1の公報)、特開平6−13593号公
報(第2の公報)等に示されている。
2. Description of the Related Art A silicon-on-insulator (SO) manufactured using a wafer bonding technique.
I) The thickness of the buried insulating film (usually an oxide film) of the substrate can be arbitrarily determined within a range permitted by the forming process.
For high breakdown voltage devices, an SOI substrate having a buried oxide film having a thickness of 1 to 3 μm is generally used. Further, for example, in the case of an SOI substrate having a diameter of 6 inches, the total thickness is 600 to
On the other hand, the thickness of the SOI layer is about 10 to 20 μm at most, which is very thin compared to the entire thickness. In an SOI substrate having such a structure, a difference in stress between the front surface and the rear surface of the substrate becomes large due to a difference in thermal expansion coefficient between the oxide film and silicon, and warpage occurs. Since this warp causes a bad effect such as deteriorating the manufacturing yield of the device or preventing the process from proceeding when the manufacturing equipment exceeds the allowable amount, the oxide film having a certain thickness is usually formed on the back surface of the substrate. To reduce warpage. A manufacturing method for reducing such warpage is disclosed in Japanese Patent Publication No. 7-955.
No. 05 (first publication) and Japanese Patent Application Laid-Open No. 6-13593 (second publication).

【0003】図4は第1の従来例として、第1の公報に
より示されたSOI基板の製造方法の工程順断面図を示
す。まず、図4(a)に示すように、単結晶シリコン基
板1を酸化処理して、その片側鏡面に厚さ500μmの
酸化膜2を形成する。、次に図4(b)に示すように、
単結晶シリコン基板1に単結晶シリコン基板3を貼り合
わせ、一体化された1枚の基板とする。次に図4(c)
に示すように、一体化された単結晶シリコン基板を酸化
性雰囲気中で約1100℃の温度で約120分間、熱酸
化処理することによって、一体化された単結晶シリコン
基板を強固に接合するとともに、全表面に厚さ約500
nmの酸化膜4を形成する。次に図4(d)に示すよう
に、単結晶シリコン基板1の表面を研磨し所望の厚さま
で薄膜化し、SOI層5を形成する。この時、単結晶シ
リコン基板3の上下面は熱膨張率が等しい同一厚さの酸
化膜によって覆われるため、一体化された単結晶シリコ
ン基板の反りは軽減される。
FIG. 4 is a cross-sectional view in the order of steps of a method of manufacturing an SOI substrate disclosed in the first publication as a first conventional example. First, as shown in FIG. 4A, the single crystal silicon substrate 1 is oxidized to form an oxide film 2 having a thickness of 500 μm on one mirror surface. Then, as shown in FIG.
The single-crystal silicon substrate 3 is bonded to the single-crystal silicon substrate 1 to form one integrated substrate. Next, FIG.
As shown in (1), the integrated single-crystal silicon substrate is thermally oxidized in an oxidizing atmosphere at a temperature of about 1100 ° C. for about 120 minutes, thereby firmly joining the integrated single-crystal silicon substrate. , About 500 on all surfaces
An oxide film 4 of nm is formed. Next, as shown in FIG. 4D, the surface of the single-crystal silicon substrate 1 is polished and thinned to a desired thickness, and the SOI layer 5 is formed. At this time, since the upper and lower surfaces of the single crystal silicon substrate 3 are covered with oxide films having the same thermal expansion coefficient and the same thickness, the warpage of the integrated single crystal silicon substrate is reduced.

【0004】次に、図5は第2の従来例として、第2の
公報により示されたSOI基板の製造方法の工程順断面
図を示す。まず図5(a)に示すように、単結晶シリコ
ン基板1に酸化膜2を形成し、続いて図5(b)に示す
ように、CVD法により窒化膜6を堆積させる。次に図
5(c)に示すように、単結晶シリコン基板3を貼り合
わせ、1100℃程度の熱処理を行う。この後、図5
(d)に示すように、単結晶シリコン基板1を研磨して
いき所望の厚さのSOI層5を残して完成する。このS
OI基板の埋込絶縁膜層における窒化膜6には引っ張り
応力が働き、それは酸化膜2の圧縮応力をうち消す方向
に働くので、SOI基板が凸型にそるもを防止する効果
がある。
Next, FIG. 5 is a sectional view showing a method of manufacturing an SOI substrate according to a second prior art as a second conventional example in the order of steps. First, as shown in FIG. 5A, an oxide film 2 is formed on a single-crystal silicon substrate 1, and then, as shown in FIG. 5B, a nitride film 6 is deposited by a CVD method. Next, as shown in FIG. 5C, the single-crystal silicon substrate 3 is bonded, and a heat treatment at about 1100 ° C. is performed. After this, FIG.
As shown in (d), the single-crystal silicon substrate 1 is polished to complete the process, leaving the SOI layer 5 having a desired thickness. This S
A tensile stress acts on the nitride film 6 in the buried insulating film layer of the OI substrate, which acts in a direction to eliminate the compressive stress of the oxide film 2, and thus has an effect of preventing the SOI substrate from warping in a convex shape.

【0005】[0005]

【発明が解決しようとする課題】上述した第1の従来例
では、SOI基板裏面の酸化膜4が反りの抑制を果たし
ているが、デバイス形成プロセスにおいて酸化膜エッチ
ングの工程が必ずあるため、この酸化膜4が除去されて
しまい反りが増大する、あるいは、裏面酸化膜が除去さ
れないようにその都度裏面を保護する工程が必要になる
といった問題点があった。
In the above-mentioned first conventional example, the oxide film 4 on the back surface of the SOI substrate suppresses the warpage. However, since the oxide film etching step is always included in the device forming process, this oxide film There is a problem that the film 4 is removed and warpage increases, or a step of protecting the back surface is required each time so that the back surface oxide film is not removed.

【0006】また、第2の従来例では、貼り合わせ界面
が単結晶シリコン(3)と窒化膜6とになるので、一般
的な単結晶シリコンと酸化膜の界面に比べて、ボイドが
発生しやすく量産性に乏しいという問題点があった。
In the second conventional example, since the bonding interface is the single crystal silicon (3) and the nitride film 6, voids are generated as compared with the general interface between the single crystal silicon and the oxide film. There was a problem that the mass production was poor.

【0007】本発明の目的は、これらの問題点を解決
し、基板の反りを低減した埋込絶縁膜層(酸化膜)をも
つSOI基板の製造方法を提供することにある。
An object of the present invention is to solve these problems and to provide a method for manufacturing an SOI substrate having a buried insulating film layer (oxide film) in which the warpage of the substrate is reduced.

【0008】[0008]

【課題を解決するための手段】本発明のSOI基板の製
造方法の構成は、第1の単結晶シリコン基板を酸化して
その表面に第1の酸化膜を形成する工程と、前記第1の
単結晶シリコン基板の一主面に前記第1の酸化膜を介し
て第2の単結晶シリコン基板の一主面を貼り合わせて1
枚の基板とする工程と、前記貼り合わせた基板の前記第
2の単結晶シリコン基板を他主面側に反り防止用の第2
の酸化膜を形成する工程と、前記第2の酸化膜を多結晶
シリコン膜で覆う工程と、前記貼り合わせた基板の前記
第1の単結晶シリコン基板の他主面側を研削・研磨し所
定の厚さのSOI層を形成する工程とを有することを特
徴とする。
According to the present invention, there is provided an SOI substrate manufacturing method comprising the steps of: oxidizing a first single crystal silicon substrate to form a first oxide film on a surface thereof; One main surface of the second single crystal silicon substrate is bonded to one main surface of the single crystal silicon substrate via the first oxide film to form one
Forming a single substrate, and bonding the second single-crystal silicon substrate of the bonded substrates to the other main surface side with a second
Forming the oxide film, covering the second oxide film with a polycrystalline silicon film, and grinding and polishing the other main surface side of the first single crystal silicon substrate of the bonded substrate to a predetermined thickness. Forming an SOI layer having a thickness of

【0009】本発明において、多結晶シリコン膜の代わ
りに、窒化膜または窒化膜と多結晶シリコン膜を用いて
第2の酸化膜を覆うことができ、又第1の単結晶シリコ
ン基板に第2の単結晶シリコン基板の一主面を貼り合わ
せた後、熱処理をしてその接合強度を上げることができ
る。
In the present invention, the second oxide film can be covered with a nitride film or a nitride film and a polycrystalline silicon film instead of the polycrystalline silicon film. After bonding one main surface of the single crystal silicon substrate, heat treatment can be performed to increase the bonding strength.

【0010】[0010]

【発明の実施の形態】本発明の実施の形態について図面
を参照して説明する。図1は本発明の第1の実施の形態
を示す製造工程順断面図である。まず、図1(a)に示
すように、単結晶シリコン基板1を熱酸化し酸化膜7を
形成する。この時、酸化膜7は後に貼り合わせ面となる
側だけに形成しても良いが、全面に形成されても構わな
い。また、この酸化膜7の厚さはデバイスの耐圧が高く
なるほど厚くすることが望ましく、例えば200V耐圧
のMOSFETを作り込む場合、0.5μm〜1μmに
する。
Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view showing a first embodiment of the present invention in the order of manufacturing steps. First, as shown in FIG. 1A, the single crystal silicon substrate 1 is thermally oxidized to form an oxide film 7. At this time, the oxide film 7 may be formed only on the side to be a bonding surface later, or may be formed on the entire surface. It is desirable that the thickness of the oxide film 7 is increased as the withstand voltage of the device is increased. For example, when a MOSFET with a withstand voltage of 200 V is formed, the thickness is set to 0.5 μm to 1 μm.

【0011】次に図1(b)に示すように、単結晶シリ
コン基板1と単結晶シリコン基板3を洗浄後常温で貼り
合わせる。この状態では接合界面は水素結合あるいは、
ファン・デル・ワールス力による弱い結合が保たれてい
るだけであるので、次に図1(c)に示すように熱処理
を行い接合を強固なものにする。この熱処理は、例えば
1100℃で2時間、酸化性雰囲気中で行うことによ
り、単結晶シリコン基板3は酸化膜8で覆われ、酸化膜
7もいくらか厚みを増し、結局基板全体を酸化膜7,8
で覆うことになる。この熱処理を窒素雰囲気中で行った
場合、単結晶シリコン基板3には酸化膜が形成されない
ので、CVD法により酸化膜を堆積させる方法もある。
裏面(単結晶シリコン基板3側の面)に形成された酸化
膜8は、SOI層を形成する研磨工程やデバイス形成プ
ロセスにおいての基板の反りを抑える働きをし、その厚
さは単結晶シリコン基板1側に形成した酸化膜7と同等
の厚さであることが望ましい。
Next, as shown in FIG. 1B, the single-crystal silicon substrate 1 and the single-crystal silicon substrate 3 are bonded at room temperature after cleaning. In this state, the bonding interface is hydrogen bonded or
Since only a weak bond due to Van der Waals force is maintained, a heat treatment is then performed as shown in FIG. 1 (c) to strengthen the bond. This heat treatment is performed, for example, at 1100 ° C. for 2 hours in an oxidizing atmosphere, so that the single crystal silicon substrate 3 is covered with the oxide film 8 and the oxide film 7 also has a somewhat increased thickness. 8
Will be covered. When this heat treatment is performed in a nitrogen atmosphere, an oxide film is not formed on the single-crystal silicon substrate 3, so that an oxide film may be deposited by a CVD method.
The oxide film 8 formed on the back surface (the surface on the side of the single crystal silicon substrate 3) functions to suppress the warpage of the substrate in the polishing step for forming the SOI layer and the device formation process. It is desirable that the thickness be equal to the thickness of the oxide film 7 formed on one side.

【0012】従って、次に図1(d)に示すように、酸
化膜8の保護膜として多結晶シリコン膜9をCVD法な
どにより堆積させる。この多結晶シリコン膜9はデバイ
ス形成プロセスでの酸化膜エッチング工程で裏面の酸化
膜8が除去されるのを防ぐためのものであり、厚さは
0.1〜0.5μm程度でよい。次に図1(e)に示す
ように、表面(単結晶シリコン基板1側の面)を研削・
研磨し、所望の厚さ、例えば5μm程度のSOI層5を
形成する。単結晶シリコン基板1に形成した酸化膜7
は、SOI層5の側面に残るが、この後SOI層5の周
辺部を1〜3mm程度の幅で研磨、あるいはエッチング
することにより、除去される。
Therefore, as shown in FIG. 1D, a polycrystalline silicon film 9 is deposited as a protective film for the oxide film 8 by a CVD method or the like. The polycrystalline silicon film 9 is for preventing the oxide film 8 on the back surface from being removed in the oxide film etching step in the device forming process, and may have a thickness of about 0.1 to 0.5 μm. Next, as shown in FIG. 1E, the surface (the surface on the side of the single crystal silicon substrate 1) is ground and
Polishing is performed to form an SOI layer 5 having a desired thickness, for example, about 5 μm. Oxide film 7 formed on single crystal silicon substrate 1
Remains on the side surface of the SOI layer 5, but is thereafter removed by polishing or etching the peripheral portion of the SOI layer 5 with a width of about 1 to 3 mm.

【0013】次に、本実施形態において、SOI基板の
裏面には埋込酸化膜7と同等厚さの酸化膜8が形成され
ており、基板の反りは矯正されている。この反り値は、
例えば埋込酸化膜7の厚さが1μmの場合、裏面酸化膜
8があれば10〜30μm程度であるが、裏面酸化膜8
がないと100μm程度に増大する。このSOI基板の
裏面には酸化膜を覆うように多結晶シリコン膜が形成さ
れているため、デバイス形成プロセスにおける酸化膜エ
ッチング工程でSOI基板裏面の酸化膜が除去されるの
を防ぐことができる。したがってSOI基板には大きな
反りを生じさせることなくデバイス形成プロセスを進め
ることができる。
Next, in this embodiment, an oxide film 8 having the same thickness as the buried oxide film 7 is formed on the back surface of the SOI substrate, and the warpage of the substrate is corrected. This warpage value is
For example, when the thickness of the buried oxide film 7 is 1 μm, the thickness is about 10 to 30 μm if the back oxide film 8 is provided.
If not present, it increases to about 100 μm. Since the polycrystalline silicon film is formed on the back surface of the SOI substrate so as to cover the oxide film, it is possible to prevent the oxide film on the back surface of the SOI substrate from being removed in the oxide film etching step in the device forming process. Therefore, the device formation process can be advanced without causing a large warp in the SOI substrate.

【0014】図2は本発明の第2の実施の形態を示す製
造工程順断面図である。図2(a)〜(c)は、第1の
実施形態と同様である。次に図2(d)にしめすように
酸化膜8の保護膜として窒化膜6をCVD法などにより
堆積させる。この窒化膜6はデバイス形成プロセスでの
酸化膜エッチング工程で裏面の酸化膜8が除去されるの
を防ぐためのものであり、厚さは0.1〜0.3μm程
度でよい。次に図2(e)に示す様に、表面(単結晶シ
リコン基板1側の面)を研削・研磨し、所望の厚さのS
OI層5を形成する。
FIG. 2 is a sectional view showing a second embodiment of the present invention in the order of manufacturing steps. 2A to 2C are the same as in the first embodiment. Next, as shown in FIG. 2D, a nitride film 6 is deposited as a protective film of the oxide film 8 by a CVD method or the like. The nitride film 6 is for preventing the oxide film 8 on the back surface from being removed in the oxide film etching step in the device forming process, and may have a thickness of about 0.1 to 0.3 μm. Next, as shown in FIG. 2E, the surface (the surface on the side of the single crystal silicon substrate 1) is ground and polished, and the S
An OI layer 5 is formed.

【0015】この実施形態において、SOI基板の裏面
には埋込酸化膜7と同等厚さの酸化膜8が形成されてお
り、基板の反りは矯正されている。加えて、このSOI
基板の裏面には酸化膜を覆うように窒化膜6が形成され
ているため、デバイス形成プロセスにおける酸化膜エッ
チング工程でSOI基板裏面の酸化膜が除去されるのを
防ぐことができる。従って、SOI基板には大きな反り
を生じさせることなくデバイス形成プロセスを進めるこ
とができる。
In this embodiment, an oxide film 8 having the same thickness as the buried oxide film 7 is formed on the back surface of the SOI substrate, and the warpage of the substrate is corrected. In addition, this SOI
Since the nitride film 6 is formed on the back surface of the substrate so as to cover the oxide film, it is possible to prevent the oxide film on the back surface of the SOI substrate from being removed in the oxide film etching step in the device formation process. Therefore, the device formation process can be advanced without causing a large warp in the SOI substrate.

【0016】図3は本発明の第3の実施の形態を示す製
造工程断面図である。図3(a)〜(c)は、第1の実
施と同様である。次に図3(d)に示すように酸化膜8
の保護膜として窒化膜6および多結晶シリコン膜9をC
VD法などにより堆積させる。この窒化膜6および多結
晶シリコン膜9をCVDなどにより堆積させる。この窒
化膜6および多結晶シリコン膜9はデバイス形成プロセ
スでの酸化膜エッチング工程で裏面の酸化膜8が除去さ
れるのを防ぐためのものであり、厚さはそれぞれ0.1
〜0.3μm程度、0.1〜0.5μm程度でよい。次
に図3(e)に示すように、表面(単結晶シリコン基板
1側の面)を研削・研磨し、所望の厚さのSOI層5を
形成する。
FIG. 3 is a sectional view showing a manufacturing process according to a third embodiment of the present invention. FIGS. 3A to 3C are the same as in the first embodiment. Next, as shown in FIG.
Nitride film 6 and polycrystalline silicon film 9 as protective films for C
It is deposited by a VD method or the like. The nitride film 6 and the polycrystalline silicon film 9 are deposited by CVD or the like. The nitride film 6 and the polycrystalline silicon film 9 are for preventing the oxide film 8 on the back surface from being removed in the oxide film etching step in the device forming process, and each has a thickness of 0.1.
It may be about 0.3 μm or about 0.1 μm to 0.5 μm. Next, as shown in FIG. 3E, the surface (the surface on the side of the single crystal silicon substrate 1) is ground and polished to form an SOI layer 5 having a desired thickness.

【0017】この実施の形態において、SOI基板の裏
面には埋込酸化膜7と同等厚さの酸化膜8が形成されて
おり、基板の反りは矯正されている。加えて、このSO
I基板の裏面には酸化膜8を覆うように窒化膜6および
多結晶シリコン膜9が形成されているため、デバイス形
成プロセスにおける酸化膜エッチング工程でSOI基板
裏面の酸化膜が除去されるのを防ぐことができる。した
がってSOI基板には大きな反りを生じさせることなく
デバイス形成プロセスを進めることができる。
In this embodiment, an oxide film 8 having the same thickness as the buried oxide film 7 is formed on the back surface of the SOI substrate, and the warpage of the substrate is corrected. In addition, this SO
Since the nitride film 6 and the polycrystalline silicon film 9 are formed on the back surface of the I substrate so as to cover the oxide film 8, it is necessary to prevent the oxide film on the back surface of the SOI substrate from being removed in the oxide film etching step in the device forming process. Can be prevented. Therefore, the device formation process can be advanced without causing a large warp in the SOI substrate.

【0018】上述した各実施形態では、SOI基板裏面
の酸化膜を保護する膜が異なるが、デバイス形成プロセ
スにおいて多結晶シリコン形成・多結晶シリコンエッチ
ングの後、酸化膜エッチングがないか極めて少ないよう
な場合、第1の実施の形態が望ましい。また、デバイス
形成プロセスにおいて窒化膜形成・窒化膜エッチングの
後、酸化膜エッチングがないか極めて少ないような場
合、第2の実施の形態が望ましい。さらに、多結晶シリ
コン形成・多結晶シリコンエッチングの後や窒化膜形成
・窒化膜エッチングの後、酸化膜エッチング工程がある
場合、窒化膜、多結晶シリコン膜を任意に重ね合わせる
第3の実施の形態が望ましい。
In each of the above-described embodiments, the film for protecting the oxide film on the back surface of the SOI substrate is different. However, after the formation of polycrystalline silicon and the etching of polycrystalline silicon in the device forming process, there is no or very little oxide film etching. In this case, the first embodiment is desirable. Further, in the case where there is no or very little oxide film etching after the formation of the nitride film and the etching of the nitride film in the device formation process, the second embodiment is desirable. Further, in the case where there is an oxide film etching step after polycrystalline silicon formation / polycrystalline silicon etching or after nitride film formation / nitride film etching, a third embodiment in which a nitride film and a polycrystalline silicon film are arbitrarily overlapped is provided. Is desirable.

【0019】[0019]

【発明の効果】以上説明したように、本発明の構成によ
れば、SOI基板の反りを矯正する酸化膜およびその酸
化膜が除去されることを防ぐ保護膜(多結晶シリコン
膜、窒化膜など)が裏面に形成されているため、デバイ
ス形成プロセスにおいて、SOI基板の反りが大きくな
ることはなく、安定して工程を進めることができるとと
もに、SOI基板の平坦性を保つことができるため製造
歩留まりも向上させることができる。
As described above, according to the structure of the present invention, an oxide film for correcting the warpage of an SOI substrate and a protective film (polycrystalline silicon film, nitride film, etc.) for preventing the oxide film from being removed. ) Is formed on the back surface, so that the warpage of the SOI substrate does not increase in the device forming process, the process can be performed stably, and the flatness of the SOI substrate can be maintained. Can also be improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1の実施の形態を示す製造工程順断
面図である。
FIG. 1 is a cross-sectional view illustrating a first embodiment of the present invention in order of a manufacturing process.

【図2】本発明の第2の実施の形態を示す製造工程順断
面図である。
FIG. 2 is a sectional view illustrating a second embodiment of the present invention in the order of manufacturing steps.

【図3】本発明の第3の実施の形態を示す製造工程順断
面図である。
FIG. 3 is a sectional view illustrating a third embodiment of the present invention in the order of manufacturing steps.

【図4】第1の従来例のSOI基板の製造工程順断面図
である。
FIG. 4 is a sectional view of a first conventional example of an SOI substrate in a manufacturing process order.

【図5】第2の従来例のSOI基板の製造工程順断面図
である。
FIG. 5 is a sectional view in order of a manufacturing process of a second conventional SOI substrate.

【符号の説明】[Explanation of symbols]

1,3 単結晶シリコン基板 2,4 酸化膜 5 SOI層 6 窒化膜 9 多結晶シリコン膜 1,3 single crystal silicon substrate 2,4 oxide film 5 SOI layer 6 nitride film 9 polycrystalline silicon film

Claims (5)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 第1の単結晶シリコン基板を酸化してそ
の表面に第1の酸化膜を形成する工程と、前記第1の単
結晶シリコン基板の一主面に前記第1の酸化膜を介して
第2の単結晶シリコン基板の一主面を貼り合わせて1枚
の基板とする工程と、前記貼り合わせた基板の前記第2
の単結晶シリコン基板の他主面側に反り防止用の第2の
酸化膜を形成する工程と、前記第2の酸化膜を多結晶シ
リコン膜で覆う工程と、前記貼り合わせた基板の前記第
1の単結晶シリコン基板の他主面側を研削・研磨し所定
の厚さのSOI層を形成する工程とを有することを特徴
とするSOI基板の製造方法。
A step of oxidizing a first single crystal silicon substrate to form a first oxide film on a surface thereof; and forming the first oxide film on one main surface of the first single crystal silicon substrate. Bonding one main surface of a second single-crystal silicon substrate to form a single substrate, and
Forming a second oxide film for preventing warpage on the other main surface side of the single crystal silicon substrate, covering the second oxide film with a polycrystalline silicon film, and forming the second oxide film on the other main surface side of the single crystal silicon substrate. Grinding and polishing the other main surface side of the single-crystal silicon substrate to form an SOI layer with a predetermined thickness.
【請求項2】 多結晶シリコン膜の代わりに、窒化膜を
用いて第2の酸化膜を覆う請求項1記載のSOI基板の
製造方法。
2. The method according to claim 1, wherein the second oxide film is covered with a nitride film instead of the polycrystalline silicon film.
【請求項3】 多結晶シリコン膜の代わりに、窒化膜お
よび多結晶シリコン膜を用いて第2の酸化膜を覆う請求
項1記載のSOI基板の製造方法。
3. The method according to claim 1, wherein the second oxide film is covered with a nitride film and a polycrystalline silicon film instead of the polycrystalline silicon film.
【請求項4】 第2の酸化膜を覆う窒化膜の上に多結晶
シリコン膜を形成する請求項2記載のSOI基板の製造
方法。
4. The method according to claim 2, wherein a polycrystalline silicon film is formed on the nitride film covering the second oxide film.
【請求項5】 第1の単結晶シリコン基板に第2の単結
晶シリコン基板の一主面を貼り合わせた後、熱処理をし
てその接合強度を上げる工程を含む請求項1乃至4記載
のSOI基板の製造方法。
5. The SOI according to claim 1, further comprising a step of bonding one main surface of the second single-crystal silicon substrate to the first single-crystal silicon substrate and then performing a heat treatment to increase the bonding strength. Substrate manufacturing method.
JP25223197A 1997-09-17 1997-09-17 Method for manufacturing SOI substrate Expired - Fee Related JP2927280B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25223197A JP2927280B2 (en) 1997-09-17 1997-09-17 Method for manufacturing SOI substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25223197A JP2927280B2 (en) 1997-09-17 1997-09-17 Method for manufacturing SOI substrate

Publications (2)

Publication Number Publication Date
JPH1197320A JPH1197320A (en) 1999-04-09
JP2927280B2 true JP2927280B2 (en) 1999-07-28

Family

ID=17234349

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25223197A Expired - Fee Related JP2927280B2 (en) 1997-09-17 1997-09-17 Method for manufacturing SOI substrate

Country Status (1)

Country Link
JP (1) JP2927280B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4915107B2 (en) * 2006-02-28 2012-04-11 ソニー株式会社 Solid-state imaging device and method for manufacturing solid-state imaging device
JP5817441B2 (en) * 2011-11-02 2015-11-18 トヨタ自動車株式会社 SOI wafer
JP6186984B2 (en) * 2013-07-25 2017-08-30 三菱電機株式会社 Manufacturing method of semiconductor device

Also Published As

Publication number Publication date
JPH1197320A (en) 1999-04-09

Similar Documents

Publication Publication Date Title
JP3033412B2 (en) Method for manufacturing semiconductor device
JPH01315159A (en) Dielectric-isolation semiconductor substrate and its manufacture
TWI474397B (en) Method for forming silicon oxide film of SOI wafer
JPH07118505B2 (en) Method for manufacturing dielectric isolation substrate
US6964880B2 (en) Methods for the control of flatness and electron mobility of diamond coated silicon and structures formed thereby
CN101675499B (en) Soi substrate manufacturing method and soi substrate
JPH098124A (en) Insulation separation substrate and its manufacture
JP2927280B2 (en) Method for manufacturing SOI substrate
JP3480480B2 (en) Method for manufacturing SOI substrate
JPH06275525A (en) Soi substrate and manufacture thereof
JP3048754B2 (en) Semiconductor substrate
JP2008166646A (en) Method of manufacturing semiconductor substrate
JP2961522B2 (en) Substrate for semiconductor electronic device and method of manufacturing the same
JP2000030993A (en) Manufacture of soi wafer and soi wafer
JP2552936B2 (en) Dielectric isolation substrate and semiconductor integrated circuit device using the same
JPH0964319A (en) Soi substrate and its manufacture
JP2754295B2 (en) Semiconductor substrate
JP2766417B2 (en) Manufacturing method of bonded dielectric separation wafer
JP2609198B2 (en) Semiconductor substrate manufacturing method
JPH01302740A (en) Dielectric isolation semiconductor substrate
JPH04199632A (en) Soi wafer and manufacture thereof
JP3846657B2 (en) Bonded substrate and manufacturing method thereof
JP3518083B2 (en) Substrate manufacturing method
JPH11345954A (en) Semiconductor substrate and its manufacture
JPH0774328A (en) Soi substrate

Legal Events

Date Code Title Description
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 19990413

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090514

Year of fee payment: 10

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090514

Year of fee payment: 10

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100514

Year of fee payment: 11

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100514

Year of fee payment: 11

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100514

Year of fee payment: 11

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100514

Year of fee payment: 11

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110514

Year of fee payment: 12

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120514

Year of fee payment: 13

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120514

Year of fee payment: 13

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130514

Year of fee payment: 14

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140514

Year of fee payment: 15

LAPS Cancellation because of no payment of annual fees