JPH02219252A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPH02219252A
JPH02219252A JP4124189A JP4124189A JPH02219252A JP H02219252 A JPH02219252 A JP H02219252A JP 4124189 A JP4124189 A JP 4124189A JP 4124189 A JP4124189 A JP 4124189A JP H02219252 A JPH02219252 A JP H02219252A
Authority
JP
Japan
Prior art keywords
film
semiconductor substrate
insulating film
substrate
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4124189A
Other languages
Japanese (ja)
Inventor
Matsuo Takaoka
高岡 松雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP4124189A priority Critical patent/JPH02219252A/en
Publication of JPH02219252A publication Critical patent/JPH02219252A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To avoid the oxidation of a part position, and prevent the generation of defects by forming a third semiconductor oxide film on a first semiconductor substrate via a non-oxidizing film, at the time of forming an element isolation region. CONSTITUTION:On a first semiconductor substrate 1, a non-oxidizing film 2 is formed; a first insulating film 3 is formed thereon; a second insulating film 5 is formed on a second semiconductor substrate 4; the first insulating film 3 on the first semiconductor substrate 1 and the second insulating film 6 on the second semiconductor substrate 4 are stuck to each other, thereby forming an SOI substrate. Successively, the second semiconductor substrate 4 is polished up to a necessary thickness, or the first semiconductor substrate 1 is polished up to a necessary thickness. Etching is performed so as to penetrate the second semiconductor substrate 4 polished up to a necessary thickness, the second insulating film 6, and a first insulating film 3, or to use the non- oxidizing film 2 as a stopper for the first semiconductor substrate 1. Thereby, a trench for forming an element isolation region, on the bottom surface of which the non- oxidizing film is exposed, is formed. Next, by oxidation, a third insulating film 7 is formed on the inner wall of the trench. Hence crystal defect can be reduced.

Description

【発明の詳細な説明】 〔概要〕 本発明は半導体酸化膜のような絶縁層を介して。[Detailed description of the invention] 〔overview〕 The present invention uses an insulating layer such as a semiconductor oxide film.

半導体基板同士を接着することにより、絶縁層上に素子
を形成する。所謂、貼り合わせSol技術における半導
体装置の製造方法に関し。
By bonding semiconductor substrates together, elements are formed on the insulating layer. Regarding a method for manufacturing a semiconductor device using the so-called bonding Sol technology.

貼り合わせSOI基板を用いた場合の素子分離領域形成
に起因する結晶欠陥の低減を目的とし。
The purpose is to reduce crystal defects caused by the formation of element isolation regions when bonded SOI substrates are used.

第一の半導体基板上に、順次、非酸化性膜及び第一の絶
縁膜を形成する工程と、第二の半導体基板上に、第二の
絶縁膜を形成する工程と。
A step of sequentially forming a non-oxidizing film and a first insulating film on a first semiconductor substrate, and a step of forming a second insulating film on a second semiconductor substrate.

該第二の半導体基板を該第二の絶縁膜並びに該第一の絶
縁膜を介して、該第一の半導体基板上に接着する工程と
、該第一の半導体基板または第二の半導体基板の接着面
とは反対の面を一定量エッチングする工程と。
bonding the second semiconductor substrate onto the first semiconductor substrate via the second insulating film and the first insulating film; A process of etching a certain amount of the surface opposite to the adhesive surface.

一定量エッチングされた該第一の半導体基板または第二
の半導体基板に、底面に非酸化性膜が露出する素子間分
離用の溝を形成し5次いで、酸化を行って溝内に第三の
絶縁膜を形成する工程とを有することにより構成する。
A groove for isolation between elements is formed in the first semiconductor substrate or the second semiconductor substrate that has been etched by a certain amount, and the non-oxidizing film is exposed on the bottom surface. and a step of forming an insulating film.

〔産業上の利用分野〕[Industrial application field]

本発明は半導体酸化膜のような絶縁層を介して半導体基
板同士を接着することにより、絶縁層上に素子を形成す
る。所謂、貼り合わせSOI技術における半導体装置の
製造方法、特に、SOI基板を用いた場合の素子分離領
域形成に起因する結晶欠陥の低減化に関する。
In the present invention, elements are formed on the insulating layer by bonding semiconductor substrates together via an insulating layer such as a semiconductor oxide film. The present invention relates to a method for manufacturing a semiconductor device using the so-called bonded SOI technology, and in particular to reducing crystal defects caused by the formation of element isolation regions when using an SOI substrate.

半導体集積回路装置も益々、高集積化、高速化が要求さ
れている。
Semiconductor integrated circuit devices are also required to be more highly integrated and faster.

このため、Sol基板を用いた装置の開発も微細化とと
もに、装置の性能の向上が必要となっている。
For this reason, the development of devices using Sol substrates requires not only miniaturization but also improvements in device performance.

〔従来の技術〕[Conventional technology]

第3図に従来方式のSol基板上の素子分離方法につい
て、模式断面図で示す。
FIG. 3 shows a schematic cross-sectional view of a conventional method for separating elements on a Sol substrate.

図において、27は第一のSi基板、28は第一の34
0g膜、29は第二のSi基板、30は第二の340g
膜。
In the figure, 27 is the first Si substrate, 28 is the first 34
0g film, 29 is the second Si substrate, 30 is the second 340g
film.

31は第一のエピタキシャル層、32は第三のSiO□
膜33は埋没コレクタ層、34は第二のエピタキシャル
層、35は第四のSiO□膜、36はU溝、37は第五
のSiO□膜である。
31 is the first epitaxial layer, 32 is the third SiO□
The film 33 is a buried collector layer, 34 is a second epitaxial layer, 35 is a fourth SiO□ film, 36 is a U groove, and 37 is a fifth SiO□ film.

第3図(a)に示すように、第一のSi基板27を熱酸
化し5表面に第一のSiO□膜28膜形8する。
As shown in FIG. 3(a), a first Si substrate 27 is thermally oxidized to form a first SiO□ film 28 on its surface.

第3図(b)に示すように、もう一方の、第二のSi基
板29を熱酸化し1表面に第二の5i02膜30を成長
し、パターニングする。
As shown in FIG. 3(b), the other second Si substrate 29 is thermally oxidized to grow a second 5i02 film 30 on one surface and patterned.

その上にSi単結晶の第一のエピタキシャル層31を形
成した後、硝酸で第二のSi基板29を表面処理し、薄
い第三のSiO□膜32膜形2する。
After forming a first epitaxial layer 31 of Si single crystal thereon, the second Si substrate 29 is surface-treated with nitric acid to form a thin third SiO□ film 32.

次に、第3図(C)に示すように、第一のSi基板27
と第二のSi基板29を、それぞれ表面の第一の酸化膜
28と第二のSiO□膜30.並びに、第三の5iO7
膜32を介在して、貼り合わせる。
Next, as shown in FIG. 3(C), the first Si substrate 27
and second Si substrate 29, respectively, with first oxide film 28 and second SiO□ film 30. and a third 5iO7
They are bonded together with a film 32 interposed therebetween.

貼り合わせた基板は、第3図(d)に示すように、第二
のSiO□膜30をストッパーとして第二のSi基板2
9を研磨して除去する。
As shown in FIG. 3(d), the bonded substrates are attached to the second Si substrate 2 using the second SiO□ film 30 as a stopper.
9 is polished and removed.

その結果第一のSi基板27の最上層には絶縁層の上に
薄いSi単結晶の第一のエピタキシャル層31が形成さ
れた形となる。
As a result, the first epitaxial layer 31 of thin single crystal Si is formed on the insulating layer in the uppermost layer of the first Si substrate 27.

次に、第3図(e)に示すように、第一のエピタキシャ
ル層31に、n゛拡散行い埋没コレクタ層33を形成し
た後、全面にn型の第二のエピタキシャル層34を成長
する。
Next, as shown in FIG. 3(e), a buried collector layer 33 is formed by n diffusion into the first epitaxial layer 31, and then an n-type second epitaxial layer 34 is grown on the entire surface.

引続き、第3図(f)に示すように、成長した第二のエ
ピタキシャル層34の上に、 CVD法により第四のS
iO□膜35を成長する。
Subsequently, as shown in FIG. 3(f), a fourth S layer is deposited on the grown second epitaxial layer 34 by the CVD method.
An iO□ film 35 is grown.

次に、第3図(g)に示すように、第四の5in2膜3
5をパターニングした後、第一のSiO□膜28膜形8
ッパーとして素子分離領域形成用のU溝36を形成する
Next, as shown in FIG. 3(g), a fourth 5in2 film 3 is formed.
After patterning 5, the first SiO□ film 28 film shape 8
A U-groove 36 for forming an element isolation region is formed as a capper.

続いて、第3図(h)に示すように、U溝36の内壁に
熱酸化により第五のSiO□膜37膜形7する。
Subsequently, as shown in FIG. 3(h), a fifth SiO□ film 37 is formed on the inner wall of the U-groove 36 by thermal oxidation.

この際、酸化熱処理により、埋没コレクタ層33更に、
第二のエピタキシャル層34のSi単結晶内に。
At this time, by oxidation heat treatment, the buried collector layer 33 and
In the Si single crystal of the second epitaxial layer 34.

結晶欠陥が発生する。Crystal defects occur.

そして素子形成領域である第二のエピタキシャル層34
に、バイポーラ・トランジスタを形成した場合に特性の
劣化を引き起こす。
And a second epitaxial layer 34 which is an element formation region.
Moreover, when a bipolar transistor is formed, the characteristics deteriorate.

上記のように、従来の貼り付けSol基板では絶縁層に
SiO2膜を利用していた。
As mentioned above, the conventional bonded Sol substrate uses a SiO2 film as an insulating layer.

このため、その後の素子分離領域形成時の熱酸化により
、Si単結晶にストレスがかかり、素子形成領域に結晶
欠陥が発生していた。
Therefore, stress was applied to the Si single crystal due to thermal oxidation during subsequent formation of the element isolation region, and crystal defects were generated in the element formation region.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従って、素子を形成しても、結晶欠陥の発生により、バ
イポーラ・トランジスタ等の特性が劣化し、信頼性が失
われる結果となっている。
Therefore, even if an element is formed, the characteristics of bipolar transistors and the like deteriorate due to the occurrence of crystal defects, resulting in a loss of reliability.

本発明は、貼り付けSol基板を用いて、素子分離を行
う場合の、結晶欠陥の低減を目的としている。
The present invention aims to reduce crystal defects when performing element isolation using a bonded Sol substrate.

〔課題を解決するための手段〕[Means to solve the problem]

第1図は本発明の原理説明図である。 FIG. 1 is a diagram explaining the principle of the present invention.

図において、1は第一の半導体基板、2は非酸化性膜、
3は第一の絶縁膜、4は第二の半導体基板、5は第二の
絶縁膜、6は素子分離領域形成用の溝、7は第三の絶縁
膜である。
In the figure, 1 is a first semiconductor substrate, 2 is a non-oxidizing film,
3 is a first insulating film, 4 is a second semiconductor substrate, 5 is a second insulating film, 6 is a groove for forming an element isolation region, and 7 is a third insulating film.

第1図(a)に示すように、第一の半導体基板1上に非
酸化性膜2を形成し、その上に第一の絶縁膜3を形成す
る。
As shown in FIG. 1(a), a non-oxidizing film 2 is formed on a first semiconductor substrate 1, and a first insulating film 3 is formed thereon.

又、第1図(b)に示すように、第二の半導体基板4上
に第二の絶縁膜5を形成する。
Further, as shown in FIG. 1(b), a second insulating film 5 is formed on the second semiconductor substrate 4.

次に、第1図(c)に示すように、第一の半導体基板1
上の第一の絶縁膜3と、第二の半導体基板4上の第二の
絶縁膜5を貼り合わせてSol基板とする。
Next, as shown in FIG. 1(c), the first semiconductor substrate 1
The first insulating film 3 on the top and the second insulating film 5 on the second semiconductor substrate 4 are bonded together to form a Sol substrate.

続いて、第1図(d)に示すように、第二の半導体基板
4を必要な厚さ迄研磨するか、又は、第一の半導体基板
1を必要な厚さまで研磨する。
Subsequently, as shown in FIG. 1(d), the second semiconductor substrate 4 is polished to a required thickness, or the first semiconductor substrate 1 is polished to a required thickness.

必要な厚さまで研磨された第二の半導体基板4と第二の
絶縁膜5及び第一の絶縁膜3を通して或いは、第一の半
導体基板lに非酸化性膜2をストッパーとして、エツチ
ングにより底面に非酸化性膜が露出する素子分離領域形
成用の溝6を形成し 次いで、酸化を行って、溝の内壁
に第三の絶縁膜7を形成する。
The bottom surface is etched through the second semiconductor substrate 4 polished to a required thickness, the second insulating film 5, and the first insulating film 3, or the first semiconductor substrate 1 is etched using the non-oxidizing film 2 as a stopper. A trench 6 for forming an element isolation region in which the non-oxidizing film is exposed is formed, and then oxidation is performed to form a third insulating film 7 on the inner wall of the trench.

〔作用〕[Effect]

本発明では、第1119で示したように、素子分離領域
形成の際に、第一の半導体基板X上に非酸化性膜2を介
して第三の半導体酸化膜7が形成されているため、その
部位は酸化されることが無く。
In the present invention, as shown in No. 1119, the third semiconductor oxide film 7 is formed on the first semiconductor substrate X via the non-oxidizing film 2 when forming the element isolation region. That part will not be oxidized.

従って欠陥の発生が生じない。Therefore, no defects occur.

〔実施例〕〔Example〕

本発明の二つの実施例の工程順模式断面図を第2図に示
す。
FIG. 2 shows schematic cross-sectional views of two embodiments of the present invention in order of steps.

図において、8は第一のSi基板、9は第一の5iOz
膜、10はSi3N4膜、11は第二のSiO□膜、1
2は第二のSi基板、13は第三の5i02膜、14は
第一のエピタキシャル層、15は第四の5i(h膜、1
6は埋没コレクタ層、17は第二のエピタキシャル層、
18は第五のSi0g膜、19はU溝、20は第六のS
iO□膜、21はポリSi、 22は第七のSiO□膜
、23はAn電極である。
In the figure, 8 is the first Si substrate, 9 is the first 5iOz
10 is a Si3N4 film, 11 is a second SiO□ film, 1
2 is the second Si substrate, 13 is the third 5i02 film, 14 is the first epitaxial layer, 15 is the fourth 5i(h film, 1
6 is a buried collector layer, 17 is a second epitaxial layer,
18 is the fifth Si0g film, 19 is the U groove, 20 is the sixth S
An iO□ film, 21 is poly-Si, 22 is a seventh SiO□ film, and 23 is an An electrode.

二つの実施例とも、第一、第二のSi基板としてp形<
100 >方位、比抵抗10Ωcmの鏡面研磨したSi
ウェハーを用いる。
In both examples, the first and second Si substrates are p-type <
100 > orientation, mirror-polished Si with resistivity 10Ωcm
Uses wafers.

第一の実施例は、先ず、第2図(a)に示すように、第
一のSi基板8を1,000 ”Cで熱酸化し、1μの
厚さに第一のSiO□膜9を形成し、続いてCV[l法
により、 S!3N4膜10を800°Cで300人の
厚さに堆積し、その上に引続きCVD法により800°
Cで100人の厚さに第二の5i02膜11を形成する
In the first embodiment, as shown in FIG. 2(a), first, a first Si substrate 8 is thermally oxidized at 1,000''C, and a first SiO□ film 9 is formed to a thickness of 1μ. Then, by the CVD method, an S!
A second 5i02 film 11 is formed to a thickness of 100 mm using C.

もう一方の第二のSi基板12を、第2図(b)に示す
ように、 1,000°Cで熱酸化し、 5,000人
の厚さに第三の5iO7膜13を形成した後、パターニ
ングする。その上にp型で比抵抗が100cmのSiの
第一のエピタキシャル層14を5 、000人の厚さに
成長した後、硝酸で第二のSi基′Fi、12を表面処
理し、薄い第四のStO□膜15を表面に形成する。
As shown in FIG. 2(b), the other second Si substrate 12 was thermally oxidized at 1,000°C to form a third 5iO7 film 13 to a thickness of 5,000 mm. , patterning. After growing a first epitaxial layer 14 of p-type Si with a resistivity of 100 cm to a thickness of 5,000 cm, the second Si base 12 is surface-treated with nitric acid, and a thin epitaxial layer 14 is grown thereon. A fourth StO□ film 15 is formed on the surface.

次に、第2図(C)に示すように、第一のSi基板8上
の第二のSiO□膜11と第二のSi基板12上の第四
のSiO□膜15膜間5い合わせて接触し、軽く圧力を
かけて、窒素ガス中において、 1,200°Cで30
分間加熱して貼り合わせる。
Next, as shown in FIG. 2(C), the second SiO□ film 11 on the first Si substrate 8 and the fourth SiO□ film 15 on the second Si substrate 12 are aligned. 1,200°C for 30 minutes in a nitrogen gas atmosphere under slight pressure.
Heat for a minute and stick together.

続いて、第2図(d)に示すように、貼り合わせた基板
は第三のSiO□膜13をストッパーとし、第二のSi
基Fi12を研磨して完全に除去する。
Subsequently, as shown in FIG. 2(d), the bonded substrates are covered with a second SiO film 13 using the third SiO□ film 13 as a stopper.
The base Fi12 is completely removed by polishing.

その結果第一のSi基板8の最上層には絶縁層の上に薄
いSi単結晶の第一のエピタキシャル層14が形成され
た形となる。
As a result, the topmost layer of the first Si substrate 8 has a thin first epitaxial layer 14 of Si single crystal formed on the insulating layer.

更に、第2図(e)に示すように、この第一のエピタキ
シャル層14に1 、250°Cでアンチモン(Sb)
のn+全面拡散を行って、埋没コレクタ層16を形成す
る。
Furthermore, as shown in FIG. 2(e), this first epitaxial layer 14 is coated with antimony (Sb) at 1,250°C.
A buried collector layer 16 is formed by performing n+ diffusion over the entire surface.

続いて、埋没コレクタ層16の表面に、n型の第一のエ
ピタキシャル層17を1050°Cで5分間の加熱処理
で、1μの厚さに成長させる。
Subsequently, an n-type first epitaxial layer 17 is grown on the surface of the buried collector layer 16 to a thickness of 1 μm by heat treatment at 1050° C. for 5 minutes.

続いて、第2図(f)に示すように、成長した第二のエ
ピタキシャル層17にCVD法により800’Cで第五
の5iQz膜18を3,000人の厚さに成長する。
Subsequently, as shown in FIG. 2(f), a fifth 5iQz film 18 is grown to a thickness of 3,000 wafers at 800'C by CVD on the grown second epitaxial layer 17.

次に、 Si、lNa膜10をストッパーとして異方性
エツチングにより素子分離領域にU溝19を形成し続い
て、熱酸化により1 、000°Cで1時間処理して3
,000人の厚さに第六のSiO□膜20をU溝19の
内壁に形成する。
Next, a U-groove 19 is formed in the element isolation region by anisotropic etching using the Si, INa film 10 as a stopper, followed by thermal oxidation at 1,000°C for 1 hour.
A sixth SiO□ film 20 is formed on the inner wall of the U-groove 19 to a thickness of 1,000 mm.

次に、第2図(g)に示すように、ポリ5i21を80
0°CでU溝19内に成長させ、溝を埋める。
Next, as shown in FIG. 2(g), poly 5i21 is
It is grown in the U groove 19 at 0°C to fill the groove.

その後3研磨によって溝以外に堆積したポリSiを除去
する。
Thereafter, poly-Si deposited outside the grooves is removed by three polishing steps.

続いて、 1000°Cで1時間の熱酸化を行い、第七
の5in2膜22を表面に3,000人の厚さに成長す
る。
Subsequently, thermal oxidation is performed at 1000°C for 1 hour to grow a seventh 5in2 film 22 on the surface to a thickness of 3000mm.

この後、第一のSi基板8の第二のエピタキシャル層1
7内に通常の工程で、ヘース領域、エミックー領域の形
成を行い、 へ!電極23をパターニングして素子を形
成する。
After this, the second epitaxial layer 1 of the first Si substrate 8 is
In 7, form the Hess region and Emic region using the normal process, and then proceed to! The electrode 23 is patterned to form an element.

第二の実施例は、第2図(e)で示された。埋没コレク
タ層16並びに第二のエピタキシャル層17の形成迄は
、第一の実施例と同一工程で行われる。
A second embodiment is shown in FIG. 2(e). The steps up to the formation of the buried collector layer 16 and the second epitaxial layer 17 are performed in the same steps as in the first embodiment.

それから、第2図(h)に示すように、第二のエピタキ
シャル層17の上に、 CVO法により、800°Cで
 第二の5tJa膜24を3,000人の厚さに形成後
、パターニングする。
Then, as shown in FIG. 2(h), a second 5tJa film 24 is formed on the second epitaxial layer 17 at 800° C. to a thickness of 3,000 yen by CVO method, and then patterned. do.

続いて、 5iJ411i24を酸化マスクとして用い
3.5μの酸化を行う。その結果、素子分離のための第
五のSiO□膜25膜形5される。
Subsequently, 3.5μ oxidation is performed using 5iJ411i24 as an oxidation mask. As a result, a fifth SiO□ film 25 is formed for element isolation.

引続き、第2図(i)に示すように、第一の実施例と同
様に、第二のエピタキシャル層17内に通常の工程で、
ベース領域、エミッター領域の形成を行い、 Al電極
26をパターニングして素子を形成する。
Subsequently, as shown in FIG. 2(i), similar to the first embodiment, in the second epitaxial layer 17, by a normal process,
A base region and an emitter region are formed, and the Al electrode 26 is patterned to form a device.

〔発明の効果〕〔Effect of the invention〕

上記のように9本発明によれば、素子分離酸化の際の体
積膨張によるストレスが、主に横方向の影響のみであり
、底面からのストレスがほぼ無視できるため、結晶欠陥
の発生が低減できる。
As described above, according to the present invention, the stress due to volume expansion during element isolation oxidation is mainly influenced only in the lateral direction, and the stress from the bottom surface can be almost ignored, so the occurrence of crystal defects can be reduced. .

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の原理説明図。 第2図は本発明の実施例の工程順模式断面図。 第3図は従来例の説明図 である。 図において。 1は第一の半導体基板、2は非酸化性膜3は第一の絶縁
膜、   4は第二の半導体基板5は第二の絶縁膜、 
  6は溝。 7は第三の絶縁膜、   8は第一のSi基板。 9は第一のSiO□膜、10はSi3N4膜11は第二
のSiO□膜、12は第二のSi基板13は第三のSi
O□膜 14は第一のエピタキシャル層。 15は第四の5iO7膜、16は埋没コレクタ層。 17は第二のエピタキシャル層。 18は第五のSiO□膜、19はU溝 20は第六のSiO□膜、21はポリSi。 22は第七のSiO□膜、23はへl電極24は第二の
5iJn膜、25は第五の5iO7膜。 26はへ!電極 ℃
FIG. 1 is a diagram explaining the principle of the present invention. FIG. 2 is a schematic cross-sectional view of the steps in an embodiment of the present invention. FIG. 3 is an explanatory diagram of a conventional example. In fig. 1 is a first semiconductor substrate, 2 is a non-oxidizing film 3 is a first insulating film, 4 is a second semiconductor substrate 5 is a second insulating film,
6 is the groove. 7 is a third insulating film, and 8 is a first Si substrate. 9 is the first SiO□ film, 10 is the Si3N4 film 11 is the second SiO□ film, 12 is the second Si substrate 13 is the third SiO□ film, and 12 is the second SiO□ film.
The O□ film 14 is the first epitaxial layer. 15 is a fourth 5iO7 film, and 16 is a buried collector layer. 17 is a second epitaxial layer. 18 is the fifth SiO□ film, 19 is the U-groove 20 is the sixth SiO□ film, and 21 is poly-Si. 22 is the seventh SiO□ film, 23 is the electrode 24 is the second 5iJn film, and 25 is the fifth 5iO7 film. 26 ha! electrode ℃

Claims (1)

【特許請求の範囲】 第一の半導体基板(1)上に、順次、非酸化性膜(2)
及び第一の絶縁膜(3)を形成する工程と、第二の半導
体基板(4)上に、第二の絶縁膜(5)を形成する工程
と、 該第二の半導体基板(4)を該第二の絶縁膜(5)並び
に該第一の絶縁膜(3)を介して、該第一の半導体基板
上(1)に接着する工程と、 該第一の半導体基板(1)または第二の半導体基板(4
)の接着面とは反対の面を一定量エッチングする工程と
、 一定量エッチングされた該第一の半導体基板(1)また
は第二の半導体基板(4)に、底面に非酸化性膜(2)
が露出する素子間分離用の溝(6)を形成し、次いで酸
化を行って、溝(6)内に第三の絶縁膜(7)を形成す
る工程とを有することを特徴とする半導体装置の製造方
法。
[Claims] A non-oxidizing film (2) is sequentially formed on the first semiconductor substrate (1).
and a step of forming a first insulating film (3), and a step of forming a second insulating film (5) on the second semiconductor substrate (4), and a step of forming the second insulating film (5) on the second semiconductor substrate (4). a step of adhering onto the first semiconductor substrate (1) via the second insulating film (5) and the first insulating film (3); Second semiconductor substrate (4
) of the first semiconductor substrate (1) or the second semiconductor substrate (4) that has been etched by a certain amount, a non-oxidizing film (2 )
A semiconductor device comprising the steps of: forming a trench (6) for isolation between elements in which is exposed; and then performing oxidation to form a third insulating film (7) in the trench (6). manufacturing method.
JP4124189A 1989-02-20 1989-02-20 Manufacture of semiconductor device Pending JPH02219252A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4124189A JPH02219252A (en) 1989-02-20 1989-02-20 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4124189A JPH02219252A (en) 1989-02-20 1989-02-20 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH02219252A true JPH02219252A (en) 1990-08-31

Family

ID=12602938

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4124189A Pending JPH02219252A (en) 1989-02-20 1989-02-20 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH02219252A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2691837A1 (en) * 1992-05-28 1993-12-03 Fujitsu Ltd Semiconductor device on the self type substrate and its manufacturing process.
JPH0613593A (en) * 1992-06-25 1994-01-21 Nec Corp Semiconductor substrate
JPH0774240A (en) * 1993-06-15 1995-03-17 Nec Corp Semiconductor device
US6242320B1 (en) 1998-12-17 2001-06-05 Hyundai Electronics Industries Co., Ltd. Method for fabricating SOI wafer
US6580128B2 (en) * 2000-01-07 2003-06-17 Sony Corporation Semiconductor substrate, semiconductor device, and processes of production of same
JP2006019424A (en) * 2004-06-30 2006-01-19 Nec Electronics Corp Soi substrate, manufacturing method thereof, and semiconductor device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2691837A1 (en) * 1992-05-28 1993-12-03 Fujitsu Ltd Semiconductor device on the self type substrate and its manufacturing process.
US5705425A (en) * 1992-05-28 1998-01-06 Fujitsu Limited Process for manufacturing semiconductor devices separated by an air-bridge
JPH0613593A (en) * 1992-06-25 1994-01-21 Nec Corp Semiconductor substrate
JPH0774240A (en) * 1993-06-15 1995-03-17 Nec Corp Semiconductor device
US6242320B1 (en) 1998-12-17 2001-06-05 Hyundai Electronics Industries Co., Ltd. Method for fabricating SOI wafer
US6580128B2 (en) * 2000-01-07 2003-06-17 Sony Corporation Semiconductor substrate, semiconductor device, and processes of production of same
JP2006019424A (en) * 2004-06-30 2006-01-19 Nec Electronics Corp Soi substrate, manufacturing method thereof, and semiconductor device

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