JPS59232437A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS59232437A JPS59232437A JP10707283A JP10707283A JPS59232437A JP S59232437 A JPS59232437 A JP S59232437A JP 10707283 A JP10707283 A JP 10707283A JP 10707283 A JP10707283 A JP 10707283A JP S59232437 A JPS59232437 A JP S59232437A
- Authority
- JP
- Japan
- Prior art keywords
- opening
- oxidation
- semiconductor substrate
- film
- silicon nitride
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/763—Polycrystalline semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76281—Lateral isolation by selective oxidation of silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76286—Lateral isolation by refilling of trenches with polycristalline material
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は高密度，高速性を備えてなる半導体集積回路装
置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor integrated circuit device having high density and high speed.
従来例の構成とその問題点
半導体集積回路は、高密ＩＷ化，筒速化，低消費電力化
が進んでいるが、かかる装置において、問題となるのが
，寄生容量である，１例えば、バイポーラ素子において
は、コレクタと基板間に発生する寄生容量であり，ＭＯ
Ｓ素子においては，ソース，ドレインと基板間ＶＣ発生
する寄生容量である。Conventional configurations and their problems Semiconductor integrated circuits are becoming more dense IW, faster, and have lower power consumption, but in such devices, parasitic capacitance is a problem. In an element, it is a parasitic capacitance that occurs between the collector and the substrate, and MO
In the S element, this is a parasitic capacitance generated between the source, drain, and substrate.
この寄生容量を削減することが出来れば、より高速で低
消費電力の半心体素子を形成することが可能である。そ
のためこの容置削減の方法として、多くの試みが実施さ
れて米た。If this parasitic capacitance can be reduced, it is possible to form a half-core element with higher speed and lower power consumption. Therefore, many attempts have been made to reduce this storage capacity.
その一例は、単結晶の絶縁物基板たとえば、ザファイア
などを使用して，その上｛てシリコン層を気相成長させ
る方法で通常Ｓ Ｏ Ｓ （ Ｓｉｌｉｃｏｎ Ｏｎ
Ｓａｐｈｉｒｅ ）と呼ばれている方法である。このＳ
ＯＳ基板を使用し、そのシリ：１ン気Ａロ成長層内に形
成された素子は、寄生容量も少なく優れた特長を有して
いるが、次の様な欠点がある。An example of this is to use a single crystal insulator substrate such as zaphire and grow a silicon layer thereon in a vapor phase.
This method is called Saphire. This S
A device using an OS substrate and formed within its silicon-air-grown layer has excellent features such as low parasitic capacitance, but has the following drawbacks.
（１） 基板として単結晶のザファイアを使用してい
るため高価である。(1) It is expensive because it uses single crystal zaphire as a substrate.
（２）素子製作のプロセスとしてｒ５温処理をする際に
ザフ１イア基板からアルミナ（ Ａ１２０３ ）が蒸発
又は拡散し、電気炉等を汚染さする。(2) Alumina (A1203) evaporates or diffuses from the XAF1IA substrate during R5 temperature treatment as part of the device manufacturing process, contaminating the electric furnace and the like.
この２点の欠点のため、ＳＯＳ基板は現在迄広く使用さ
れるに至っていない。Due to these two drawbacks, SOS substrates have not been widely used to date.
第２の従来例としては、シリコンの多孔質化により、基
板を絶縁物化する方法である。第１図はその製造工程を
示す断面図である。A second conventional example is a method in which the substrate is made into an insulator by making silicon porous. FIG. 1 is a sectional view showing the manufacturing process.
第１図ａはｎ型ンリコン基板１に高濃度のｐ型不純物層
２を形成し、この上にｎ型のエビタギシャル層３を気相
成長させ，エビタギ／ヤル層３に選択的にｐ型不純物層
４を形成したものである。In Figure 1a, a highly concentrated p-type impurity layer 2 is formed on an n-type silicon substrate 1, an n-type epitaxial layer 3 is grown in a vapor phase on this layer, and the p-type impurity layer 3 is selectively doped. Layer 4 was formed.
次に、第１図ｂ ｖｃ示すように、ｐ型不純物層２。Next, as shown in FIG. 1 b vc, a p-type impurity layer 2 is formed.
４を多孔質化させ多孔質領域５を形成する。ここで、多
孔質処理は通常、ＨＦ（沸酸）溶媒内で、電界を印加す
ることにより、ｐ型不純物層が選択的に多孔質化される
ことを利用している。この多孔質領域らは表面積が多い
ため、酸化されやすく、酸化処理をすることにより，容
易に酸化膜６に変化する（第１図Ｏ）。4 is made porous to form a porous region 5. Here, the porous treatment usually utilizes the fact that the p-type impurity layer is selectively made porous by applying an electric field in an HF (hydrofluoric acid) solvent. Since these porous regions have a large surface area, they are easily oxidized, and are easily transformed into an oxide film 6 by oxidation treatment (FIG. 1O).
第１図に示す方法で製造されたものは素子形成領域の側
面部と底面部が酸化されており、寄生容量も小さくなり
良好であるが、次の様な欠点を有する。The device manufactured by the method shown in FIG. 1 has oxidized side and bottom portions of the element forming region and has a small parasitic capacitance, which is good, but it has the following drawbacks.
（１）高濃度のｐ型不純物層を埋込むため、気相成長さ
れた層に不純物が拡散されやすく、薄いｎ型層が形成さ
ｔ′Ｌ．にくい。(1) Since the p-type impurity layer is buried at a high concentration, the impurity is easily diffused into the vapor-phase grown layer, and a thin n-type layer is formed. Hateful.
（２）第１図ａにおけるｐ散拡散層４の大きさ（断面，
開孔口等）Ｋより多孔質化の状態が太きく作用される。(2) Size (cross section,
(pore openings, etc.) The state of porosity is affected more strongly than by K.
（３）酸化工程により多孔質領域は膨脂し、多孔質領域
の大きさにより膜厚が均一とならない。(3) The porous region swells due to the oxidation process, and the film thickness becomes uneven depending on the size of the porous region.
等の欠点が存在する。There are drawbacks such as:
第３の例を，第２図に示す。第２図ａはｐ型／リコン基
板１１にｎ型領域１２を拡散形成し、その後ｎ型たとえ
ばＱ．６Ω−ＣａＨの気相成長層１３を形成し、その上
に酸化シリコン層１４を付着さぜ、最上部に耐酸化性物
質たとえばシリコン窒化膜（ Ｓｉ３Ｎ，、膜）１５を
形成し、開口後、シリコン基板１１を異方性エノチング
したものである。シリコン窒化膜１ｓｉシリコン基板１
１のエノチングにより、その先端部１６はひさし状にな
るが、開口部１７ば、異方性エノチングたとえばＲ・工
・Ｅ・（ Ｒｅ？Ｌｃｔｉｒｅ ｉｏｎ ｅｔｃｈ
ｉｎｇ ） ＶＣより、ほぼ垂直に開口される。第２図
ｂにおいては、シリコン窒化膜１１をマスクとして酸化
処理を行い酸化膜１８を薄く形成した後、全面にシリコ
ン窒化膜１９。A third example is shown in FIG. In FIG. 2a, an n-type region 12 is diffused into a p-type/recon substrate 11, and then an n-type region 12, for example, Q. A 6Ω-CaH vapor phase growth layer 13 is formed, a silicon oxide layer 14 is deposited thereon, an oxidation-resistant material such as a silicon nitride film (Si3N, film) 15 is formed on top, and after opening, A silicon substrate 11 is anisotropically etched. Silicon nitride film 1si silicon substrate 1
1, the tip 16 becomes a canopy, but the opening 17 is anisotropically etched, such as R・E・(Re?Lctire ion etch).
ing) It is opened almost perpendicularly from the VC. In FIG. 2b, an oxidation process is performed using the silicon nitride film 11 as a mask to form a thin oxide film 18, and then a silicon nitride film 19 is formed over the entire surface.
２０、２１を形成する。ここで、１９は開［１部１７の
側面に付着したもの、２０ほシリコン窒化膜１５−ヒに
、２１は開口部１７の底面に付着したものである。次に
、第２図Ｃにおいては、ノリコン基板１１を、異方性の
エツチングにより、シリコン窒化膜２０．２１を除去す
る。尚、側面に付着しているシリコン窒化膜１９は異方
性エツチングのために除去されない。ここで、開口１部
１７の底面２２は酸化膜１８が露出した状態となる。こ
の後、シリコン窒化膜１ら、１８をマスクとして酸化処
理を行ない、酸化膜２３を形成する（第２図ｄ）。20 and 21 are formed. Here, 19 is what is attached to the side surface of the opening 17, 20 is what is attached to the silicon nitride film 15-1, and 21 is what is attached to the bottom of the opening 17. Next, in FIG. 2C, the silicon nitride films 20 and 21 of the Noricon substrate 11 are removed by anisotropic etching. Note that the silicon nitride film 19 adhering to the side surfaces is not removed due to anisotropic etching. Here, the oxide film 18 is exposed on the bottom surface 22 of the opening 1 portion 17. Thereafter, an oxidation process is performed using the silicon nitride films 1 and 18 as masks to form an oxide film 23 (FIG. 2d).
ここで、本工程では開口部１７の側面に耐酸性物質であ
るシリコン窒化膜１９が被着さ１％でいるために、横方
向へは酸化が進甘ず、そのため垂直な方向に伸びる酸化
膜２３が形成される。Here, in this step, since the silicon nitride film 19, which is an acid-resistant material, is deposited on the side surface of the opening 17 at a rate of 1%, oxidation does not proceed in the lateral direction, and therefore the oxide film extends in the vertical direction. 23 is formed.
この従来例は、酸化膜が横に広がらず活性領域がその１
壕残るため側面の分離法としては優れでいるが、活性領
域底部は酸化膜が形成されておらず％１ｔｉｌ１面の寄
生容量のみしか削減できない欠点を有する。In this conventional example, the oxide film does not spread horizontally and the active region is
This method is excellent as a side surface isolation method because a trench remains, but it has the disadvantage that no oxide film is formed at the bottom of the active region and only the parasitic capacitance of the %1til1 plane can be reduced.
発明の目的
本発明は素子形成領域の側面ばかりでなく、底面にも絶
縁膜を形成でさる半導体装置の製造方法を提供せんとす
るものである。OBJECTS OF THE INVENTION The present invention provides a method for manufacturing a semiconductor device in which an insulating film is formed not only on the side surfaces of an element forming region but also on the bottom surface.
発明の構成
本発明の半導体装置の製造方法は半導体基体に形成した
開口部に選択的に耐酸化性被膜を形成し、この被膜をマ
スクとして半導体基体を酸化し、底面及び側面が酸化膜
で包囲された活性領域を形成するものである。Structure of the Invention The method for manufacturing a semiconductor device of the present invention includes selectively forming an oxidation-resistant film on an opening formed in a semiconductor substrate, oxidizing the semiconductor substrate using this film as a mask, and surrounding the bottom and side surfaces with the oxide film. This forms an active region.
実施例の説明
〔実施例１〕
第３図は本発明の一実施例を示す工程断面図である。第
３図ａで３１はｐ型（１１１）基板で比抵抗は０．６〜
１Ω〜ｃｔｎである。３２は高濃度のｎ型埋込み層でＡ
ｓ が拡散されている。３３は気相成長法で形成された
ｎ型エピタギ／ヤル層で０．５〜０．６Ω−Ｃｍの比抵
抗である。３４は熱酸化膜、３５は耐酸化性被膜たとえ
ばシリコン窒化膜（５ｉ５Ｎ４膜）で、分離領域になる
部分のみを選択的に開口し、そこから基板をエツチング
除去する。エツチングの方法は、異方性の強いドライエ
ッチ法たとえば反応性イオンエッチ（Ｒ，１，Ｅ・）を
使って行ない、垂直にｐ型基板３１に達する深さ迄エツ
チングして開１」部３６を形成する。次に、第３図すに
示す如く、ノリ：１ン窒化膜３５をマスクとして熱酸化
を行ない酸化膜３了を形成する。その後全面にシリコン
窒化膜３８，３９．４０を減圧ＣＶＤ法で形成する。こ
こで、３８は開１］部３６の側面、３９はシリコン窒化
膜３６上、４０は開口部３６底面に形成さｉたノリコン
窒化膜である。尚、減圧ＣＶＤ法でのシリコン窒化膜の
生成は、開ｊ」部３６の側面へシリコン窒化膜を均質に
付着させるためである。その後、活性イオンエツチング
法で異方性の強いエツチングを行なつと、開口部３６の
側壁部のシリコン窒化膜３８のみを残して、シリコン窒
化膜３９，４０が除去される（第３図Ｃ）。Description of Examples [Example 1] FIG. 3 is a process sectional view showing an example of the present invention. In Figure 3a, 31 is a p-type (111) substrate with a specific resistance of 0.6~
It is 1Ω~ctn. 32 is a high concentration n-type buried layer A
s is diffused. 33 is an n-type epitaxial layer formed by vapor phase growth and has a specific resistance of 0.5 to 0.6 Ω-Cm. 34 is a thermal oxide film, and 35 is an oxidation-resistant film such as a silicon nitride film (5i5N4 film). Only the portion that will become the isolation region is selectively opened, and the substrate is etched away from there. The etching method is a highly anisotropic dry etching method, such as reactive ion etching (R, 1, E. form. Next, as shown in FIG. 3, thermal oxidation is performed using the glue nitride film 35 as a mask to form an oxide film 3. Thereafter, silicon nitride films 38, 39, and 40 are formed on the entire surface by low pressure CVD. Here, 38 is a side surface of the opening 36, 39 is a silicon nitride film formed on the silicon nitride film 36, and 40 is a silicon nitride film formed on the bottom surface of the opening 36. The silicon nitride film is generated by the low pressure CVD method in order to uniformly adhere the silicon nitride film to the side surface of the opening 36. Thereafter, when highly anisotropic etching is performed using active ion etching, the silicon nitride films 39 and 40 are removed, leaving only the silicon nitride film 38 on the side wall of the opening 36 (FIG. 3C). .
この後、酸化膜３７を除去し、基板３１を等方向なエツ
チングたとえば湿式のエツチングを行ない開［」都４１
を形成する（第３図ｄ）。そして、シリコン窒化膜を、
暴力性の強い付着法たとえばスパッタ法あるいはプラズ
マ法を使い形成する。従って、シリコン窒化膜４２．４
３は図の如く形成され、開口部３６の側面、特に、開口
部４１の４１１１１面４４にはシリコン窒化膜は付着さ
７″１．ない（第３図ｅ）。その後、高圧酸化法で約７
気圧の圧力下で酸化すると、被酸化領域は、シリコン窒
化膜３５．３８．４２１ ４３が覆われていない領域に
限定される為、開口部４１の側面４４の方向に酸化が進
み、同時に膨張した酸化膜は、開口部３６を埋めるべく
上部へ伸びるように形成され、結果として、分離された
エヒリギンヤル層３３の底面及び側面に酸化膜４５が形
成さｎる（第３図ｆ）。Thereafter, the oxide film 37 is removed, and the substrate 31 is etched in an isodirectional manner, for example, by wet etching.
(Fig. 3d). Then, the silicon nitride film is
It is formed using a highly violent adhesion method, such as a sputtering method or a plasma method. Therefore, the silicon nitride film 42.4
No. 3 is formed as shown in the figure, and the silicon nitride film is not attached to the side surface of the opening 36, especially the 41111 surface 44 of the opening 41 (see FIG. 7
When oxidized under atmospheric pressure, the oxidized area is limited to the area where the silicon nitride film 35, 38, 421 43 is not covered, so the oxidation progresses in the direction of the side surface 44 of the opening 41 and expands at the same time. The oxide film is formed to extend upward to fill the opening 36, and as a result, an oxide film 45 is formed on the bottom and side surfaces of the separated secondary layer 33 (FIG. 3f).
尚、最適な条件と、活性領域の距離を狭くすると、横に
伸びた酸化膜４６同士は、活性領域下部で接続すること
となる。Note that when the optimum conditions and the distance between the active regions are narrowed, the horizontally extending oxide films 46 are connected to each other at the bottom of the active regions.
〔実施例２〕 第４図は本発明の他の実施例を示す工程断面図である。[Example 2] FIG. 4 is a process sectional view showing another embodiment of the present invention.
葦ず、第４図ａで、５１はｐ型基板であるが、Ｎ型でも
良い。５２は高濃度のｎ型拡散層”？ｌ’、コノ上に低
濃度のｎ型エピタキシャルＪｆ４５３が形成されている
。エビタキ／ヤル層に開口部をもうけ、酸化層５４と、
開口部側壁の酸化層５５を酸化］二程により成長させ、
第１の実施例に詳述したごとぐ、！１１Ｉ酸化性被膜た
とえばシリコン窒化膜５６．５７を形成する。図で明ら
かなように開口部５８の底部に基板６１が露出している
。この後、弗酸と硝酸の混合液でエツチングする。エツ
チングは当初緩やかであるが、液が高ａ度の拡散層６２
に達した時、早くなり非等方的な形状を示し、開口部５
９が形成される（第４図ｂ）。次に、シリコン窒化膜を
スパッター等の方法で異方的に付着させ、開口部６９の
底面」二、シリコン窒化膜６６上にそれぞれシリコン窒
化膜６Ｑ、６１を形成する（第４図Ｃ）。次に、シリコ
ン窒化膜５７゜６０．６１をマスクに酸化処理を行ない
、分離されたエピタキシャル層５３下に酸化膜６２が形
成される１で酸化処理をする（第４図ｄ）。この後、通
常の溝埋込み法により、多結晶シリコン膜６３を開口部
３６に埋込み、多結晶シリコン膜６３」二に酸化膜６４
を形成する（第４図ｅ）。In FIG. 4a, 51 is a p-type substrate, but it may be an n-type substrate. 52 is a high concentration n-type diffusion layer "?l', and a low concentration n-type epitaxial layer Jf453 is formed on top of it. An opening is made in the epitaxial/yellow layer, and an oxide layer 54 is formed.
The oxide layer 55 on the side wall of the opening is grown by two steps,
As detailed in the first embodiment! A 11I oxidizing film, such as a silicon nitride film 56,57, is formed. As is clear from the figure, the substrate 61 is exposed at the bottom of the opening 58. After that, it is etched with a mixture of hydrofluoric acid and nitric acid. Etching is gradual at first, but the etching is at a high a degree in the diffusion layer 62.
When reaching , it becomes faster and shows an anisotropic shape, and the opening 5
9 is formed (Fig. 4b). Next, a silicon nitride film is anisotropically deposited by a method such as sputtering to form silicon nitride films 6Q and 61 on the bottom surface of the opening 69 and on the silicon nitride film 66, respectively (FIG. 4C). Next, an oxidation process is performed using the silicon nitride film 57.60.61 as a mask, and an oxidation process is performed at step 1 to form an oxide film 62 under the separated epitaxial layer 53 (FIG. 4d). Thereafter, a polycrystalline silicon film 63 is filled in the opening 36 by a normal trench filling method, and then the polycrystalline silicon film 63 and the oxide film 64 are filled.
(Fig. 4e).
以上の工程により、単結晶領域であるエピタキシャル層
５３が酸化膜で囲こ寸れた構造が形成される。Through the above steps, a structure in which the epitaxial layer 53, which is a single crystal region, is surrounded by an oxide film is formed.
本実施例の場合は分離すべきエピタキシャル層５３の間
が犬のときでも、多結晶シリコン膜を埋め込むのみで分
離が可能となる利点を有する。更に、本実施例では高濃
度の拡散層６２をエツチングしているので、容易に非等
方的形状の開口部５つを形成でさる利点を有する。This embodiment has the advantage that even if there is a gap between the epitaxial layers 53 to be separated, separation is possible simply by embedding a polycrystalline silicon film. Furthermore, in this embodiment, since the highly-concentrated diffusion layer 62 is etched, there is an advantage that five openings having anisotropic shapes can be easily formed.
崗、以上の実施例は主にバイポーラ集積回路に適用でさ
る活性領域について示しているが、他に一般のＭＯ３型
集積回路や、固体撮像素子、記憶素子とじても使用でき
、一般的なＳ ＯＸ （５ｉｌｉｃｏｎｏｎ １ｎｓ
ｕｌａｔｏｒ ）デバイスと同様な用途が期待される。Although the above embodiments are mainly applied to active regions applied to bipolar integrated circuits, they can also be used in general MO3 type integrated circuits, solid-state image sensors, and memory devices. OX (5iliconon 1ns
Applications similar to those for ulator) devices are expected.
特に、ＭＯＳデバイスにおいては、ラッチアップ防止、
α線によるソフトエラー防止等の効果が期待される。In particular, in MOS devices, latch-up prevention,
It is expected to be effective in preventing soft errors caused by alpha rays.
発明の効果
本発明によれば活性領域の側面及び底面に分離酸化膜を
容易に形成でき、しかも、
（１）製作プロセスが、通常集積回路において多用さ几
ている方法のみを用いて実施でさるため、装置への汚染
等の問題が発生しない。Effects of the Invention According to the present invention, it is possible to easily form an isolation oxide film on the side and bottom surfaces of the active region, and furthermore, (1) the manufacturing process can be carried out using only methods that are commonly used in normal integrated circuits; Therefore, problems such as contamination of the equipment do not occur.
−（２）絶縁膜がシリコンの熱酸化膜であるので、膜の
ち密性にも優れ、活性領域であるシリコンとの界面での
界面準位も少ない。-(2) Since the insulating film is a thermally oxidized silicon film, the film has excellent film density and has few interface states at the interface with silicon, which is the active region.
（３）活性領域の太ささ等により酸化時間を長くするこ
とにより、酸化部分の膨張に伴なう歪の発生が考えられ
るが、本発明は活性領域下部すべてを酸化する必要もな
く、歪の発生と寄生容量削減のかねあいで、横方向への
酸化量を決定することが可能である。(3) By lengthening the oxidation time depending on the thickness of the active region, strain may occur due to expansion of the oxidized portion, but the present invention eliminates the need to oxidize the entire lower part of the active region, and reduces strain. It is possible to determine the amount of oxidation in the lateral direction based on the balance between generation and reduction of parasitic capacitance.
等の効果を有し、工業的価値が高いものである。It has the following effects and is of high industrial value.
第１図ＩＬ −Ｑ ｕ多孔質を使った従来の酸化法によ
る工程断面図、第２図ａ −６は従来法による垂直型絶
縁分離法による工程断面図、第３図ａ −ｆは本発明の
第１の実施例を示す工程断面図、第４図ａ〜ｅは本発明
の第２の実施例を示す工程断面図である。
３５．３８，４２．４３・・・・・・シリコン窒化膜、
３６・・・・・・第１の開口部、４１・・・・・・第２
の開口部、４５・・・・・・酸化膜、５２・・・・・・
高濃度拡散層、５６゜５７．６Ｑ、６１・・・・・・ノ
リコン窒化膜、６２・・・・・・酸化膜、６３・・・・
・・多結晶シリコン膜。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第３
図
第４図Figure 1 is a process cross-sectional view of a conventional oxidation method using IL-Q u porous material, Figure 2 a-6 is a process cross-section view of a conventional vertical insulation separation method, and Figure 3 a-f is a process cross-sectional view of the present invention. FIGS. 4A to 4E are process cross-sectional views showing the second embodiment of the present invention. 35.38, 42.43... Silicon nitride film,
36...First opening, 41...Second
opening, 45... oxide film, 52...
High concentration diffusion layer, 56°57.6Q, 61...Noricon nitride film, 62...Oxide film, 63...
...Polycrystalline silicon film. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 3
Figure 4
Claims (5)
マスクとして前記半導体基体に第１の開口部を形成する
工程と、第２の耐酸化性被膜を前記半導体基体上に形成
する工程と、異方性エツチングにより前記第１の開口部
側面に前記第２の耐酸化性被膜を残存させる工程と、前
記第１の開口部底部から前記半導体基体をエツチングし
第２の開口部を形成する工程と、前記半導体基体表面か
ら異方的に第３の耐酸化性被膜を付着させ、前記第２の
開口部の底部に前記第３の耐酸化性被膜を形成する工程
と、前記第１〜第３の耐酸化性被膜をマスクとして酸化
性雰囲気で前記半導体基体を熱処理して、前記第１．第
２の開口部に酸化膜を形成する工程とを含むことを特徴
とする半導体装置の製造方法。(1) Forming a first opening in the semiconductor substrate using a first oxidation-resistant coating formed on the semiconductor substrate as a mask; and forming a second oxidation-resistant coating on the semiconductor substrate. a step of leaving the second oxidation-resistant film on the side surface of the first opening by anisotropic etching, and etching the semiconductor substrate from the bottom of the first opening to form a second opening. a step of anisotropically depositing a third oxidation-resistant coating from the surface of the semiconductor substrate to form the third oxidation-resistant coating on the bottom of the second opening; The semiconductor substrate is heat-treated in an oxidizing atmosphere using the first to third oxidation-resistant films as masks, and the semiconductor substrate is heat-treated in an oxidizing atmosphere using the first to third oxidation-resistant films as masks. A method of manufacturing a semiconductor device, comprising the step of forming an oxide film in the second opening.
た第３の開口部と酸化物を介して接続されることを特徴
とする特許請求の範囲第１項記載の半導体装置の製造方
法。(2) The semiconductor device according to claim 1, wherein the second opening filled with oxide is connected to an adjacent third opening via oxide. Production method.
マスクとして前記半導体基体に第１の開口部を形成する
工程と、第２の耐酸化性被膜を前記半導体基体上に形成
する工程と、異方性エツチングにより前記第１の開口部
側面に前記第２の耐酸化性被膜を残存させる工程と、前
記第１の開口部から前記半導体基体をエツチングし、第
２の開口部を形成する工程と、前記半導体基体表面から
異方的第３の耐酸化性被膜を付着させ前記第２の開口部
の底面に前記第３の耐酸化性被膜を形成する工程と、前
記第１〜第３の耐酸化性被膜をマスクとして酸化性雰囲
気で前記半導体基体を熱処理して、前記第２の開口部に
酸化膜を形成する工程と、前記第１の開口部に絶縁膜を
介して半導体層を形成する工程とを含むことを特徴とす
る半導体装置の製造方法。(3) forming a first opening in the semiconductor substrate using the first oxidation-resistant coating formed on the semiconductor substrate as a mask; and forming a second oxidation-resistant coating on the semiconductor substrate. a step of leaving the second oxidation-resistant film on the side surface of the first opening by anisotropic etching; and etching the semiconductor substrate from the first opening to form a second opening. a step of depositing an anisotropic third oxidation-resistant coating from the surface of the semiconductor substrate to form the third oxidation-resistant coating on the bottom surface of the second opening; heat-treating the semiconductor substrate in an oxidizing atmosphere using a third oxidation-resistant film as a mask to form an oxide film in the second opening; 1. A method for manufacturing a semiconductor device, comprising the step of forming a layer.
濃度不純物層が形成されていることを特徴とする特許 の製造方法。(4) A patented manufacturing method characterized in that a high concentration impurity layer is formed in a portion of the semiconductor substrate where the second opening is to be formed.
た第３の開し１部と酸化物を介して接続されていること
を特徴とする特許請求の範囲第３項記載の半導体装置の
製造方法。(5) The second opening filled with the oxide is connected to the adjacent third opening via the oxide. A method for manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10707283A JPS59232437A (en) | 1983-06-15 | 1983-06-15 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10707283A JPS59232437A (en) | 1983-06-15 | 1983-06-15 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59232437A true JPS59232437A (en) | 1984-12-27 |
Family
ID=14449768
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10707283A Pending JPS59232437A (en) | 1983-06-15 | 1983-06-15 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59232437A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5112771A (en) * | 1987-03-20 | 1992-05-12 | Mitsubishi Denki Kabushiki Kaisha | Method of fibricating a semiconductor device having a trench |
| US5661073A (en) * | 1995-08-11 | 1997-08-26 | Micron Technology, Inc. | Method for forming field oxide having uniform thickness |
| US6110798A (en) * | 1996-01-05 | 2000-08-29 | Micron Technology, Inc. | Method of fabricating an isolation structure on a semiconductor substrate |
| EP1049155A1 (en) * | 1999-04-29 | 2000-11-02 | STMicroelectronics S.r.l. | Process for manufacturing a SOI wafer with buried oxide regions without cusps |
| US6465865B1 (en) | 1996-01-05 | 2002-10-15 | Micron Technology, Inc. | Isolated structure and method of fabricating such a structure on a substrate |
| US6699742B2 (en) * | 1999-03-16 | 2004-03-02 | Micron Technology, Inc. | Base current reversal SRAM memory cell and method |
| US6891213B1 (en) | 1999-03-16 | 2005-05-10 | Micron Technology, Inc. | Base current reversal SRAM memory cell and method |
| JP2009508322A (en) * | 2005-06-02 | 2009-02-26 | ザ ボード オブ トラスティーズ オブ ザ ユニヴァーシティー オブ イリノイ | Printable semiconductor structure and related manufacturing and assembly methods |
-
1983
- 1983-06-15 JP JP10707283A patent/JPS59232437A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5112771A (en) * | 1987-03-20 | 1992-05-12 | Mitsubishi Denki Kabushiki Kaisha | Method of fibricating a semiconductor device having a trench |
| US5661073A (en) * | 1995-08-11 | 1997-08-26 | Micron Technology, Inc. | Method for forming field oxide having uniform thickness |
| US6103595A (en) * | 1995-08-11 | 2000-08-15 | Micron Technology, Inc. | Assisted local oxidation of silicon |
| US6110798A (en) * | 1996-01-05 | 2000-08-29 | Micron Technology, Inc. | Method of fabricating an isolation structure on a semiconductor substrate |
| US6465865B1 (en) | 1996-01-05 | 2002-10-15 | Micron Technology, Inc. | Isolated structure and method of fabricating such a structure on a substrate |
| US6479370B2 (en) | 1996-01-05 | 2002-11-12 | Micron Technology, Inc. | Isolated structure and method of fabricating such a structure on a substrate |
| US6559032B2 (en) | 1996-01-05 | 2003-05-06 | Micron Technology, Inc. | Method of fabricating an isolation structure on a semiconductor substrate |
| US6699742B2 (en) * | 1999-03-16 | 2004-03-02 | Micron Technology, Inc. | Base current reversal SRAM memory cell and method |
| US6891213B1 (en) | 1999-03-16 | 2005-05-10 | Micron Technology, Inc. | Base current reversal SRAM memory cell and method |
| EP1049155A1 (en) * | 1999-04-29 | 2000-11-02 | STMicroelectronics S.r.l. | Process for manufacturing a SOI wafer with buried oxide regions without cusps |
| JP2009508322A (en) * | 2005-06-02 | 2009-02-26 | ザ ボード オブ トラスティーズ オブ ザ ユニヴァーシティー オブ イリノイ | Printable semiconductor structure and related manufacturing and assembly methods |
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