JPH0516181B2 - - Google Patents
Info
- Publication number
- JPH0516181B2 JPH0516181B2 JP57081583A JP8158382A JPH0516181B2 JP H0516181 B2 JPH0516181 B2 JP H0516181B2 JP 57081583 A JP57081583 A JP 57081583A JP 8158382 A JP8158382 A JP 8158382A JP H0516181 B2 JPH0516181 B2 JP H0516181B2
- Authority
- JP
- Japan
- Prior art keywords
- groove
- film
- dielectric material
- filled
- depth
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000003989 dielectric material Substances 0.000 claims description 19
- 239000004065 semiconductor Substances 0.000 claims description 17
- 238000005229 chemical vapour deposition Methods 0.000 claims description 15
- 238000002955 isolation Methods 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 8
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 238000009413 insulation Methods 0.000 claims description 4
- 238000000926 separation method Methods 0.000 claims 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 238000005530 etching Methods 0.000 description 4
- 238000011049 filling Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000007373 indentation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
- 238000004335 scaling law Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/763—Polycrystalline semiconductor regions
Description
【発明の詳細な説明】
本発明は半導体基板に設けた溝内に誘電体材料
を充填して複数の半導体素子間相互の絶縁分離
（アイソレーシヨン）を行なつた半導体装置に関
するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device in which a trench provided in a semiconductor substrate is filled with a dielectric material to isolate a plurality of semiconductor elements from each other.
上記絶縁分離は、従来のPN接合分離に比べ
て、所要面積と寄生容量が非常に小さく、高集積
高速LSIに適している。ところが、任意の溝幅の
溝に誘電体材料を平坦に埋め込む必要がある（表
面に凹凸が生じると、その上に形成する配線金属
が切断される可能性が大きくなる等の欠点が生じ
る。）ため、その平坦化のためにプロセスが複雑
になる欠点があつた。 The above insulation isolation requires much smaller area and parasitic capacitance than conventional PN junction isolation, and is suitable for highly integrated high-speed LSIs. However, it is necessary to fill the dielectric material flatly into a groove with an arbitrary groove width (if the surface is uneven, there are drawbacks such as an increased possibility that the wiring metal formed thereon will be cut). Therefore, there was a drawback that the process for flattening was complicated.
本発明の目的は、上記従来技術の欠点を除去
し、簡単なプロセスで溝内に誘電体材料（本明細
書では、多結晶シリコン、非晶質シリコン、
SiO2、Si3N4など、アイソレーシヨンのために溝
内に充填する材料を総称して誘電体材料と記す）
を平坦に充填できる溝構造を備えた半導体装置を
提供することにある。 The object of the present invention is to eliminate the drawbacks of the prior art described above and to form a dielectric material (herein polycrystalline silicon, amorphous silicon, polycrystalline silicon, amorphous silicon,
Materials filled in the groove for isolation, such as SiO 2 and Si 3 N 4 , are collectively referred to as dielectric materials.)
An object of the present invention is to provide a semiconductor device having a trench structure that can be flatly filled.
この目的を達成するために、本発明の半導体装
置は、半導体基板に設けた断面形状がＹ字形であ
る溝内に誘電体材料をCVD（ケミカル ヴエイパ
ー デポジシヨン（Chemical Vapor
Deposition））法、またはCVD法および熱酸化法
を用いて充填して素子間の絶縁分離を行なう半導
体装置において、上記溝の断面形状を
1.0≧Ｈ／Ｄ≧0.1＋0.625（Ｗ／Ｄ）2
但しＷ：溝の開口部の幅
Ｄ：溝の深さ
Ｈ：溝の充填時に半導体基板表面に形成される誘
電体材料の膜厚
Ｗ／Ｄ≦1.2
なる条件を満たす範囲内に選んだことを特徴とす
る。 In order to achieve this object, the semiconductor device of the present invention uses CVD (Chemical Vapor Deposition) to deposit a dielectric material into a groove with a Y-shaped cross section provided in a semiconductor substrate.
In a semiconductor device in which insulation isolation between elements is achieved by filling using a deposition method, a CVD method, or a thermal oxidation method, the cross-sectional shape of the trench is 1.0≧H/D≧0.1+0.625 (W/D). 2 However, W: Width of the trench opening D: Depth of the trench H: Thickness of the dielectric material formed on the surface of the semiconductor substrate when filling the trench W/D≦1.2. It is characterized by
すなわち、本発明は溝の幅を一定寸法以下に制
限することによつてCVD法（少なくとも１回は
必ず行なう）または熱酸化法で形成された埋込用
誘電体材料の平坦化エツチングを容易にするもの
である。これは、CVD法および熱酸化法では溝
の側面からも誘電体膜の形成が起こるため狭い溝
は充填されやすいからである。 That is, the present invention makes it easy to planarize and etch the buried dielectric material formed by the CVD method (which must be performed at least once) or the thermal oxidation method by limiting the width of the groove to a certain size or less. It is something to do. This is because in the CVD method and the thermal oxidation method, a dielectric film is formed from the side surfaces of the trench, so narrow trenches are easily filled.
以下、本発明を図面を用いて説明する。 Hereinafter, the present invention will be explained using the drawings.
第１図は本発明の原理を説明するための模式的
断面図である。図において、１は半導体基板、２
は断面形状が、Ｙ字形であるアイソレーシヨン用
の溝、３は誘電体材料の膜である。 FIG. 1 is a schematic cross-sectional view for explaining the principle of the present invention. In the figure, 1 is a semiconductor substrate, 2
3 is an isolation groove having a Y-shaped cross section, and 3 is a film made of a dielectric material.
アイソレーシヨン用の溝２の幅Ｗの上限値は、
溝２の深さＤと例えばCVD法で形成した誘電体
材料の膜厚Ｈによつて変化する。まず、アイソレ
ーシヨン溝幅の最適値について説明する。 The upper limit of the width W of the isolation groove 2 is:
It changes depending on the depth D of the groove 2 and the film thickness H of the dielectric material formed by, for example, CVD method. First, the optimum value of the isolation groove width will be explained.
第１図に示すように、アイソレーシヨン用の溝
２の幅（溝の開口部の幅）をＷ、深さをＤ、誘電
体材料のCVD膜厚をＨ、CVD後の表面の窪みを
Ａとすると、種々実験の結果から、
Ａ＝Ｈ−√2−（２）2 (1)
の関係が成り立つたことが分つた。 As shown in Figure 1, the width of the isolation groove 2 (width of the opening of the groove) is W, the depth is D, the CVD film thickness of the dielectric material is H, and the depression on the surface after CVD is Assuming that A, it was found from the results of various experiments that the relationship A=H−√ 2 −(2) 2 (1) holds.
ここで、(1)式をＤで規格化すると、 Ａ／Ｄ＝Ｈ／Ｄ−√（）2−（2）2 (2) となる。 Here, when formula (1) is normalized by D, it becomes A/D=H/D−√() 2 −(2) 2 (2).
表面の窪みＡが大きくなると配線金属が切れや
すくなるので、Ａの上限は断線率で制限される。
配線として使用するAl膜の膜厚はデバイスの寸
法に依存し、おおむね溝の深さＤの1/3である
（スケーリング則を考慮している）。そこで、Al
膜の膜厚をＤ／３としたときの、Al膜の断線率
と窪みの大きさの割合Ａ／Ｄとの関係を測定した
ところ、第２図に示したグラフのようになり、Ａ
がＤの20％以下であれば断線が起ころないことが
わかつた。従つて、例えば溝の深さ3μｍ、Al膜
の厚さ1μｍとしたとき、Ａは0.6μｍ以下にする必
要がある。 As the surface depression A becomes larger, the wiring metal becomes more likely to break, so the upper limit of A is limited by the wire breakage rate.
The thickness of the Al film used as the wiring depends on the dimensions of the device, and is approximately 1/3 of the trench depth D (taking into account the scaling law). Therefore, Al
When we measured the relationship between the disconnection rate of the Al film and the depression size ratio A/D when the film thickness was D/3, the graph shown in Figure 2 was obtained, and A
It was found that if D is less than 20% of D, disconnection will not occur. Therefore, for example, when the depth of the groove is 3 μm and the thickness of the Al film is 1 μm, A needs to be 0.6 μm or less.
さて、表面の窪みＡは、溝の深さＤの20％以下
となることが望ましいので、この条件は、
0.2≧Ｈ／Ｄ−√（）2−（2）2 (3)
と表わされる。(3)式を変形すると、
Ｈ／Ｄ≧0.1＋0.625（Ｗ／Ｄ）2 (4)
となる。 Now, since it is desirable that the depression A on the surface be 20% or less of the depth D of the groove, this condition is expressed as 0.2≧H/D−√() 2 −(2) 2 (3). When formula (3) is transformed, H/D≧0.1+0.625(W/D) 2 (4).
(4)式で表わされる領域を図示すると第３図の斜
線部となり、この斜線部の範囲に入るように
溝幅Ｗを決める必要がある。さらに、埋込材料
（充填する誘電体材料）のCVD膜厚は厚くなる
程、CVDに時間がかかり膜厚のばらつきも大き
くなるので、CVD膜厚Ｈは溝の深さＤよりも小
さいこと（Ｈ／Ｄ≦1.0）が望ましい。従つて、
溝幅Ｗは第３図における二重斜線部の範囲に入
るように決めることがより望ましい。 The region expressed by equation (4) is illustrated as the shaded area in FIG. 3, and it is necessary to determine the groove width W so that it falls within the range of this shaded area. Furthermore, as the CVD film thickness of the filling material (dielectric material to be filled) becomes thicker, CVD takes longer and the variation in film thickness becomes larger. Therefore, the CVD film thickness H should be smaller than the trench depth D ( H/D≦1.0) is desirable. Therefore,
It is more desirable to determine the groove width W so that it falls within the double hatched area in FIG.
このように溝の断面形状を決めることによつ
て、容易に絶縁分離領域の平坦化が達成される。 By determining the cross-sectional shape of the trench in this manner, the insulation isolation region can be easily flattened.
次に、バイポーラ集積回路の製造に関する実施
例を用いて、本発明を具体的に説明する。 Next, the present invention will be specifically explained using an example related to manufacturing a bipolar integrated circuit.
第４図ａ〜ｆは本発明の誘電体分離溝構造を有
する半導体装置の製造工程説明図で、同図ｆは本
発明の一実施例の半導体装置（バイポーラ集積回
路）の断面構造を示している。以下、図面の順番
ａ〜ｆに対応させて説明する。 4A to 4F are explanatory diagrams of the manufacturing process of a semiconductor device having a dielectric isolation groove structure according to the present invention, and FIG. 4F shows a cross-sectional structure of a semiconductor device (bipolar integrated circuit) according to an embodiment of the present invention. There is. Hereinafter, the explanation will be made in accordance with the order a to f of the drawings.
(a)：面方位（100）のSi基板４の表面にコレクタ
埋込層（厚さ約1.0μｍ）５を設け、その上にト
ランジスタの能動部分となるSiエピタキシヤル
層（厚さ約1.5μｍ）６を形成した後、その表面
を熱酸化してSiO2膜（厚さ約1000Å）７を形
成し、さらにその上に周知のCVD法によつて
Si3N4膜（厚さ約2000Å）８を形成した。(a): A collector buried layer (approximately 1.0 μm thick) 5 is provided on the surface of a Si substrate 4 with a plane orientation of (100), and a Si epitaxial layer (approximately 1.5 μm thick ) 6, the surface is thermally oxidized to form a SiO 2 film (about 1000 Å thick) 7, and then a well-known CVD method is applied to form a SiO 2 film 7.
A Si 3 N 4 film (about 2000 Å thick) 8 was formed.
(b)：通常のホトエツチング法を用いてSi3N4膜８
をパターニングした後、露出されたSiO2膜７
をオーバエツチしてSi3N4膜のひさし９を形成
した。次に、アルカリ系異方性エツチング液を
用いてSiエピタキシヤル層６を約1μｍエツチし
て斜めの（111）面、（55度）１０を形成し、さ
らにSi3N4膜８をマスクにして反応スパツタ法
でSiを約2μｍエツチし、埋込層５を突き抜ける
ほぼ垂直な溝１１を形成した。ここで、Si3N4
膜のパターン幅１２は、SiO2膜７のサイドエ
ツチを含めた溝の幅（パターン幅）１３が溝の
深さ１４よりも大きくならないようにし、2μ
ｍ以下に限定した。(b): Si 3 N 4 film 8 using normal photoetching method
After patterning, the exposed SiO 2 film 7
The eaves 9 of the Si 3 N 4 film were formed by overetching. Next, the Si epitaxial layer 6 is etched by about 1 μm using an alkaline anisotropic etching solution to form a diagonal (111) plane (55 degrees) 10, and the Si 3 N 4 film 8 is used as a mask. Then, the Si was etched by about 2 μm using a reactive sputtering method to form a substantially vertical groove 11 penetrating through the buried layer 5. Here, Si 3 N 4
The pattern width 12 of the film is set to 2μ so that the groove width (pattern width) 13 including the side etching of the SiO 2 film 7 is not larger than the groove depth 14.
It was limited to m or less.
(c)：チヤネル発生防止の目的で、埋込層５と反対
の導電性を持つ不純物をイオン打込み法によつ
て溝１１の底面に導入し、チヤネルストツパ層
１５を形成した。次いで、N2雰囲気中でアニ
ールした後、Si3N4膜８をマスクに選択酸化を
行ない溝内に厚いSiO2膜（厚さ約4000Å）１
６を形成した。マスクに用いた上記Si3N4膜８
を除去した後、再びSi3N4膜１７を全面に被着
し、さらにCVD法によつて多結晶Si１８を被
着した。ここで、多結晶Si１８の膜厚は溝の深
さ１４と同程度の約3μｍとした。このとき、
多結晶Si１８の表面に生ずる窪み１９は非常に
小さく約0.3μｍであつた。(c): For the purpose of preventing channel generation, an impurity having conductivity opposite to that of the buried layer 5 was introduced into the bottom surface of the groove 11 by ion implantation to form a channel stopper layer 15. Next, after annealing in an N 2 atmosphere, selective oxidation is performed using the Si 3 N 4 film 8 as a mask to form a thick SiO 2 film (about 4000 Å thick) 1 in the groove.
6 was formed. The above Si 3 N 4 film used for the mask 8
After removing the Si 3 N 4 film 17, a polycrystalline Si film 18 was further deposited by CVD. Here, the film thickness of the polycrystalline Si 18 was set to about 3 μm, which is about the same as the depth 14 of the groove. At this time,
The depression 19 formed on the surface of the polycrystalline Si 18 was very small, about 0.3 μm.
(d)：次に、等方性のエツチング液を用いて多結晶
Si１８をSi3N4膜１７の表面が出るまでエツチ
ングを行なつた。このときの多結晶Siの窪み２
０も約0.3μｍであつた。(d): Next, polycrystals are etched using an isotropic etching solution.
Etching was performed on the Si 18 until the surface of the Si 3 N 4 film 17 was exposed. Hollow 2 of polycrystalline Si at this time
0 was also approximately 0.3 μm.
(e)：次に、熱酸化を行なつて溝内に充填された多
結晶Siの表面にSiO2膜（厚さ約4000Å）２１
を形成し、表面のSi3N4膜１７を除去し、アイ
ソレーシヨン工程が完了した。(e): Next, thermal oxidation is performed to form a SiO 2 film (about 4000 Å thick) 21 on the surface of the polycrystalline Si filled in the groove.
was formed, the Si 3 N 4 film 17 on the surface was removed, and the isolation process was completed.
(f)：次に、Siエピタキシヤル層６にコレクタ取出
し用拡散層２２、ベース領域２３を形成した
後、表面にパシベーシヨン膜２４を形成した。
次に、エミツタ領域２５を形成し、さらにコレ
クタ電極２６、エミツタ電極２７、ベース電極
２８を設けて、バイポーラトランジスタが完成
した。(f): Next, after forming a collector extraction diffusion layer 22 and a base region 23 on the Si epitaxial layer 6, a passivation film 24 was formed on the surface.
Next, an emitter region 25 was formed, and a collector electrode 26, an emitter electrode 27, and a base electrode 28 were provided to complete the bipolar transistor.
以上説明したように、本発明を用いることによ
つて、容易に分離領域の平坦化が達成され、従来
の複雑なアイソレーシヨン工程が約1/2に短縮さ
れ生産性が著しく向上する。 As explained above, by using the present invention, flattening of the isolation region can be easily achieved, the conventional complicated isolation process can be shortened to about 1/2, and productivity can be significantly improved.
なお、前記実施例では、溝へ埋込む誘電体材料
として多結晶Siを用いているが、その代りに
SiO2等の他の誘電体材料を用いることも可能で
ある。 In the above embodiment, polycrystalline Si is used as the dielectric material buried in the groove, but instead
It is also possible to use other dielectric materials such as SiO2 .
第１図は本発明の原理を説明するための模式的
断面。第２図はAl配線の断線率と窪みの大きさ
の割合との関係を示すグラフ、第３図は本発明に
よる溝形状の選定範囲を示すグラフ、第４図ａ〜
ｆは本発明の一実施例の半導体装置の製造工程説
明図である。
１……半導体基板、２……アイソレーシヨン用
の溝、３……誘電体材料の膜、４……シリコン基
板、５……コレクタ埋込層、６……Siエピタキシ
ヤル層、７……SiO2膜、８……Si3N4膜、９……
Si3N4膜のひさし、１０……斜めのエツチ面、１
１……ほぼ垂直なエツチ面、１２……Si3N4膜の
パターン幅、１３……SiO2膜のパターン幅、１
４……溝の深さ、１５……チヤネルストツパ層、
１６……SiO2膜、１７……Si3N4膜、１８……多
結晶Si（誘電体材料）、１９，２０……窪み、２１
……SiO2膜、Ｗ……溝の開口部の溝、Ｄ……溝
の深さ、Ｈ……誘電体材料の膜厚、Ａ……表面の
窪み。
FIG. 1 is a schematic cross section for explaining the principle of the present invention. Fig. 2 is a graph showing the relationship between the disconnection rate of Al wiring and the proportion of the size of the depression, Fig. 3 is a graph showing the selection range of the groove shape according to the present invention, and Fig. 4 a~
f is an explanatory diagram of the manufacturing process of a semiconductor device according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Isolation groove, 3... Dielectric material film, 4... Silicon substrate, 5... Collector buried layer, 6... Si epitaxial layer, 7... SiO 2 film, 8... Si 3 N 4 film, 9...
Si 3 N 4 film eaves, 10... diagonal etched surface, 1
1... Almost vertical etched surface, 12... Pattern width of Si 3 N 4 film, 13... Pattern width of SiO 2 film, 1
4... Groove depth, 15... Channel stopper layer,
16... SiO 2 film, 17... Si 3 N 4 film, 18... Polycrystalline Si (dielectric material), 19, 20... Hollow, 21
...SiO 2 film, W... Groove at the opening of the groove, D... Depth of the groove, H... Thickness of the dielectric material, A... Indentation on the surface.
Claims (1)
溝内に誘電体材料をCVD法、またはCVD法およ
び熱酸化法を用いて充填して素子間の絶縁分離を
行なう半導体装置において、上記溝の断面形状を 1.0≧Ｈ／Ｄ≧0.1＋0.625（Ｗ／Ｄ）2 但しＷ：溝の開口部の幅 Ｄ：溝の深さ Ｈ：溝の充填時に半導体基板表面に形成される誘
電体材料の膜厚 Ｗ／Ｄ≦1.2 なる条件を満たす範囲内に選んだことを特徴とす
る誘電体分離構造を有する半導体装置。 ２ 上記溝内にSi3N4膜を介して上記誘電体材料
が充填されていることを特徴とする特許請求の範
囲第１項記載の半導体装置。[Claims] 1. A semiconductor in which dielectric material is filled into a groove with a Y-shaped cross section provided in a semiconductor substrate using a CVD method, or a CVD method and a thermal oxidation method to provide insulation separation between elements. In the device, the cross-sectional shape of the above groove is 1.0≧H/D≧0.1+0.625 (W/D) 2 However, W: Width of the groove opening D: Depth of the groove H: When the groove is filled, the cross-sectional shape of the groove is A semiconductor device having a dielectric isolation structure, characterized in that the film thickness of the dielectric material to be formed is selected within a range that satisfies the following condition: W/D≦1.2. 2. The semiconductor device according to claim 1, wherein the groove is filled with the dielectric material via a Si 3 N 4 film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8158382A JPS58199536A (en) | 1982-05-17 | 1982-05-17 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8158382A JPS58199536A (en) | 1982-05-17 | 1982-05-17 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58199536A JPS58199536A (en) | 1983-11-19 |
| JPH0516181B2 true JPH0516181B2 (en) | 1993-03-03 |
Family
ID=13750337
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8158382A Granted JPS58199536A (en) | 1982-05-17 | 1982-05-17 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58199536A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07326663A (en) * | 1994-05-31 | 1995-12-12 | Fuji Electric Co Ltd | Dielectric isolation method of wafer |
| JPH07326664A (en) * | 1994-05-31 | 1995-12-12 | Fuji Electric Co Ltd | Filling method of dielectric isolation trench of wafer |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS564245A (en) * | 1979-06-14 | 1981-01-17 | Ibm | Method of forming embedded oxide isolating region |
-
1982
- 1982-05-17 JP JP8158382A patent/JPS58199536A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS564245A (en) * | 1979-06-14 | 1981-01-17 | Ibm | Method of forming embedded oxide isolating region |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58199536A (en) | 1983-11-19 |
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