JP2553702B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

TECHNICAL FIELD The present invention relates to a semiconductor device used for an SOI type semiconductor device and a manufacturing method thereof.

<< Prior Art >> As a conventional semiconductor device, for example, one shown in FIG. 8 is known. This is the 1988 Extended Abstr
acts of 5th International Warkshop on Future Elec
This is a quotation from tion Device P155, which realizes an SOI substrate by embedding SiO ₂ in a silicon (Si) substrate. The manufacturing process will be described below with reference to FIGS.

In FIG. A, the silicon substrate 1 is thermally oxidized to form the first Si ₃ N ₄
Then, after depositing the first HTO oxide film, the etching mask 2 is formed by photo-etching into a desired shape. After that, trench etching of the silicon substrate 1 is performed by a reactive ion etcher (RIE).

Next, in FIG. B, a thermal oxidation process is performed to form a SiO ₂ film on the sidewalls and bottom surface of the trench, and then a second SiN film and a second HTO oxide film are deposited, and then RIE is used to form a trench. The bottom surface and the etching mask 3 made of the HTO oxide film / SiN film / SiO ₂ film are anisotropically etched to expose the silicon substrate 1 on the bottom surface of the trench. As a result, the etching mask 3 remains on the sidewall of the trench.

Next, in FIG. 3C, the silicon substrate 1 masked by the etching masks 2 and 3 is isotropically etched to form isotropic etching holes 4.

Then, in FIG. D, the silicon substrate 1 is thermally oxidized again,
A thermal oxide film 5 is formed in the etching hole 4 which is not covered with the etching masks 2 and 3, and a silicon island 6 which is dielectrically separated from the silicon substrate 1 is formed.

Finally, in FIG. 5e, after removing the etching masks 2 and 3, the buried oxide film 7 is deposited to form an SOI type semiconductor substrate.

<< Problems to be Solved by the Invention >> However, the SOI semiconductor having such a structure has the following problems.

(1) When performing isotropic etching and thermal oxidation of the trench bottom surface, an etching mask having a three-layer structure must be provided on the sidewall of the trench, which complicates the process, lowers the yield, and increases the unit cost. .

(2) Similarly, since the etching process is isotropic, the variation in the etching amount becomes large within the wafer, within the lot, and between lots. Therefore, in order to avoid overetching, the etching processing time must be kept short, and the upper limit of the width dimension of the silicon island occurs due to the design, so that a silicon island having a large area cannot be formed.

<Object of the Invention> The present invention has been made in order to solve such a conventional problem, and an object of the present invention is to improve a yield, reduce a unit cost, and to provide a semiconductor island having a large area. It is to provide a semiconductor device that can be formed and a method for manufacturing the same.

<< Means for Solving the Problems >> In order to achieve the above object, the present invention provides a semiconductor island electrically connected to a single crystal semiconductor substrate through a dielectric layer. In a semiconductor device having, a semiconductor island is formed from an element formation region formed in a <110> direction of a silicon substrate whose surface is a {110} plane, and the {110} plane and two {111} planes forming a triangular prism. It is characterized by being formed.

The present invention also provides a method for manufacturing a semiconductor device having a semiconductor island electrically insulated from a semiconductor substrate by interposing a dielectric layer on the semiconductor substrate, wherein the surface of the silicon substrate is a {110} plane. Forming a mask pattern of a predetermined width having a <110> direction as a longitudinal direction, and the silicon substrate so that a wall of a {100} plane defined by the mask pattern of the predetermined width and having a predetermined depth from the substrate surface remains And anisotropically etching both walls of the mask portion by using an etching solution having an etching rate of {100} planes higher than that of {111} planes. And a step of forming a dielectric layer by thermal oxidation up to the thickness of.

<< Operation >> This invention uses a semiconductor substrate made of silicon for {11
Since the anisotropic etching is performed using an etching solution having a 0} plane and an etching rate of the {100} plane that is higher than that of the {111} plane, the three main planes are {110}, {111}, and {111). A semiconductor island in the shape of a triangular prism can be formed, and the side etching amount at the lower part of the semiconductor island can be accurately controlled in the forming process.

<< Embodiment >> An embodiment of the present invention will be described below with reference to the drawings.

1 to 4 show a semiconductor device according to a first embodiment of the present invention, FIG. 1 shows a plan view of a part of a semiconductor substrate according to the embodiment, and FIG. 2 shows FIG. 6 is a sectional view taken along line VI-VI of FIG.

In this semiconductor substrate, as shown in FIGS. 1 and 2, a silicon island 31 having a triangular cross section whose longitudinal direction is the <110> direction is formed on the surface of a silicon substrate 34. This Silicon Island
Since the isolation region 32 is formed on the side bottom surface of 31 with the silicon oxide film 33 interposed therebetween, the silicon island 31 is electrically insulated from the silicon substrate.

The surface of the silicon island 31 is the {110} plane of the silicon crystal, and the bottom of the silicon island 31 is the {111} plane. This is a silicon island 31
It is shown that it was formed through a process of etching the bottom of the sample with an alkaline anisotropic etching solution and stopping the etching when the {111} plane was exposed.

Next, a method of manufacturing the semiconductor substrate will be described with reference to FIG.

In FIG. A, first, the silicon substrate 34 is thermally oxidized to form a pad oxide film 35, and the Si ₃ N ₄ film 3 for preventing oxidation is formed on the upper surface thereof.
6. Deposit a mask oxide film 37 for the reactive ion etching mask. After that, the mask oxide film 37, Si
₃ N _{4 The} film 36 and the pad oxide film 35 are photo-etched, and the mask oxide film 3 is formed only on the region where the silicon islands are formed.
7. Si ₃ N ₄ film 36 and pad oxide film 35 are left. Note that, here, the pattern of the mask oxide film 37, the Si ₃ N ₄ film 36, and the pad oxide film 35 is formed on the {110} plane of the silicon crystal on the surface of the silicon substrate 34 with the <110> direction as the longitudinal direction. There is.

Next, as shown in FIG. B, the silicon substrate 34 is subjected to trench etching by using, for example, a reactive ion etcher (RIE) to form a silicon groove 38. At this time, the {100} plane is exposed on the side surface in the longitudinal direction of the trench.

Then, in FIG. C, an alkaline anisotropic etching solution,
The silicon trench 38 is etched using, for example, a potassium hydroxide (KOH) solution. As a result, the anisotropic etching hole 41 surrounded by the {111} plane 41 is formed.

Further, as shown in FIG. 3D, thermal oxidation is performed so that the silicon island 31 is completely dielectrically separated from the silicon substrate 34.
An oxide film 40 is formed, and a silicon island 31 separated from the silicon substrate 34 is formed.

Finally, in FIG. 5e, the anisotropic etching hole 39 is filled with polysilicon, an oxide film or the like to form the isolation region 32, and the surface is further planarized to complete the semiconductor substrate.

FIG. 4 is a diagram for explaining in detail the side etching of the lower part of the silicon island.

As shown in the figure, when the exposed silicon surface {110} of the trench side wall is etched with an alkaline etchant, the {100} surface has a higher etching rate than the {111} surface, so {111} The etching ends when the surface is exposed. Therefore, even if there is etching variation within the wafer, within the lot, or between lots, the etching will stop at the {111} plane, and the variation will be eliminated. It will be possible to match. That is, by using this method, it is possible to form the silicon island 31 with almost no dimensional variation after processing.

Even if the plane orientation of the surface of the silicon substrate is slightly off-angled from the {110} plane, there is no problem in forming the structure of the present invention.

A specific design example will be described below. As shown in the figure, one half of the trench depth is D, the side etch amount at the bottom of the silicon island 31 is d, the length s of the dielectrically isolated portion of the oxide film 40, and the width of the silicon island 31. Let W be W, the oxide film thickness be Tox, and the silicon consumption rate during oxidation be α: W = 2 · d + s d = D · tan θ (θ = 54.7 °) s = 2 · α · Tox (α ‖ 0.45) From the above equation, the relation between W, D and Tox is W = 2 · D · tan θ + 2 · α · Tox.

Here, for example, if processing is performed with Tox = 200 nm and D = 5 μm set, a silicon island 31 with W = 14.3 μm can be obtained.

On the contrary, when it is desired to form the silicon island 31 with a width of 14.3 μm, anisotropic etching is performed after performing trench etching with a depth of 10 μm at intervals of 14.3 μm, and then performing a 200 nm heat treatment. Oxidation would be good.

For comparison, in the case of forming a 7 μm wide silicon island in the conventional example shown in FIG. 8 as well, after performing 6.8 μm isotropic etching in the step of FIG. It must be thermally oxidized to 400 nm. Moreover, in isotropic etching, there is usually a variation of ± 10%, resulting in a variation of about ± 0.7 μm after processing.

As described above, even if a wide silicon island is manufactured by the conventional method, a silicon island having a large dimensional error is formed and it cannot be practically used.

As in this embodiment, the upper surface of the semiconductor substrate is {110}.
Plane, and anisotropic etching using an etchant in which the {100} plane has a higher etching rate than the {111} plane, and the upper surface of the semiconductor substrate is the {100} plane and {110} plane is larger than the {111} plane. In comparison with the case where anisotropic etching is performed using an etching solution having a high surface etching rate, in this embodiment, it is possible to form a silicon island having a width twice that of a trench having the same depth. it can. That is, in the present embodiment, in order to form a silicon island having the same width as in the latter case, the trench etching with a depth of ½ is sufficient, and thus the cost can be significantly reduced.

5 to 7 show a semiconductor device according to a second embodiment of the present invention, FIG. 5 shows a plan view of a part of a semiconductor substrate according to the embodiment, and FIG. 6 shows FIG. 7 is a sectional view taken along line XX of FIG. 7, and FIG. 7 is a sectional view taken along line XI-XI of FIG.

As shown in the figure, this semiconductor substrate has a trench-shaped isolation region 61 formed at both ends of the formation region of the silicon island 51 and having a depth enough to reach the bottom of the silicon island 51. The silicon island 51 is insulated from the substrate 54 by the isolation region 52 formed in.

 The manufacturing method of this embodiment will be briefly described below.

First, both ends of the silicon island formation region on the silicon substrate 54 are
Trench etching is performed by RIE or the like. After that, an insulating film is thinly formed by thermal oxidation or CVD (chemical vapor deposition), and then polysilicon or the like is formed by CVD or the like to completely fill the trench. Next, flattening is performed by a method such as normal etch back. The trench-like isolation region 61 is formed by the above process.

Next, trench etching is performed on both sides of the silicon island formation region by a method such as RIE to expose the {100} plane.

At this time, both ends of the silicon island formation region are formed on the silicon substrate.
It is supported by a separation region 61 formed in 54. Furthermore, anisotropic etching of the side surface of the trench is performed using an alkaline anisotropic etching solution such as potassium hydroxide (KOH), and finally the constriction under silicon island 51 is changed to silicon oxide film 53 by thermal oxidation or the like. By embedding the isolation region 52, the semiconductor device of this embodiment is completed.

In this embodiment, even after the alkali etching step in which the strength of the lower portion of the silicon island 51 is weakened, since both ends of the silicon island are supported, it is possible to completely prevent the silicon island 51 from being damaged during cleaning, etc. It can be greatly improved. As a result, the effect of significantly reducing the cost of the semiconductor device is obtained.

<< Effects of the Invention >> As described above, the present invention has an upper surface of a semiconductor substrate made of silicon as a {110} plane and is anisotropically etched by using an etching solution having a higher etching rate of a {100} plane than a {111} plane. Therefore, the processing steps are simplified, and at the same time, the dimensional accuracy in forming the semiconductor island is improved, the yield in manufacturing the semiconductor device is improved, and the unit cost is reduced.

Further, similarly, since the processing accuracy is improved, a semiconductor island having a large area can be formed, and the degree of freedom in designing the semiconductor substrate can be improved.

[Brief description of drawings]

1 to 4 show a semiconductor device according to a first embodiment of the present invention, FIG. 1 is a plan view of a part of a semiconductor substrate according to the embodiment, and FIG. 2 is a VI-VI of FIG. FIG. 3 is a sectional view taken along the line, FIG. 3 is an explanatory view showing a method for manufacturing a semiconductor substrate, FIG. 4 is an explanatory view of side etching under a silicon island, and FIGS. 5 to 7 relate to a second embodiment of the present invention. FIG. 5 shows a semiconductor device, FIG. 5 is a plan view of a part of a semiconductor substrate according to an embodiment, FIG. 6 is a sectional view taken along line XX of FIG. 5, and FIG. 7 is FIG.
FIG. 8 is a sectional view taken along line XI-XI and FIG. 8 is a manufacturing process diagram of a conventional example. 31 51 51 Silicon island 32 52 Isolation area 33 53 Silicon oxide film 34 54 Silicon substrate 35 Pad oxide film 36 Si ₃ N ₄ film 37 Mask oxide film 38 ...... Silicon trench 39 …… Anisotropic etching hole 40 …… Oxide film 41 …… Silicon surface 61 …… Trench-shaped isolation region

Claims (2)

(57) [Claims] 1. A semiconductor device having a semiconductor island electrically connected to a single crystal semiconductor substrate through a dielectric layer, wherein the surface of the silicon substrate is a {110} plane. A semiconductor device, wherein a semiconductor island is formed from an element formation region formed in the <110> direction and the {110} plane and two {111} planes forming a triangular prism. 2. A method of manufacturing a semiconductor device having a semiconductor island, which is electrically insulated from a semiconductor substrate by interposing a dielectric layer on the semiconductor substrate, comprising: a silicon substrate having a {110} surface. Forming a mask pattern of a predetermined width having a <110> direction as a longitudinal direction, and the silicon substrate so that a wall of a {100} plane defined by the mask pattern of the predetermined width and having a predetermined depth from the substrate surface remains And anisotropically etching both walls of the mask portion by using an etching solution having an etching rate of {100} planes higher than that of {111} planes. And a step of forming a dielectric layer by thermal oxidation up to the thickness of 1. A method of manufacturing a semiconductor device, comprising: