JPH0481329B2 - - Google Patents
Info
- Publication number
- JPH0481329B2 JPH0481329B2 JP57122105A JP12210582A JPH0481329B2 JP H0481329 B2 JPH0481329 B2 JP H0481329B2 JP 57122105 A JP57122105 A JP 57122105A JP 12210582 A JP12210582 A JP 12210582A JP H0481329 B2 JPH0481329 B2 JP H0481329B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- substrate
- etching
- sio
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 claims description 28
- 238000000034 method Methods 0.000 claims description 20
- 238000005530 etching Methods 0.000 claims description 18
- 239000004065 semiconductor Substances 0.000 claims description 17
- 238000002955 isolation Methods 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 239000010408 film Substances 0.000 claims 6
- 239000010409 thin film Substances 0.000 claims 3
- 238000001947 vapour-phase growth Methods 0.000 claims 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 20
- 239000010410 layer Substances 0.000 description 9
- 238000001020 plasma etching Methods 0.000 description 8
- 239000000463 material Substances 0.000 description 6
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- 229910017855 NH 4 F Inorganic materials 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Drying Of Semiconductors (AREA)
- Element Separation (AREA)
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、半導体装置の製造方法に係わり、特
に微細化が進んだ素子分離技術の形成方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming an element isolation technique with advanced miniaturization.
最近、半導体装置製造におけるリソグラフイ技
術、エツチング技術等が進歩し、半導体装置の高
集積化、微細化が一段と進んでいる。半導体装置
の微細化が進むと素子分離領域も微細化されてく
る。従来の選択酸化法（LOCOS）に代わり、Si
基板の素子分離領域をエツチングして凹部を形成
し、その凹部に絶縁膜を埋め込むという新しい素
子分離法（BOX法）が是案されている。第１図
に従来のBOX法の１例を示す。
Recently, lithography technology, etching technology, etc. in semiconductor device manufacturing have progressed, and semiconductor devices are becoming more highly integrated and miniaturized. As semiconductor devices become smaller, element isolation regions also become smaller. Si replaces the traditional selective oxidation method (LOCOS)
A new element isolation method (BOX method) has been proposed in which the element isolation region of the substrate is etched to form a recess and an insulating film is buried in the recess. Figure 1 shows an example of the conventional BOX method.
まず、Si基１に選択的に凹部を形成し、その上
にCVD法により絶縁膜２を全面に形成し、その
上にレジスト３を用いて上を平坦化する（第１図
ａ）。その後、レジスト３と絶縁膜２をエツチン
グ速度が等しいRIE（リアクテイブイオンエツチ
ング）を用いて、半導体基板の凸部表面が露出す
るまでエツチングする（第１図ｂ）。 First, a recess is selectively formed in the Si base 1, an insulating film 2 is formed on the entire surface by CVD, and a resist 3 is used to planarize the upper surface (FIG. 1a). Thereafter, the resist 3 and the insulating film 2 are etched using RIE (reactive ion etching) having an equal etching speed until the surface of the convex portion of the semiconductor substrate is exposed (FIG. 1b).
この方法を用いると凸部の間隔が狭い所（Ａの
所）では、絶縁膜２が完全に埋め込まれ、表面も
平坦化されるが、凸部の間隔が広い所（Ｂの所）
では、レジスト３の膜厚が薄く形成されるために
残置される絶縁膜２も薄くなつてしまい完全な平
坦化も出来ない。さらに、絶縁膜２が薄くなるた
め、配線とSi基板間の容量も増えて半導体装置の
動作速度も遅くなつてしまう。 When this method is used, the insulating film 2 is completely buried and the surface is flattened in places where the intervals between the protrusions are narrow (place A), but in places where the intervals between the protrusions are wide (place B).
In this case, since the resist 3 is formed thin, the remaining insulating film 2 is also thin and cannot be completely flattened. Furthermore, since the insulating film 2 becomes thinner, the capacitance between the wiring and the Si substrate also increases, and the operating speed of the semiconductor device also decreases.
この発明は、上述した従来法の欠点を改良した
もので、完全な平坦化することの出来る素子分離
法を提供することを目的とする。
The present invention improves the drawbacks of the conventional method described above, and aims to provide an element isolation method that can achieve complete planarization.
本発明は半導体基板表面に、選択的に凹凸部を
形成する工程と、前記半導体基板表面の全面に少
なくとも１層以上の絶縁膜を形成する工程と、前
記絶縁膜全面上に前記絶縁膜の耐エツチング性を
有する第２の膜を形成する工程と、前記凸部の少
なくとも第２の膜をエツチングする工程と、前記
凸部を除いて残置された第２の膜をマスクに前記
絶縁膜をエツチングする事により前記半導体基板
の凹部に前絶縁膜を残置させる工程とを具備した
事を特徴とする半導体装置の製造方法である。
The present invention includes a step of selectively forming uneven portions on the surface of a semiconductor substrate, a step of forming at least one layer of an insulating film on the entire surface of the semiconductor substrate, and a step of forming an insulating film on the entire surface of the insulating film. a step of forming a second film having etching properties; a step of etching at least the second film on the convex portion; and a step of etching the insulating film using the second film remaining except for the convex portion as a mask. This method of manufacturing a semiconductor device is characterized by comprising a step of leaving a pre-insulating film in the recessed portion of the semiconductor substrate.
本発明によればフイールド領域の平坦化が達成
され、かつ自己整合により、素子分離領域上に耐
エツチング性マスクを形成出来るので、工程が少
なくて済むと同時に、マスク合せの必要がないの
で、合せずれのための余分の領域を必要としない
ため、微細化が出来る。
According to the present invention, the field region can be flattened, and an etching-resistant mask can be formed on the element isolation region by self-alignment, which reduces the number of steps and eliminates the need for mask alignment. Since no extra area is required for misalignment, miniaturization is possible.
本発明の一実施例を第２図ａ〜ｄを用いて説明
する。まず、たとえば主平面１００のSi基板２１
を用意してその上にたとえば写真蝕刻法を用いて
選択的にマスク材を形成した後、前記マスク材を
マスクにたとえばCF2ガスを含むRIEにより前記
Si基板２１をエツチングして前記Si基板にたとえ
ば0.5μｍの凹部を形成する。
An embodiment of the present invention will be described using FIGS. 2a to 2d. First, for example, the Si substrate 21 on the main plane 100
After preparing a mask material and selectively forming a mask material thereon using, for example, photolithography, the mask material is used as a mask to perform the above-mentioned process by RIE containing, for example, CF 2 gas.
The Si substrate 21 is etched to form a recess of, for example, 0.5 μm in the Si substrate.
その後、マスク材をマスクにフイールド反転層
のイオン注入をSi基板２１中にした後、前記マス
ク材を除去する。その後、例えばSiH4とO2を含
むCVD法により厚さ0.5μｍ程度のSiO2膜２２を
全面に形成する。その後、例えばSiH4ガすを含
むCVD法を用いてSiN膜２３を厚さ0.1μｍ程度形
成する（第２図ａ）。 Thereafter, ions of a field inversion layer are implanted into the Si substrate 21 using the mask material, and then the mask material is removed. Thereafter, a SiO 2 film 22 with a thickness of about 0.5 μm is formed on the entire surface by, for example, a CVD method containing SiH 4 and O 2 . Thereafter, a SiN film 23 having a thickness of about 0.1 μm is formed using, for example, a CVD method containing SiH 4 gas (FIG. 2a).
その後、例えば、ダイヤモンド粉末を用いたブ
レード法により、研磨する事により、凸部の前記
SiN膜２３を除去して凸部のSiO2膜２２を露出さ
せる（第２図ｂ）。 After that, the convex portions are polished by, for example, a blade method using diamond powder.
The SiN film 23 is removed to expose the SiO 2 film 22 in the convex portion (FIG. 2b).
その後、たとえばNH4F液を用いて前記SiN膜
２３をマスクに凸部のSiO2膜２２を選択的にエ
ツチングして、Si基板２１表面が露出するまでエ
ツチングする（第２図ｃ）。 Thereafter, the SiO 2 film 22 in the convex portions is selectively etched using, for example, an NH 4 F solution using the SiN film 23 as a mask until the surface of the Si substrate 21 is exposed (FIG. 2c).
その後、例えばリン酸を用いて前記SiN膜２３
を除去する（第２図ｄ）。するとSi基板２１の凹
部のみにSiO2膜２２が残置される。 After that, the SiN film 23 is removed using, for example, phosphoric acid.
(Fig. 2d). Then, the SiO 2 film 22 is left only in the recessed portion of the Si substrate 21.
本発明によれば、自己整合により、素子分離領
域上に耐エツチング性マスクを形成出来るので、
工程が短かくして済むと同時に、マスク合せの必
要がないので、合せずれのための余分の領域を必
要としないため、微細化が出来る。 According to the present invention, an etching-resistant mask can be formed on the element isolation region by self-alignment.
The process can be shortened, and at the same time, since there is no need for mask alignment, there is no need for extra areas for misalignment, so miniaturization can be achieved.
また平坦化する時のエツチングする材料が１層
のため、エツチング条件の制限がなくなり許容範
囲が広がるため、高速なRIEが用いる事が出来
る。 Furthermore, since there is only one layer of material to be etched during planarization, there are no restrictions on etching conditions and the tolerance range is widened, so high-speed RIE can be used.
また、RIEを用いた時にSi基板までエツチング
された時にSi基板表面にダメージ層を形成し、半
導体装置の特性を劣化させる事があり、このダメ
ージ層を除去する工程が増加するが、本発明で
は、RIE等のダメージ層を形成するエツチング法
を用いる事なく平坦なエツチングが出来る。すな
わち湿式エツチング（エツチング液を用いる方
法）だけで済むので簡単でありダメージ層を形成
する事がない。そのために高価なRIE装置を用い
なくても済む。 Furthermore, when using RIE, when the Si substrate is etched, a damaged layer may be formed on the surface of the Si substrate, deteriorating the characteristics of the semiconductor device, and the process of removing this damaged layer is increased. , flat etching can be performed without using etching methods such as RIE that form damaged layers. In other words, only wet etching (method using an etching solution) is required, which is simple and prevents the formation of a damaged layer. Therefore, there is no need to use an expensive RIE device.
また素子分離領域のSiO2２２のRIEを行なわな
いために、SiO2膜厚のバラツキの増大およびオ
ーバーエツチングによる膜圧の減少を無くす事が
出き、プロセス制御が容易となり、半導体装置の
特性の均一化が計れるとともに歩留り向上にな
る。 Furthermore, since RIE of SiO 2 22 in the element isolation region is not performed, it is possible to eliminate increases in variation in SiO 2 film thickness and decreases in film thickness due to overetching, making process control easier and improving the characteristics of semiconductor devices. Uniformity can be measured and yield can be improved.
第３図ａ，ｂは本発明の別の実施例を示したも
のである。まず、Si基板３１に選択的に0.5μｍの
凹部を形成した後、例えば1.0μｍのSiO2膜３２を
形成した後、例えばNH4F液でSiO2膜３２をエツ
チングして（破線Ａ）Si基板３１と同じ寸法に
SiO2膜３２を形成した後（第３図ａ）、例えば
0.1μｍのSiN膜３３を形成した後、例えばブレー
ド法により、凸部のSin膜３３を除去した後、例
えばNH4F液を用いてSiN膜３３をマスクにSiO2
膜３２をSi基板が露出するまでエツチングする
（第３図ｂ）。その後、例えばリン酸を用いて、
SiN膜３３を除去すればSi基板の凹部にSi基板よ
りも高いSiO2膜３２を形成する事が出来る。 Figures 3a and 3b show another embodiment of the invention. First, after selectively forming a 0.5 μm recess in the Si substrate 31 and forming, for example, a 1.0 μm SiO 2 film 32, the SiO 2 film 32 is etched with, for example, NH 4 F solution (broken line A). Same dimensions as board 31
After forming the SiO 2 film 32 (FIG. 3a), for example
After forming the SiN film 33 with a thickness of 0.1 μm, remove the Si film 33 on the convex portions by, for example , a blade method .
The film 32 is etched until the Si substrate is exposed (FIG. 3b). Then, using e.g. phosphoric acid,
By removing the SiN film 33, it is possible to form an SiO 2 film 32 in the concave portion of the Si substrate, which is higher in thickness than the Si substrate.
この方法を用いる事により、埋め込む絶縁膜を
Si基板より高く形成する事が容易に出来る。この
高くSiO2を埋め込む事により、Si基板凸部の周
辺での電界集中を防止する事が出来る。このため
に、Si基板凸部の周辺に出来る寄生トランジスタ
が形成出来ないようになり、半導体装置の特性の
劣化を防止できる。 By using this method, the buried insulating film can be
It can be easily formed higher than a Si substrate. By embedding SiO 2 to this high level, it is possible to prevent electric field concentration around the protrusions of the Si substrate. This prevents the formation of parasitic transistors around the convex portions of the Si substrate, thereby preventing deterioration of the characteristics of the semiconductor device.
また、SiO2埋め込み後の工程によるSiO2膜の
膜厚減りの分だけ、あらかじめ厚くSiO2を形成
出来る事になる。 Furthermore, SiO 2 can be formed thicker in advance by an amount corresponding to the reduction in the thickness of the SiO 2 film due to the step after SiO 2 embedding.
第４図は本発明の別の実施例である。 FIG. 4 shows another embodiment of the invention.
Si基板４１に凹部を形成する時に例えばKOH
液を用いてSi基板４１をエツチングする事によ
り、凹部の側面の角度を垂直から斜めに形成した
だけで後の工程は第２図と同一である。 When forming a recess in the Si substrate 41, for example, KOH
The subsequent steps are the same as those shown in FIG. 2, except that the angle of the side surfaces of the recesses is changed from vertical to oblique by etching the Si substrate 41 using a liquid.
この方法によれば、SiO2膜４２を形成した時、
Si基板４１の凹部の寸法が微細な時に発生する
SiO2の密度のうすい所（凹部中央に発生する）
が形成されなくなる。つまり、後の工程でSiO2
膜４２の中央部がエツチング速度が速いために凹
部になる事を防止した方法である。この方法を用
いれば信頼性の高い、微細な素子分離が形成出来
る。 According to this method, when the SiO 2 film 42 is formed,
Occurs when the dimensions of the recess in the Si substrate 41 are minute.
Places where SiO 2 density is low (occurs in the center of the recess)
is no longer formed. In other words, in the later process SiO 2
This method prevents the central part of the film 42 from becoming a recess due to the high etching speed. Using this method, highly reliable and fine element isolation can be formed.
上記実施例において、絶縁膜としてSiO2を用
いたが、他の絶縁膜を用いても良く、SiNや
Al2O3やBSG、PSG、AsSG、BPSG等の一層あ
るいはこれらの積層としても良い。 In the above example, SiO 2 was used as the insulating film, but other insulating films may be used, such as SiN or
It may be a single layer of Al 2 O 3 , BSG, PSG, AsSG, BPSG, etc., or a stack of these layers.
第２の膜としては、SiNを用いたが、絶縁膜の
耐エツチング性があれば良く、Poly−Si、Al、
Ｗ、等の一層あるいは積層を用いれば良い。 Although SiN was used as the second film, it is sufficient as long as it has etching resistance as an insulating film, such as poly-Si, Al,
A single layer or a laminated layer of W, etc. may be used.
また、第２の膜は除去したが、必要ならば少な
くとも一部を残置させておいても良い。後の工程
でのSiO2膜等の絶縁膜の膜減りを防止出来る。 Further, although the second film was removed, at least a portion may be left if necessary. It is possible to prevent thinning of insulating films such as SiO 2 films in later processes.
第１図ａ，ｂは従来法を示した断面図、第２図
ａ〜ｄ、第３図ａ，ｂ及び第４図は本発明の実施
例を示した断面図である。
図において、１，２１，３１，４１……Si基
板、２，２２，３２，４２……SiO2膜、３……
レジスト、２３，３３，４３……SiN膜。
1A and 1B are sectional views showing the conventional method, and FIGS. 2A to 2D, 3A and 3B, and 4 are sectional views showing an embodiment of the present invention. In the figure, 1, 21, 31, 41... Si substrate, 2, 22, 32, 42... SiO 2 film, 3...
Resist, 23, 33, 43...SiN film.
Claims (1)
凸部を形成する工程と、この半導体基板上に気相
成長で前記凹凸部の段差以上の膜厚の厚い絶縁膜
を形成する工程と、この絶縁膜上に気相成長で前
記絶縁膜に対して耐エツチング性を有する薄膜を
形成する工程と、ラツピングを行つて前記凸部上
に形成された耐エツチング性を有する薄膜及び前
記厚い絶縁膜の一部を除去する工程と、残置され
た前記耐エツチング性を有する薄膜をマスクに前
記絶縁膜を溶液エツチングする事により前記半導
体基板の凹部に前記厚い絶縁膜を残置させて素子
分離絶縁膜を形成する工程とを具備したことを特
徴とする半導体装置の製造方法。1. A step of forming an uneven portion having recesses with different widths on the surface of a semiconductor substrate, a step of forming a thick insulating film having a thickness equal to or larger than the step of the uneven portion on this semiconductor substrate by vapor phase growth, and A step of forming a thin film having etching resistance on the insulating film by vapor phase growth, and wrapping the thin film having etching resistance formed on the convex portion and a part of the thick insulating film. and a step of solution-etching the insulating film using the remaining etching-resistant thin film as a mask to leave the thick insulating film in the concave portion of the semiconductor substrate to form an element isolation insulating film. A method for manufacturing a semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12210582A JPS5913342A (en) | 1982-07-15 | 1982-07-15 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12210582A JPS5913342A (en) | 1982-07-15 | 1982-07-15 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5913342A JPS5913342A (en) | 1984-01-24 |
| JPH0481329B2 true JPH0481329B2 (en) | 1992-12-22 |
Family
ID=14827761
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12210582A Granted JPS5913342A (en) | 1982-07-15 | 1982-07-15 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5913342A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS618945A (en) * | 1984-06-25 | 1986-01-16 | Nec Corp | Semiconductor integrated circuit device |
| US5173439A (en) * | 1989-10-25 | 1992-12-22 | International Business Machines Corporation | Forming wide dielectric-filled isolation trenches in semi-conductors |
| KR100444311B1 (en) * | 1997-06-28 | 2004-11-08 | 주식회사 하이닉스반도체 | Method for manufacturing isolation layer of semiconductor device using two-step cmp processes |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5363871A (en) * | 1976-11-18 | 1978-06-07 | Matsushita Electric Ind Co Ltd | Production of semiconductor device |
-
1982
- 1982-07-15 JP JP12210582A patent/JPS5913342A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5363871A (en) * | 1976-11-18 | 1978-06-07 | Matsushita Electric Ind Co Ltd | Production of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5913342A (en) | 1984-01-24 |
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