JP2001196454A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for forming a self-aligned contact having a sacrificial filling stud. SOLUTION: This method for manufacturing a semiconductor device comprises: a step of providing a semiconductor substrate 20 having a conductor, a step of forming dielectric caps 28 on the conductor, a step of forming spacers 30 on the dielectric caps 28 and the sidewalls of the conductor, a step of forming dielectric liners 32 on the spacers 30 and the conductor, a step of forming a sacrificial layer, a step of forming insulating layers 38 whose material is different from that of the dielectric liner 32 and filling openings, a step of removing filling studs, a step of partially removing the dielectric liner 32 which is positioned on the substrate and between the spacers 30, and a step of making electronic connection with the substrate by forming a conducting layer 39 on the insulating layers 38 and filling a contact hole.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to self-consistency (self-consistency).
The present invention relates to a method for fabricating a semiconductor device for forming a self-aligned contact with sacrificial fill-in studs.

[0002]

2. Description of the Related Art The self-aligned contact (SAC) process involves a deep sub-micron I
Widely used in the production of C. In this step, the process window of light exposure can be reduced, and the size of the chip can be reduced by reducing the size of the cell.

FIGS. 1 to 3 are sectional views showing a conventional SAC process. The process starts with providing a semiconductor substrate 2 with conductive lines. The conductor comprises a silicon oxide layer 4, a polysilicon layer 6, and a tungsten silicide layer, as shown in FIG.
silicide line) 8. Next, after forming a SiN cap 10 located on the top of the conductor and a SiN spacers 12 located on the side wall of the conductor, an inter layer dielectric 14 is formed.
(Eg, an oxide layer) is deposited between and on top of the wires. Then, referring to FIG. 2, a contact hole 16 is formed by a light exposure process, and in order to open the contact hole where the loss of the SiN cap 10 and the SiN spacer 12 is minimized, a high oxide (Si oxide) to SiN selectivity is used. -SiN selectivity) oxidation etching recipe (recipe) (usually fluorocarbon gas chemistry (ca
rbon fluoride gas chemisty)). As shown in FIG. 3, the conductive layer 18 is used to fill the opened contact hole 16 and the dielectric layer 14
Etchback or CMP (chemical mecha) to remove excess portions of conductive layer 18 located on top of
nical planarization) is performed. To preserve the proper insulation plugs and wires, use Si
It is necessary to minimize the loss of the N cap 10 and the SiN spacer 12.

[0004] An ideal SAC etch requires an oxide etch recipe with a high selectivity of silicon oxide-SiN (> 20), and meeting this practice is a very challenging goal. If the SiN located at the apex and side walls of the conductor is lost to some extent, the conductor is too thin to provide a sufficient insulating layer. Therefore, an electrical short occurs between the plug and the conductive wire, resulting in a failure of the contact. 4 and 5 show an ideal situation and a more realistic situation after the SAC process, respectively. Due to the reduced line or space design rules, the length of the SiN spacers around the conductors is reduced, which is a greater challenge in performing SAC etching. Since it is difficult to significantly improve the selectivity of SAC etching, new process flows for SAC formation have been proposed to solve this problem.

[0005]

As described above, the present invention provides:
It is an object of the present invention to provide a method of manufacturing a semiconductor device in which a self-aligned contact having a sacrificial filling stud is formed.

[0006]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method comprising: providing a semiconductor substrate having a conductive line; and forming a dielectric cap on the conductive line. Forming sacrificial filling studs to form openings between the steps of: forming a spacer on the sidewalls of the dielectric cap and the conductor; and forming a dielectric liner on the spacer and the conductor. Forming and providing a sacrificial layer, forming an insulating layer having a material different from that of the guide liner on the sacrificial layer, filling the opening, and forming a contact hole. Removing said filling studs and said dielectric layer located on said substrate and between said spacers through said contact holes. Manufacturing a semiconductor device, comprising: a step of removing a part of the contactor; and a step of forming a conductive layer on the insulating layer and filling a contact hole to electronically connect to the substrate. Is the way.

According to a second aspect of the present invention, in the method of manufacturing a semiconductor device according to the first aspect, the conductive wire includes a silicon oxide liner, a polysilicon layer, and a tungsten silicide layer. Is a method for manufacturing a semiconductor device comprising:

According to a third aspect of the present invention, in the method of manufacturing a semiconductor device according to the first aspect, the dielectric cap, the spacer, and the dielectric liner are made of SiO ₂ , SiN, SiO
This is a method for manufacturing a semiconductor device made of N, Al ₂ O ₃ , or SiC.

According to a fourth aspect of the present invention, in the method of manufacturing a semiconductor device according to the first aspect of the present invention, the semiconductor device is polished by a CMP process to remove an upper portion of the insulating layer. And a step of exposing the sacrificial filling stud to light.

According to a fifth aspect of the present invention, in the method of manufacturing a semiconductor device according to the first aspect of the present invention, the sacrificial filling stud is removed by isotropic dry etching or wet etching. And etching the sacrificial filling stud back.

According to a sixth aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the first aspect, wherein a part of the dielectric liner located on the substrate and located between the spacers is removed. And a method of manufacturing a semiconductor device performed by an anisotropic RIE process.

According to a seventh aspect of the present invention, in the method of manufacturing a semiconductor device, the semiconductor device according to the first aspect is polished by a CMP process to remove an upper portion of the conductive layer. And a method of manufacturing a semiconductor device in which the insulating layer is exposed such that an insulating plug is formed.

[0013] According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: providing a semiconductor substrate having a conductive wire; forming an induction cap on the conductive wire; Forming a dielectric liner on the conductor, forming a spacer on the side wall of the dielectric liner, and forming a sacrificial layer to form the sacrificial fill stud forming an opening therebetween. A step of forming an insulating layer different from that of the guide liner in the sacrificial layer to fill the opening; removing the filling stud to form a contact hole; and Removing a portion of the dielectric liner between the spacer and the substrate; forming a conductive layer on the insulating layer; By filling the Tohoru,
Electronically connecting the substrate to the substrate.

According to a ninth aspect of the present invention, in the method of manufacturing a semiconductor device according to the ninth aspect, the conductive wire is formed of a silicon oxide liner, a polysilicon layer, and a tungsten silicide layer. This is a method for manufacturing a semiconductor device.

According to a tenth aspect of the present invention, in the method of manufacturing a semiconductor device according to the eighth aspect, the dielectric cap, the spacer, and the dielectric liner are made of SiO ₂ , SiN, SiO
This is a method for manufacturing a semiconductor device made of N, Al ₂ O ₃ , or SiC.

According to the present invention, in the method of manufacturing a semiconductor device according to the present invention, the semiconductor device is polished by a CMP process to remove an upper portion of the insulating layer. And a step of exposing the sacrificial filling stud to light.

According to a twelfth aspect of the present invention, in the method of manufacturing a semiconductor device according to the ninth aspect, the removal of the sacrificial filling stud is performed by isotropic dry etching or wet etching. A method of manufacturing a semiconductor device, which is performed by etching back the sacrificial filling stud using the method.

According to a thirteenth aspect of the present invention, in the method of manufacturing a semiconductor device, a part of the dielectric liner between the spacer and the substrate is removed. And a method of manufacturing a semiconductor device performed by an anisotropic RIE process.

According to a fourteenth aspect of the present invention, in the method of manufacturing a semiconductor device, the semiconductor device according to the eighth aspect is polished by a CMP process to remove an upper portion of the conductive layer. And a method of manufacturing a semiconductor device in which the insulating layer is exposed such that an insulating plug is formed.

According to a fifteenth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: providing a semiconductor substrate having a conductor; forming an induction cap on the conductor; Forming a first dielectric liner on the conductive line, forming a second dielectric liner on the second dielectric liner, and forming the sacrificial fill stud to form an opening therebetween; A step of forming a sacrificial layer, a step of forming an insulating layer different from that of the induction liner in the sacrificial layer to fill the opening, and a step of removing the filling stud to form a contact hole. Removing a portion of the first dielectric liner and a portion of the second dielectric liner between the conductive line and the substrate through the contact hole. Extent and, by filling the formed contact hole conductive layer on the insulating layer, a method of manufacturing a semiconductor device comprising the steps of connecting electronically to the substrate, in that it consists of.

According to a sixteenth aspect of the present invention, in the method of manufacturing a semiconductor device according to the fifteenth aspect, the dielectric cap, the first dielectric liner,
And the second dielectric liner is SiO ₂ , S
This is a method for manufacturing a semiconductor device made of iN, SiON, Al ₂ O ₃ , or SiC.

According to a seventeenth aspect of the present invention, in the method of manufacturing a semiconductor device according to the fifteenth aspect, the semiconductor device is polished by a CMP process to remove an upper portion of the insulating layer. And a step of exposing the sacrificial filling stud to light.

In the method of manufacturing a semiconductor device according to the present invention, the sacrificial filling stud may be removed by isotropic dry etching or wet etching. And etching the sacrificial filling stud back.

According to a nineteenth aspect of the present invention, in the method of manufacturing a semiconductor device according to the fifteenth aspect, the first method is provided on the substrate and between the conductive wires.
The removal of a part of the dielectric liner and a part of the second dielectric liner is a method of manufacturing a semiconductor device performed by an anisotropic RIE process.

According to a twentieth aspect of the present invention, in a method of manufacturing a semiconductor device according to the fifteenth aspect, the semiconductor device is polished by a CMP process to remove an upper portion of the insulating layer. And a method of manufacturing a semiconductor device in which the insulating layer is exposed such that an insulating plug is formed.

According to the present invention, a method for manufacturing a semiconductor device includes the following steps. First, a semiconductor substrate provided with a conductive wire is provided. The conductor is a silicon oxide layer, a polysilicon layer,
And a tungsten silicide layer. Next, a dielectric cap is formed over the conductor. The conductor is then constituted by the formation of a silicon oxide layer, a polysilicon layer, a tungsten silicide layer, and a dielectric cap by a light exposure and etching process. Then, spacers are formed on the dielectric cap and the side walls of the conductor. Then, a dielectric liner is conformally formed on the spacer and the conductor. Sacrificial layer (sacrif
icial layer) is deposited on the dielectric liner. The sacrificial layer is provided to form a sacrificial fill stud with an opening formed therebetween. The insulating layer made of different materials from the dielectric liner
The opening is filled by depositing on the sacrificial layer. C
The sacrificial fill stud is exposed by polishing the top of the insulating layer by MP (Chemical Mechanical Planarization). The sacrificial filling stud is removed by etching back, thereby forming a contact hole. A portion of the dielectric liner located on the substrate and between the spacers is a reactive ion etch (RIE).
Anisotropic etching is performed by g) to expose the substrate. Finally, a conductive layer is electronically coupled to the substrate by depositing on the insulating layer and filling the contact holes.
Polishing the upper portion of the conductive layer by CMP exposes the insulating layer to form an insulating plug.

According to the above process flow, appropriate insulation can be achieved without the need for a SAC RIE recipe having a high selectivity of silicon oxide-SiN. The thickness of the dielectric cap on the conductor can be minimized to reduce the aspect ratio, thereby achieving better dielectric cap filling. In the above process flow, no extra photomask is required. SiN caps or SiN spacers can substitute oxide to reduce the coupling capacitance between the plug and the conductor.

[0028]

BEST MODE FOR CARRYING OUT THE INVENTION In order to further clarify the above-mentioned objects, features and advantages of the present invention, preferred embodiments of the present invention will be described below with reference to the drawings.

The present invention provides a method for forming a self-aligned contact having sacrificial filled studs.

(Embodiment 1) In this embodiment 1,
First, a semiconductor substrate having a conductive wire is provided. As shown in FIG. 6, the conductor comprises a silicon oxide layer 22, a polysilicon layer 24, and a tungsten silicide layer 26.
The silicon oxide layer 22 is preferably formed from silicon oxide by a thermal oxidation process. The polysilicon layer 24 and the tungsten silicide layer 26 are continuously formed on the silicon oxide layer 22 by a PECVD (Plasma Enhanced Chemical Vapor Deposition) process.

Next, a dielectric cap 28 is formed over the conductor. The thickness of the dielectric cap 28 is about 200-2500 °
And PECVD or LPCVD
(Low pressure chemical vapor deposition) process, SiO ₂ , SiN, S
It is preferably formed of iON, Al ₂ O ₃ , or SiC. The conductor is then formed by the formation of a silicon oxide layer 22, a polysilicon layer 24, a tungsten silicide layer 26, and a dielectric cap 28 by light exposure and etching steps. Then, the spacer 30 is formed on the dielectric cap 28 and the side wall of the conductive wire. The thickness of the spacer 30 is in the range of about 100-600 °, and as shown in FIG.
By etching back after the CVD process, S
It is preferably formed of iO ₂ , SiN, SiON, Al ₂ O ₃ , or SiC. Then, dielectric liner 32
Are formed conformally on the spacer 30 and the conductor. The thickness of the dielectric liner 32 is in the range of about 100-400 ° and is made of SiO ₂ , SiN, SiON, Al ₂ O ₃ , or S ₂ by a PECVD or LPCVD process.
Preferably, it is formed of iC.

Referring to FIG. 7, a sacrificial layer of polysilicon is deposited over dielectric liner 32. The sacrificial layer is provided to form sacrificial filling studs 34 with openings 36 formed therebetween. Spacer 30 and dielectric liner 32 are sharp corners around the bottom of the wire.
A polysilicon stringer that can prevent the formation of
Prevent formation during polysilicon RIE.

Referring to FIG. 8, 1000 to 8000 °
Guide liner 3 such as a silicon oxide layer
An insulating layer 38 of two different materials is deposited on the sacrificial layer and fills the openings 36 by PECVD or a spin-on process.

The sacrificial filling stud 34 is exposed by polishing the upper portion of the insulating layer 38 by CMP. This is the platen speed
Process parameters such as pressure, back pressure, pad type, and slurry type to adjust the removal rate (remo
val rate), uniformity, and selectivity. The result is shown in FIG.

Referring to FIG. 9, the sacrificial fill stud 34 is etched back by isotropic dry or wet etching to remove it, thereby forming a contact hole 37.

Referring to FIG. 10, the portion of the dielectric liner 32 located on the substrate 20 and between the spacers 30 is anisotropically etched by RIE,
Expose 0.

Lastly, referring to FIG. 11, a conductive layer 39 such as a polysilicon layer or a tungsten layer is deposited on the insulating layer by a sputtering process to form a contact hole 3.
By filling 7, it is electronically connected to the substrate 20. Then, the upper portion of the conductive layer 39 is polished by CMP to expose the insulating layer 38 such that an insulating plug is formed.

(Embodiment 2) FIGS. 12 to 17 show:
A second embodiment of the present invention is shown.

The present embodiment starts with providing a semiconductor substrate 40 having conductive wires. As shown in FIG. 12, the conductive wires are a silicon oxide layer 42, a polysilicon layer 44,
And a tungsten silicide layer 46. The silicon oxide layer 42 is preferably formed from silicon oxide by a thermal oxidation process. The polysilicon layer 44 and the tungsten silicide layer 46 are continuously formed on the silicon oxide layer 42 by a PECVD process.

Next, a dielectric cap 48 is formed on the conductor. The thickness of the dielectric cap 48 is about 200-2500Å
And PECVD or LPCVD
Depending on the process, SiO ₂ , SiN, SiON, Al ₂ O ₃ ,
Alternatively, it is preferably formed of SiC. The conductor is then formed by the formation of a silicon oxide layer 42, a polysilicon layer 44, a tungsten silicide layer 46, and a dielectric cap 48 by a light exposure and etching process. Then, a dielectric liner 50 is conformally formed on the conductor. The thickness of the dielectric liner 50 is about 100 to 400
ＰＥ and PECVD or LPCV
D ₂ process, SiO ₂ , SiN, SiON, Al
_It is preferably formed of ₂ O ₃ or SiC. And, the spacer 52 is formed on the side wall of the dielectric liner 50 of the conductive wire. The thickness of the spacer 52 is about 100 to 6
As shown in FIG. 12 and by etching back after the PECVD or LPCVD step, SiO ₂ , SiN, SiON,
It is preferably formed of Al ₂ O ₃ or SiC.

Referring to FIG. 13, a sacrificial layer of polysilicon is deposited over dielectric liner 50 and spacers 52. The sacrificial layer is provided to form a sacrificial filling stud 54 such that an opening 56 is formed therebetween. The dielectric liner 50 and spacer 52 are formed of polysilicon stringers that can prevent the formation of acute angles around the bottom of the conductor.
Prevent formation during polysilicon RIE.

Referring to FIG. 14, 1000 to 8000
An insulating layer 58 of Å thickness and of a different material from the inductive liner 50, such as a silicon oxide layer, is deposited on the sacrificial layer and fills the openings 56 by a PECVD or spin-on process.

The sacrificial filling stud 54 is exposed by polishing the upper part of the insulating layer 58 by CMP. This can be achieved by adjusting process parameters such as platen speed, back pressure, pad type, and slurry type to meet the required removal, uniformity, and selectivity requirements of the process. The result is shown in FIG.

Referring to FIG. 15, sacrificial fill stud 54 is etched back by isotropic dry etching or wet etching to remove, thereby forming contact hole 57.

Referring to FIG. 16, the portion of the dielectric liner 50 located on the substrate 40 and between the spacers 52 is anisotropically etched by RIE,
Expose 0.

Finally, referring to FIG. 17, a conductive layer 59 such as a polysilicon layer or a tungsten layer is deposited on the insulating layer by a sputtering process to form a contact hole 5.
By filling 7, it is electronically connected to the substrate 40. Then, the upper portion of the conductive layer 59 is polished by CMP to expose the insulating layer 58 such that an insulating plug is formed.

(Embodiment 3) FIGS. 18 to 23 show:
A third embodiment of the present invention is shown.

The present embodiment starts with providing a semiconductor substrate 60 having conductive lines. As shown in FIG. 18, the conductive wires are a silicon oxide layer 62, a polysilicon layer 64,
And a tungsten silicide layer 66. The silicon oxide layer 62 is preferably formed from silicon oxide by a thermal oxidation process. The polysilicon layer 64 and the tungsten silicide layer 66 are continuously formed on the silicon oxide layer 62 by a PECVD process.

Next, a dielectric cap 68 is formed over the conductor. The thickness of the dielectric cap 68 is about 200-2500 °
And PECVD or LPCVD
Depending on the process, SiO ₂ , SiN, SiON, Al ₂ O ₃ ,
Alternatively, it is preferably formed of SiC. The conductor is then constituted by the formation of a silicon oxide layer 62, a polysilicon layer 64, a tungsten silicide layer 66, and a dielectric cap 68 by a light exposure and etching process. Then, the first dielectric liner 70 and the second dielectric liner 72 are formed continuously and conformally on the conductor. First
Preferably, the thickness of the dielectric liner 70 is in the range of about 100-600 ° and is formed of SiN by a PECVD or LPCVD process. The thickness of the second dielectric liner 72 is in the range of about 100-600 ° and, as shown in FIG.
Preferably, it is formed of SiO ₂ by a CVD process.

Referring to FIG. 19, a sacrificial layer of polysilicon is deposited over second dielectric liner 72. The sacrificial layer is provided to form sacrificial filling studs 74 between which openings 76 are formed. The first dielectric liner 70 and the second dielectric liner 72 prevent a polysilicon stringer, which may prevent forming an acute angle around the bottom of the conductor, from forming during the polysilicon RIE.

Referring to FIG. 20, 1000 to 8000
An insulating layer 78 of different thickness from the first inductive liner 70, such as a silicon oxide layer, is deposited on the sacrificial layer and PECVD or spin-on.
The opening 76 is filled by the ON process.

The sacrificial filling stud 74 is exposed by polishing the upper part of the insulating layer 78 by CMP. This can be achieved by adjusting process parameters such as platen speed, back pressure, pad type, and slurry type to meet the required removal, uniformity, and selectivity requirements of the process. The result is shown in FIG.

Referring to FIG. 21, sacrificial filling stud 54 is etched back by isotropic dry etching or wet etching to remove it, thereby forming contact hole 77.

Referring to FIG. 22, portions of the first dielectric liner 70 and the second dielectric liner 72 on the substrate 60
Anisotropic etching is performed by RIE, and the substrate 60 is exposed.

Finally, referring to FIG. 23, a conductive layer 79 such as a polysilicon layer or a tungsten layer is deposited on the insulating layer by a sputtering process to form a contact hole 7.
By filling 7, it is electronically connected to the substrate 60. Then, the upper portion of the conductive layer 79 is polished by CMP to expose the insulating layer 78 to form an insulating plug.

The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing steps of a process according to a known technique.

FIG. 2 is a cross-sectional view showing steps of a process according to the related art.

FIG. 3 is a cross-sectional view showing steps of a process according to a known technique.

FIG. 4 is a cross-sectional view showing an ideal situation after the SAC process.

FIG. 5 is a sectional view showing an actual situation after the SAC step.

FIG. 6 is a cross-sectional view illustrating a step in Embodiment 1.

FIG. 7 is a cross-sectional view illustrating a step in the first embodiment.

FIG. 8 is a cross-sectional view illustrating a process in Embodiment 1.

FIG. 9 is a cross-sectional view illustrating a step in Embodiment 1.

FIG. 10 is a cross-sectional view illustrating a process in Embodiment 1.

FIG. 11 is a cross-sectional view illustrating a process in Embodiment 1.

FIG. 12 is a cross-sectional view illustrating a step in Embodiment 2.

FIG. 13 is a cross-sectional view illustrating a step in Embodiment 2.

FIG. 14 is a cross-sectional view illustrating a process in Embodiment 2.

FIG. 15 is a cross-sectional view illustrating a step in Embodiment 2.

FIG. 16 is a cross-sectional view illustrating a step in Embodiment 2.

FIG. 17 is a cross-sectional view illustrating a step in Embodiment 2.

FIG. 18 is a cross-sectional view illustrating a step in Embodiment Mode 3.

FIG. 19 is a cross-sectional view illustrating a step in Embodiment Mode 3.

FIG. 20 is a cross-sectional view illustrating a step in Embodiment Mode 3.

FIG. 21 is a cross-sectional view illustrating a step in Embodiment Mode 3.

FIG. 22 is a cross-sectional view illustrating a step in Embodiment Mode 3.

FIG. 23 is a cross-sectional view illustrating a step in Embodiment Mode 3.

[Explanation of symbols]

2, 20, 40, 60 semiconductor substrates, 4, 22, 42,
62 silicon oxide layer, 6, 24, 44, 64 polysilicon layer, 8, 26, 46, 66 tungsten silicide layer, 10 SiN cap, 12 SiN spacer, 14 interlayer dielectric layer, 16, 37, 57 contact hole, 18, 39, 59, 79 conductive layer, 28, 4
8,68 dielectric cap, 30,52 spacer, 3
2,50 dielectric liner, 34,54,74 sacrificial filling stud, 36,56 opening, 38,58,
78 insulating layer, 70 first dielectric liner, 72 second dielectric liner.

Continued on the front page F-term (reference) 4M104 BB01 BB18 CC01 CC05 DD02 DD04 DD07 DD08 DD09 DD15 DD16 DD17 DD18 DD75 EE05 EE09 EE14 EE16 EE17 FF14 HH20 5F033 HH04 HH28 JJ04 JJ19 KK01 MM07 MM15 Q19 Q16 Q19 Q19 Q18 RR01 RR03 RR04 RR06 RR08 SS13 SS15 SS21 TT08 XX31

Claims (20)

[Claims] A step of providing a semiconductor substrate having a conductive line; a step of forming a dielectric cap on the conductive line; a step of forming a spacer on a side wall of the dielectric cap and the conductive line; Forming a dielectric liner on the line; forming and providing a sacrificial layer to form a sacrificial fill stud that forms an opening therebetween; and Forming an insulating layer different from that of the liner and filling the opening; removing the filling stud to form a contact hole; and positioning the spacer on the substrate through the contact hole. Removing a portion of the dielectric liner in between; forming a conductive layer on the insulating layer and contacting By filling Lumpur, a step of connecting electronically to the substrate,
A method for manufacturing a semiconductor device, comprising: 2. The method according to claim 1, wherein the conductor comprises a silicon oxide liner, a polysilicon layer, and a tungsten silicide layer. 3. The dielectric cap, the spacer, and the dielectric liner are each made of SiO ₂ , SiN,
SiON, Al ₂ O ₃ or the method of manufacturing a semiconductor device according to claim 1 consisting of SiC,. 4. A CM for removing an upper portion of the insulating layer.
2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of exposing said sacrificial filling stud by polishing in a P step. 5. The method of manufacturing a semiconductor device according to claim 1, wherein said sacrificial filling stud is removed by etching back said sacrificial filling stud by isotropic dry etching or wet etching. 6. The method according to claim 1, wherein the portion of the dielectric liner located on the substrate and between the spacers is removed by an anisotropic RIE process. 7. A CM for removing an upper portion of the conductive layer.
2. The method of manufacturing a semiconductor device according to claim 1, wherein the insulating layer is exposed by polishing in a P step so that an insulating plug is formed. 8. Providing a semiconductor substrate having a conductive line, forming an induction cap on the conductive line, forming a dielectric liner on the conductive line, forming a spacer on a side wall of the dielectric liner. Forming a sacrificial layer so as to form a sacrificial filling stud that forms an opening therebetween; and forming an insulating layer having a material different from that of the induction liner in the sacrificial layer. Filling the opening; removing the filling stud to form a contact hole; removing a portion of the dielectric liner between the spacer and the substrate through the contact hole; Forming a conductive layer on the insulating layer and filling the contact holes to electronically connect to the substrate;
A method for manufacturing a semiconductor device, comprising: 9. The method according to claim 8, wherein the conductor comprises a silicon oxide liner, a polysilicon layer, and a tungsten silicide layer. 10. The dielectric cap, the spacer,
And the dielectric liners are SiO ₂ , Si
N, SiON, Al ₂ O ₃ or method according to claim 8, wherein comprising a SiC,. 11. A method for removing an upper portion of the insulating layer by using C
9. The method of manufacturing a semiconductor device according to claim 8, further comprising a step of exposing said sacrificial filling stud by polishing by an MP step. 12. The method according to claim 8, wherein the sacrificial filling stud is removed by etching back the sacrificial filling stud using isotropic dry etching or wet etching. 13. The method according to claim 8, wherein the removal of a part of the dielectric liner between the spacer and the substrate is performed by an anisotropic RIE process. 14. A method for removing an upper portion of the conductive layer, comprising the steps of:
9. The method of manufacturing a semiconductor device according to claim 8, wherein the insulating layer is exposed such that an insulating plug is formed by polishing in an MP process. 15. Providing a semiconductor substrate having a conductive line, forming an induction cap on the conductive line, forming a first dielectric liner on the conductive line, Forming a second dielectric liner; forming a sacrificial layer to form a sacrificial fill stud forming an opening therebetween; and wherein the sacrificial layer has a material different from that of the induction liner. Forming an insulating layer and filling the opening; removing the filling stud to form a contact hole; and the first dielectric liner between the conductor and the substrate through the contact hole. Removing a portion of the second dielectric liner and forming a conductive layer on the insulating layer to fill a contact hole. Accordingly, a step of connecting electronically to the substrate,
A method for manufacturing a semiconductor device, comprising: 16. The dielectric cap, the first dielectric liner, and the second dielectric liner are each formed of SiO.
_{2, SiN, SiON, Al 2} O 3 or the method of manufacturing of claim 15 semiconductor device, wherein the SiC,. 17. A method for removing an upper portion of the insulating layer, comprising the steps of:
16. The method of manufacturing a semiconductor device according to claim 15, further comprising a step of exposing said sacrificial filling stud by polishing by an MP step. 18. The method of manufacturing a semiconductor device according to claim 15, wherein the sacrificial filling stud is removed by etching back the sacrificial filling stud by isotropic dry etching or wet etching. 19. The semiconductor device according to claim 15, wherein a portion of the first dielectric liner and a portion of the second dielectric liner located on the substrate and between the conductive lines are removed by an anisotropic RIE process. Manufacturing method. 20. A method for removing an upper portion of the insulating layer, comprising the steps of:
The method according to claim 15, wherein the insulating layer is exposed by polishing by an MP process so that an insulating plug is formed.