TW510017B - Method for producing self-aligned contact having sacrificial filling pillar - Google Patents

Abstract

The present invention provides a method for producing a self-aligned contact having a sacrificial filling pillar. The method will not damage other isolation layer when performing a self-aligned contact process, thus preventing the occurrence of a current leakage from impaired isolation effectiveness. The method does not need to use an etching agent having a high selectivity of silicon oxide to silicon nitride in the reactive ion etching process to achieve the self aligned contact production process. Furthermore, the thickness of the insulative Method for producing self-aligned contact having sacrificial filling pillar cap layer covering the conductive lines formed by the invented method can be reduced, thereby reducing the aspect ratio and obtaining a better insulative layer gap filling. The insulative material used by the method can greatly reduce the parasitic capacitance between layers of conductive wire.

Description

510017

See Figure 1A for the bottom layer 4 and the two diagrams of the wire junction structure. For the dielectrics to be implemented, see Figure 1C for the semiconductor to expose the plug. m ψ 、: It is formed by silicon oxide-lined wire structure, and the cap layer and wire on stone f. One person's please refer to the 1B electric layer (oxidation; ε layer) to form as shown in Figure 16. Next, please fill the contact window 16 with the conductive layer 18, and isolate the contact with the edge. Do not form silicon nitride on the base's polycrystalline layer 6 and the stone structure. The lithography of the wire structure and the post-etching process layer 14 and the intermediary pattern form a comprehensive formation of the substrate 20 electrically connected to the dielectric layer 14 so that the upper cover composed of the tungsten layer 8 is formed on the surface of the bottom 2 Layer 10 and the silicon nitride spacer layer 12. A dielectric is formed thereon to define the contact window between the dielectric layers and the electrical layers. A conductive layer 18 is filled, and then the conductive layer 18 is chemically and mechanically researched to form a quasi-contact process. The contact window 16 is then formed. When the step is separated from the ^ t _ f layer, if the non-isotropic anti-f ion is used. When chf3 is used as an etchant: the second reaction layer is 反, the oxidation layer and the nitrogen layer are The ratio of the breaking rate is more than 20 to 1, in order to prepare the top cover of silicon wafer 10 and silicon nitride to achieve this project. 2A „Sun Er'er's process technology has not implemented a non-isotropic self-aligning contact process I. The loss is caused by the contact window engraving actually formed by the middle and later stages, and if the layer 1G and nitrogen The cutting of the spacer layer 12 has been affected and the second conductor is too serious, which will affect the insulation and isolation of the wind and the short circuit between the green structure and the contact plug. It is the disadvantage that it makes it difficult to reduce the size of the component, especially ... Micron generations only allow smaller line widths

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It is difficult to significantly improve the reaction ion, so if there is no new process technology: "It is still very difficult to see that the amount of economic scale cannot be reached = breaking will make it difficult to increase the μ rate. The purpose of this specification is to provide a In the quasi-contact process, the self-filling column will damage other barriers .: Method = self-aligning contact process steps. Another purpose is to provide a kind of sacrificial filling. Nitrogen cutting with high oxygen needs to be touched in the reactive ion engraving process. There is another choice of tincture to achieve self-alignment and contact with Baiming. The purpose is to provide a quasi-contact process with sacrificial packed columns. This method uses: Parasitic capacitance between the layers of the wire. "Badong He" "Small field to reduce the connection of fir" This invention discloses-a kind of self-pairing with sacrificial packing columns provided by oxygen it, 'f first'-semiconductor The substrate is formed on the wire structure in order on the substrate to form an insulating cap layer, which is defined as: m ξ ·. Then, a wire insulating spacer layer is formed on both sides of the insulating cap layer and the wire structure. Second, the compliance is formed -insulation The liner layer covers the wire insulation spacer layer and the surface of the wire structure. Secondly, a sacrifice layer is comprehensively formed, and then lithography and money engraving procedures are performed, and the sacrifice layer is defined to form a sacrificial filled column and interpose the sacrificial filled column. Then, an insulating layer different from the material of the insulating cushion layer is formed comprehensively to fill the opening between the animal-type filled columns. Then, the insulating layer is ground to expose the sacrificial layer 510017. 5. Description of the invention (4) The upper surface of the animal-type filling column. Furthermore, the sacrificial type filling column is removed to form a contact window opening. Secondly, the contact window opening is engraved using an anisotropic reactive ion name to remove the overlying semiconductor substrate. An insulating liner layer is formed between the conductive insulating spacers. Finally, a conductive layer is completely formed to fill the opening of the contact window to be electrically connected to the semiconductor substrate, and then the electrical layer is ground to expose the insulating layer and make conductive. The layer forms a contact plug that is isolated by insulation. In summary, it will not be damaged when self-aligning, and for nitriding, this side is reduced, so this method is adopted for obvious and easy to understand. As stated clearly, the method of contact suppression is such that the silicon selection method can reduce the size of the device. The following is as follows: This method separates the layer without the need for an etchant to cover the conductivity ratio. The material can be obtained from the above, and one of the preferred sources is implemented and the ionizer is used to achieve a better online reduction. Other embodiments have a self-response isolation process and a gap on the insulation. The special contact registration effect of the wire layer makes it possible to use the parasitic characteristics of the thick insulation layer filling in the Micro Motion contact capping layer, and the leakage current in the attached figure, the oxide scale, and the J degree can be charged. fl Capacitance (point energy j, t [Schematic description] Figures 1 A to 1 C are cross-sectional views according to the conventional manufacturing process. Figure 2A shows the cross-section of the contact window of Li Da ~. ^ Formed by alignment contact process

Fig. 2B is a cross-sectional view of a contact window actually formed after performing anisotropic reactive ion etching. v Figures 3A to 3F are cross-sectional views of a manufacturing process of a self-aligned contact process with a sacrificial fill post according to Embodiment 1 of the present invention. 4A to 4F are cross-sectional views of a manufacturing process of a self-aligned contact process with a sacrificial post according to Embodiment 2 of the present invention. 5A to 5F are cross-sectional views of a manufacturing process of a self-aligned contact process with a sacrificial post according to Embodiment 3 of the present invention. [Character description] 20, 40, 60 ~ semiconductor substrate; 22, 42, 62 ~ oxidized substrate layer; 2 4, 4 4, 6 4 ~ polycrystalline stone layer; 2 6, 4 6, 6 6 ~ Tungsten silicide layer; 2 8, 4, 8 and 6 8 insulating cover layer; 30, 5 2 to insulating spacer layer; 3 2, 50 to insulating pad layer; i 7 0 to first insulating pad layer; 7 2 ~ Second insulation pad layer; 34, 54, 74 ~ sacrificial filling posts; 36, 56, 76 ~ openings; 37, 57, 77 ~ contact window openings; 38, 58, 78 ~ insulation layers; 39, 59, 79 ~ conductive layer. 510017, description of the invention (6) Embodiment 1 Now, referring to FIGS. 3A to 3F, a preferred embodiment according to the present invention will be described. First, as shown in FIG. 3A, the substrate 20 is, for example, a silicon wafer, on which a conductor element, such as a transistor element, can be used. Here, the semiconducting yarn required for Av is to be interspersed. For the sake of simplicity, it is represented by a base 20 of one ::. On the surface of the substrate 20: ^ dagger base layer 22, a polyspar base layer 24, and a petrified base layer; formed into a structure, for example, first formed by a thermal oxidation process-a thin oxide base = 22, and then a plasma-enhanced chemical vapor deposition (pEcvD) is formed into a silicon layer 24 and a tungsten silicide layer 26 ′, and then a insulation layer is formed on the wire structure: a marginal cap layer 28, for example, promoted by electrical destruction Chemical Vapor Deposition (pEcvD) or Low Pressure Chemical Vapor Deposition (LPCVD) forming a two-layer emulsified stone layer, nitrogen-cut layer, nitrogen-oxygen-cut layer, oxide layer, or carbonized carbide with a thickness of 2000 to 2500 A Evening floor. Next, a lithography and etching process is performed to define the pattern of the wire structure composed of the silicon oxide substrate layer 22, the polycrystalline silicon layer 24, the tungsten silicide layer 26, and the insulating cap layer as shown in the figure. Next, the insulating cap Layer and the side wall of the wire structure, a wire insulation spacer layer 30 is formed, and a plasma is used to promote PECVD or low pressure chemical vapor deposition (LpcVD) to form a thickness of 100 to 600 A Silicon layer, silicon nitride layer, silicon oxynitride layer, & aluminum carbide layer or silicon carbide layer. This thin film layer is then etched back (etching-back) to form an insulating spacer layer 30. Second, the compliance forms an insulating liner The cushion layer 3 2 covers the insulation layer of the wire and the surface of the wire structure, and a plasma-assisted chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LpcvD) is used to form a thick 510017. 5. The description of the invention (7) is 100 to — one of a siliconized silicon layer, a silicon nitride layer, a silicon oxynitride layer, a siliconized aluminum layer, or a carbonized carbide layer. 32 == Refer to Figure 3B for a comprehensive formation of a sacrificial layer before micro / Define the sacrificial layer to form a sacrificial fill The pillar 34 and the intervening, the opening between the scholar-type filling posts 3 6. This sacrificial layer can be a polycrystalline stone ^ Yu Zhi has already formed an insulating spacer layer 30 and an insulating pad layer 32, so you can: 'At this moment, the polycrystalline stone layer produces residues and causes electrical shorts. The layer material is shown in Figure 3C, and the planarity forms a layer different from the insulating liner. The opening 36 between the filled columns is, for example, 80 (PECVD) to form an oxide layer with a thickness of 5000 to MOO A. The edge reed U㊉2 is polished by a planarization process such as chemical mechanical polishing, and the exposed surface is polished. The sacrificial packing column is formed on the table ® to form a force margin diagram as shown in the figure, such as adjusting the turntable speed in the process parameters, pressing down the sentence type, the type of abrasive, and the type of abrasive to control the removal rate in the process, evenly And selectivity, remove the upper part of this insulating layer. Please refer to the wide picture of the two systems of sex, county, and county. Use the isotropic dry etching process or the isotropic process to fill the sacrificial fill column to form a contact window opening. 37. Hungry ι Η Λ times 'see Figure 3E' via the contact window opening 37 An anisotropic reactive ion etching process is used to remove the insulating gasket layer covering the semiconducting insulating layer of the wire. Soil-And 〖丨 At the end, please refer to Figure 3F. 37, and the semiconductor AV is said to be 9, fill the dry V body substrate 20 is electrically connected, and then chemically

510017 V. Description of the invention (8) Mechanically grind the conductive layer 39 to expose the insulating layer 38, so that the conductive layer 39 forms a contact plug which is insulated and isolated, wherein the conductive layer is a sputtered polycrystalline silicon layer or a crane layer . Embodiment 2 Referring now to Figs. 4A to 4F, another modified embodiment of the car according to the improved method of the present invention will be described. First, as shown in FIG. 4A, on the surface of the semiconductor substrate 40, a wire structure composed of a silicon oxide substrate layer ", a polycrystalline silicon layer 44 = a stone evening chemical crane layer 46 is sequentially formed, for example, First, a thin silicon oxide substrate layer 42 is formed by a thermal process, and then a polycrystalline silicon oxide layer 44 and one are formed by a plasma-assisted chemical vapor deposition / child deposition (PECVD) process; An insulating cap layer 48 is formed on the wire structure, for example, a silicon dioxide (PECVD) or low-pressure chemical vapor deposition (LpcvD) is formed with a plasma to form a silicon dioxide with a thickness of 200 to 2500 A. Layer, silicon nitride layer, oxynitride layer, oxide layer or carbonized carbide layer. Next, the lithography and coin engraving procedures are performed to define the silicon oxide substrate layer 42 and the polycrystalline silicon layer 44 as shown in the figure. , = Pattern of the wire structure composed of the tungsten layer 46 and the insulating cap layer 48. Next, an compliant insulation layer 5G is formed to cover the surface of the wire structure. fΛν / degrees of 100 to 400, two layers of oxides and nitrides: oxide-oxide layer Or a layer of carbide fossil. Secondly, a wire insulation spacer layer 52 is formed on the side wall of the cover, which is also a chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (_forming-thickness 1). . To _ into the dioxide

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Silicon, silicon oxynitride, aluminum oxide, or silicon carbide. The thin film layer is etched-backed to form an insulating spacer layer 52. For a long time, referring to FIG. 4B, a sacrificial layer is comprehensively formed, and then micro, shadow, and etching processes are performed, and the sacrificial layer is defined to form a sacrificial filled column 54 and an opening 56 between the sacrificial type and filled columns. The sacrificial layer may be a polycrystalline silicon layer. Since the insulating spacer layer 50 and the insulating liner layer 52 have been previously formed, it is possible to prevent electrical shorts caused by residues generated when the polycrystalline silicon layer is etched. Next, referring to FIG. 4C, an insulating layer different from the insulating liner layer material is formed to fill the openings 56 between the sacrificial filled columns. For example, a plasma-assisted chemical vapor deposition (PECVD) molding process is used to form an insulating layer. An oxide layer having a thickness of 5000 to 8000 A. Then, using a planarization process, such as chemical mechanical polishing, to grind this layer, the layer is routed out of the upper surface of the sacrificial filled column to form a pattern of the edge layer 58 as shown in the figure, such as adjusting the turntable in the process parameters Speed, down pressure, type of polishing pad and type of abrasive to control the removal rate, uniformity and selectivity in the process, and remove the upper part of the insulating layer. Further, referring to FIG. 4D, the sacrificial fill pillar is etched back by using an isotropic dry etching process or an isotropic ten wet etching process to remove the sacrificial fill pillar to form a contact window opening 5 7. Its person, please refer to FIG. 4E, through the contact window opening 5 7 using an anisotropic reactive ion rhyme to remove the insulating gasket layer covering the I conductor substrate and interposed between the insulation layers of the wire. . Finally, referring to FIG. 4F, a conductive layer 59 is comprehensively formed, which passes through the insulating layer 58 and is electrically connected to the semiconductor substrate 40. Then, a chemical mechanical research 510017 is used. , So that the insulating layer 58 is exposed, and the conductive layer 59 forms a contact plug which is isolated by insulation, wherein the conductive layer is a sputtered polycrystalline silicon layer or a tungsten layer. Embodiment 3 Referring now to Figs. 5A to 5F, another preferred embodiment of the improved method according to the present invention will be described. First, as shown in FIG. 5A, on the surface of the semiconductor substrate 60, a wire structure composed of a silicon oxide substrate layer β2, a polycrystalline silicon layer 64, and a tungsten silicide layer 66 is sequentially formed. For example, first A thermal oxidation process is used to form a thin oxide stone substrate layer 62, and then a plasma-assisted chemical vapor deposition (PECVD) is used to form a polycrystalline silicon layer 64 and a tungsten silicide layer 66, and then on the wire structure An insulating cap layer 68 is formed, for example, a plasma-assisted chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LpCVD) is used to form a SiO 2 layer, a SiO 2 layer, and a silicon oxynitride layer having a thickness of 200 to 2500 A. Layer, alumina layer, or silicon carbide layer. Next, a lithography and etching process is performed to define a pattern of a wire structure composed of a silicon oxide substrate layer 62, a polycrystalline silicon layer 64, a silicon = crane layer 66, and an insulating cap layer 68 as shown in the figure. Then, a first insulating pad layer 70 and a second insulating pad layer 72 are conformably formed to cover the surface of the wire structure, and a plasma-assisted chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition is also used. (LPCVD) forming a nitride with a thickness of 100 to 600 Λ; a layer of 70 g and an oxide layer with a thickness of iq0 to goo a 7 2 ° ^ Secondly, please refer to FIG. 5B, a comprehensive formation of a sacrificial The layer then performs the micro- and post-etching procedures to define the sacrificial layer to form a sacrificial filled column 74 and a dielectric layer.

510017 V. Description of the invention (11) The opening 76 between the sacrificial packing columns. This sacrificial layer can be a polycrystalline silicon layer. Since the insulating spacer layer 70 and the insulating liner layer 72 have been formed before, the residue can be prevented from being etched when the polycrystalline silicon layer is etched. Then, see FIG. 5C. Forming an insulating layer of „not ==“ layer material to fill the opening M ′ between the sacrificial filling columns, such as two-electrode promoted chemical vapor deposition (PECVD) forming an oxide layer of 5000 to 8000A . After d, a planarization process, such as chemical mechanical polishing, is used to grind the upper surface of the sacrifice Γ-type filled column to form the pattern of the edge layer 78 as shown in the figure, such as the turntable in adjusting the process parameters. Force the type of abrasive pad and the type of abrasive to control: remove the second sentence and selectivity, and remove the upper part of the insulating layer. ^ Remove the sheep, all the more, please refer to FIG. 5D, and use the isotropic wet etching process to fill the sacrificial pattern with the sacrifice pattern to form a column; == enter ... cut to remove this sacrificial pattern For example, referring to FIG. M, the non-fluorinated reactive ion etching process is used to remove the insulating liner layer covering the semiconductor substrate 2 and the insulating spacer layer through the contact window opening 77 using a non-reactive reactive ion etching process.土-) 丨 于 最 # See Figure 5F, comprehensive character—through the insulating layer 78 and the semiconducting jealous 79, it wears the conductive layer 79 to expose: 缘}, connect, and then: Contact plugs isolated by CMP, agricultural ,, and [Ray: make the conductive layer 79 form an insulated layer. " This conductive layer is a coin-plated polycrystalline silicon layer or tungsten. Although the present invention has been disclosed above as a preferred example, it is not intended to limit page 14 510017 5. Description of the invention (12) The invention, Anyone skilled in this art can make changes and retouching without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application.

Claims (1)

510017 6. Scope of patent application 1. A self-aligned contact process with sacrificial filled pillars is applicable to a semiconductor substrate. The method includes the following steps: (a) forming a wire structure on the semiconductor substrate; (b) in An insulation cover layer is formed on the wire structure; (c) a first-level insulation spacer layer is formed on the insulation cover layer and the side walls on both sides of the wire structure; & (d) an insulation pad layer is formed to cover the insulation space of the wire and Wire structure surface (e) forming a sacrificial layer, and defining the sacrificial layer to form a sacrificial filling pillar and an opening between the sacrificial filling pillar; (f) forming an insulating 忒 sacrificial filling different from the material of the insulating liner layer (G) removing the sacrificial filling post to form a contact window opening; (h) removing the insulating liner covering the semiconductor substrate 1 between the wire insulation spacer layer through the contact window opening A plutonium layer; and (1) forming a conductive layer to fill the contact window opening and be electrically connected to the semiconductor substrate. ("The method as described in item 1 of the scope of the patent application, wherein the wire structure in this step is composed of a silicon oxide substrate layer, a polycrystalline silicon layer, and a tungsten silicide layer. —3 • As described in the patent application The method according to item 1, wherein the insulating cover, the wire insulating spacer layer and the insulating pad layer are made of silicon dioxide, gasified stone layer, silicon oxynitride layer, aluminum oxide layer, or silicon carbide 4. The method as described in item 1 of the scope of patent application, wherein this step Page 16 510017 Patent Application Range_ (〇 More includes grinding the upper surface of the insulating packing column by chemical mechanical. Make the way out of the sacrificial type 5. The method described in item 丨 of the scope of patent application, 苴 (S) To remove the sacrificial packing column, the benefit = this step or wait 6 directions: engraving, and the sacrificial packing column is etched back. Engraving. Process r * The method described in item 1 of the patent scope is printed, where: The removal in step (h) covers the semiconductor substrate and is between the two and two steps. The item, and the edge pad layer are made by using anisotropic reactive ion etching. The method described in item 1, wherein the conductive layer in Xi Niu (0) is a polycrystalline silicon layer or a tungsten layer, and the conductive layer is polished so that the exposed layer is isolated by mechanical chemical research and mechanical research. The contact inserts a thin edge layer, so that the conductive layer is formed by a self-aligned contact process which is insulated at -8 ϊ = ΐ sacrificial filled column, which is suitable for a rich conductor substrate. The method includes the following steps: (a) Forming a wire structure on the semiconductor substrate; (b) forming a wire structure on the wire structure; Insulating cap layer; (c) Forming: an insulating gasket layer to cover the surface of the wire structure; (j) a wire insulation spacer layer on the side walls of the insulating gasket layer covering the wire structure; Forming a sacrificial layer, and defining the sacrificial layer to form a sacrificial filling pillar; and 丨 an opening between the sacrificial filling pillar;-, shape / an insulating layer different from the material of the insulating liner layer to fill the sacrificial The opening between the two types of filled pillars; ,,,,,,,,,,,,,,,,,,,,,,,,,,,, ---- ~ --------— __ (运) Remove # (h) Form a contact window opening through the Γ sacrificial filled pillar; and Removing the insulating pad layer covering the semiconductor substrate between the conductive window opening (i) ^ and the spring insulating spacer layer; and the bottom electrically connected to form a conductive layer to fill the contact window opening And the method described in the semiconductor substrate (a) according to item No. 8 of the patent scope, wherein the line structure composed of the step layer is a silicon oxide substrate layer, a polycrystalline silicon layer, and a tungsten silicide. 1 ^ The method described in item 8 of the patent application, wherein the insulating k-layer: The spacer layer and the insulating layer are made of a dioxide dioxide layer, an oxynitride layer, an oxide layer, or a carbonized layer, and an ε layer. (F) The contention is as described in item 8 of the patentable scope A method, wherein the step includes grinding the insulating layer to expose the upper surface of the sacrificial filled column by chemical mechanical polishing. 1 2 · The method according to item 8 of the scope of patent application, wherein the step ^ # The removal of the sacrificial filling column is to etch back the sacrificial plastic filling column using an isotropic dry etching process 3 ^ isotropic wet etching process. 1 3. The method as described in item 8 of the scope of patent application, wherein, In this step), the insulating liner layer removed on the semiconductor substrate and interposed between the insulation layers of the conductor is removed by using an anisotropic reactive ion etching process. 0 ^ • 14 · The method according to item 8, wherein the conductive layer in step (1) is a polycrystalline silicon layer or a tungsten layer, and the conductive layer is chemically and mechanically polished to expose the insulating layer, thereby forming the conductive layer. Insulated Page 18 Contact plug 15 · —A sacrificial type is used for a semiconductor wafer, and the alignment contact process is suitable to dry the isotropic substrate. The method includes the following steps: forming a guide on the semiconductor substrate; (c) ^ Forming an insulating capping layer; ⑷ formation-the second insulating pad layer with an id line junction; the surface; the layer; the M complex layer of this brother an insulating pad. Y into a sacrificial layer 'and define the sacrifice reed with hard work The filling column and the opening layer between the sacrificial filling column ^ form the sacrificial filling (f) to form an insulating layer different from the first filling the sacrificial filling branch n & The opening in Tottenham; (g) removing the sacrificial 埴 also knows (h) through the contact window door 一, a contact window opening; and the "n" opening between the wires covers the semiconductor substrate An overlying underlayer; and ^, ° between the structures-an insulating liner layer, the second insulating substrate is electrically connected to form a conductive layer to fill the opening of the contact window and the semiconductor substrate 16 · if applying for a patent Fan Yuan cap layer, the method described in the guide t5, wherein the silicon insulating layer, the silicon nitride layer, Said oxygen: the insulating spacer layer and is designed for the application as floor i7 dioxide, Ming oxide layer or layers hinder fossil evening. The step IK !: The method described in item 15, wherein the step type fills the S surface above the column. Pre-mechanically grind the insulating layer to expose the sacrifice Page 19, 510017, 6. Patent application scope 1 8 · The method described in item 15 of the patent application scope, wherein the removal of the sacrificial packing column in step (g) is performed using an isotropic dry etching process or An isotropic wet etching process is performed to etch back the sacrificial filled column. 19. The method according to item 15 of the scope of patent application, wherein in step (h), the removal of the insulating pad layer covering the semiconductor substrate and interposed between the wire insulating spacer layers is performed by using Isotropic reactive ion etching process. 2 0. The method according to item 15 of the scope of patent application, wherein the conductive layer in step (i) is a polycrystalline silicon layer or a tungsten layer, and the conductive layer is chemically and mechanically polished to expose the conductive layer. An insulating layer, so that the conductive layer forms a contact plug which is isolated by insulation. Page 20