JP2001196476A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the reliability of a semiconductor device by designing a fine device element. SOLUTION: A sidewall spacer 18a made of a second polycrystalline silicon film is formed on the side surface of a first polycrystalline silicon film 13. In this case, when the thickness of the sidewall spacer is set to x, the distance from the surface of a buried insulation film 17 to that of the first polycrystalline silicon film is set to a, film thickness when the second polycrystalline silicon film is formed is set to b, and the distance between the first polycrystalline silicon films 13 is set to c, b <=a=x<c/2 is satisfied.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a nonvolatile semiconductor memory, and more particularly to a semiconductor device having a memory cell array structure and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, a nonvolatile semiconductor memory having a miniaturized two-layer stack structure gate electrode and a memory transistor has been known. Hereinafter, a method of manufacturing a nonvolatile semiconductor memory having a memory cell array structure according to the related art will be described.

First, as shown in FIG. 23, a gate oxide film 12 having a thickness of, for example, 80 ° is formed on a silicon substrate 11, and a film thickness of, for example, 1000
The first polycrystalline silicon film 13 of Å is formed. On the first polycrystalline silicon film 13, a film thickness of, for example, 1500
A silicon nitride film 14 serving as an etching mask material of Å is formed.

[0006] Next, as shown in FIG. 24, a resist 14 a is formed on the silicon nitride film 14.
4a is patterned by photolithography. Using the patterned resist 14a as a mask, the silicon nitride film 14 is removed by anisotropic dry etching. Then, the resist 14a is wet-etched.
Is removed.

Next, as shown in FIG. 25, using the patterned silicon nitride film 14 as a mask, a first polycrystalline silicon film 13, a gate oxide film 12, and a silicon substrate 11 are formed by anisotropic dry etching. The groove 15 is formed by etching to the depth.

Next, as shown in FIG. 26, in order to recover the damage of the etched surface of the silicon substrate 11, a film thickness is formed on the exposed surfaces of the silicon substrate 11 and the first polycrystalline silicon film 13, for example. An oxide film 16 of 100 ° is formed.

Next, as shown in FIG. 27, a buried insulating film 17 having a thickness of, for example, 6000 ° is formed on the entire surface, and the recess 15 is buried. Next, CMP (Chemical Mecha)
The buried insulating film 17 is flattened to a desired height by the nical polishing method, and the surface of the silicon nitride film 14 is exposed. Thereafter, as shown in FIG. 28, the silicon nitride film 14 is removed by wet etching, and the element region 1 is removed.
1a and an element isolation region 11b are formed.

Next, as shown in FIG. 29, a second polycrystalline silicon film 18 having a thickness of, for example, 1000 ° is formed on the entire surface. Next, as shown in FIG. 30, a resist 14b is formed on second polycrystalline silicon film 18 and patterned. Using the patterned resist 14b as a mask, as shown in FIG. 31, the second polycrystalline silicon film 18 is removed by anisotropic etching to form a slit portion 18b. After that, the resist 14b is removed.

Next, as shown in FIG. 32, an ONO film (laminated film of silicon oxide film / silicon nitride film / silicon oxide film) 19 having a thickness of, for example, 120 ° is formed on the entire surface. Next, as shown in FIG. 33, a third polycrystalline silicon film 22 having a thickness of, for example, 1000 ° is formed on the ONO film 19, and a third polycrystalline silicon film 22 having a thickness of, for example, 500 A high melting point silicide film 21 is formed.

Thereafter, in order to form word lines, a high melting point silicide film 21 is formed by anisotropic dry etching.
Third polycrystalline silicon film 20, ONO film 19, second polycrystalline silicon film 18, and first polycrystalline silicon film 13
Are sequentially processed. Thus, a memory cell (not shown) is formed.

[0011]

In the above-mentioned conventional nonvolatile memory, a voltage of about 20 V is applied to the high melting point silicide film 21 and FN (Fowler-Nordher) is applied to the gate oxide film 12.
m) Generate current. Thereby, electrons are injected into first polycrystalline silicon film 13. On the other hand, silicon substrate 1
1 is applied to the gate oxide film 12 with a voltage of about 20 V.
An N current is generated. Thereby, electrons are extracted from first polycrystalline silicon film 13.

As described above, electrons are injected and extracted by the FN current generated in the gate oxide film 12. The magnitude of this FN current depends on the first and second polycrystalline silicon films 1.
It is determined by the potential of the floating gate electrode composed of 3 and 18. The potential of this floating gate electrode is
And the coupling capacity ratio of the ONO film 19. In other words, the gate oxide film 12 and O
The coupling capacity ratio of the NO film 19 is important.

Here, the capacitance of the gate oxide film 12 is C1,
When the capacitance of the ONO film 19 is C2, the coupling capacitance ratio C satisfies the relationship of Expression (1). When the surface area of the ONO film 19 is S, the film thickness of the ONO film 19 is d, and the relative dielectric constant is ε, the capacitance C2 of the ONO film 19 satisfies the relationship of the expression (2).

C = C2 / (C1 + C2) (1) C2 = ε × S / d (2) To increase the potential of the floating gate electrode, the equation (1)
Must be increased. In order to increase the coupling capacitance ratio C, a method of reducing the thickness of the ONO film 19 or increasing the surface area of the ONO film 19 can be mentioned from the equation (2).

However, when the ONO film 19 becomes thin, a leak current is generated. As a result, the reliability of the ONO film 19 cannot be ensured. The surface area of the ONO film 19 depends on the size of the opening of the slit 18b. However, FIG.
In the step of forming the slit portion 18b shown in FIG. 1, the accuracy required for the slit portion 18b is stricter than the accuracy that can be adjusted by the current lithography technology. Therefore, it is difficult to meet the demand for strict dimensional accuracy of the slit portion 18b under the current design rules.
It is difficult to increase the surface area of the film 19.

As described above, when the conventional manufacturing method is used, there is a problem that a highly reliable semiconductor device cannot be obtained because it is difficult to design a fine device element.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor device capable of designing a fine device element and improving reliability, and a method of manufacturing the same. To provide.

[0018]

The present invention uses the following means to achieve the above object.

According to the semiconductor device of the present invention, a trench for isolating an element region in a semiconductor substrate, a gate oxide film formed on the element region, and a first multi-layer formed on the gate oxide film are provided. A crystalline silicon film, a first insulating film exposing an upper portion of the first polycrystalline silicon film and filling the trench, and a second insulating film formed on a side surface of an upper portion of the exposed first polycrystalline silicon film. 2 and a sidewall spacer made of a polycrystalline silicon film, and an ONO film formed on the entire surface.

The thickness of the side wall spacer is x, the distance from the surface of the first insulating film to the surface of the first polycrystalline silicon film is a, and the film at the time of forming the second polycrystalline silicon film is When the thickness is b and the distance between the first polycrystalline silicon films is c, the relationship of b ≦ a = x <c / 2 is satisfied.

According to another aspect of the present invention, there is provided a semiconductor device comprising: a second insulating film formed between the first polycrystalline silicon film and the side wall spacer;
And a recess formed at the upper end of the polycrystalline silicon film.

The thickness of the sidewall spacer is x, the distance from the surface of the first insulating film to the surface of the first polycrystalline silicon film is a, and the film thickness at the time of forming the second polycrystalline silicon film is When the thickness is b and the distance between the first polycrystalline silicon films is c, the relationship of b ≦ a = x <c / 2 is satisfied.

The thickness of the second insulating film is from 20 to 40.
Å. Further, the first polycrystalline silicon film and the second polycrystalline silicon film are doped with the same kind of impurities.

In the method of manufacturing a semiconductor device according to the present invention, a step of forming a gate oxide film on a semiconductor substrate; a step of forming a first polycrystalline silicon film on the gate oxide film; Forming a first insulating film on the polycrystalline silicon film and patterning the same; and removing the first polycrystalline silicon film and the gate oxide film using the patterned first insulating film as a mask. Exposing the surface of the semiconductor substrate, removing the semiconductor substrate in the exposed region to a desired depth, and forming a groove in the semiconductor substrate; Forming an oxide film on the exposed surface of the polycrystalline silicon film, forming a second insulating film over the entire surface and filling the trench, and planarizing the second insulating film. , The first A step of surface Enmaku is exposed,
A step of removing the first insulating film; a step of removing the second insulating film and the oxide film to expose an upper portion of the first polycrystalline silicon film; A step of forming a crystalline silicon film; a step of removing the second polycrystalline silicon film; forming a side wall spacer on a side surface of the first polycrystalline silicon film; and forming an ONO film on the entire surface And a step.

The thickness of the sidewall spacer is x, the distance from the surface of the first insulating film to the surface of the first polycrystalline silicon film is a, and the film thickness at the time of forming the second polycrystalline silicon film is When the thickness is b and the distance between the first polycrystalline silicon films is c, the relationship of b ≦ a = x <c / 2 is satisfied.

The first polycrystalline silicon film and the second polycrystalline silicon film are doped with the same kind of impurities. The sidewall spacer is formed by anisotropic dry etching.

According to another method of manufacturing a semiconductor device of the present invention, a step of forming a gate oxide film on a semiconductor substrate, a step of forming a first polycrystalline silicon film on the gate oxide film, Forming a first insulating film on the first polycrystalline silicon film and patterning the first polycrystalline silicon film, and using the patterned first insulating film as a mask, the first polycrystalline silicon film and the gate oxide film Is removed, the surface of the semiconductor substrate is exposed, and the semiconductor substrate in the exposed region is removed to a desired depth to form a groove in the semiconductor substrate; and Forming an oxide film on the exposed surface of the first polycrystalline silicon film, forming a second insulating film on the entire surface,
A step of filling the groove, a step of planarizing the second insulating film to expose a surface of the first insulating film, a step of removing the first insulating film, and a step of removing the second insulating film. Removing the insulating film and the oxide film, and exposing an upper portion of the first polycrystalline silicon film; and forming a third insulating film so as to cover the exposed upper portion of the first polycrystalline silicon film. Forming a film, forming a second polysilicon film over the entire surface, removing the second polysilicon film and the third insulating film, and removing the first polysilicon film. Forming a sidewall spacer on the side surface of the film with the third insulating film interposed therebetween, and etching back the sidewall spacer and a part of the first polysilicon film to form an upper portion of the sidewall spacer and the first polycrystalline silicon film; Forming a recess at the upper end of the polycrystalline silicon film; And a step of ONO film is formed on the surface.

The thickness of the side wall spacer is x, the distance from the surface of the first insulating film to the surface of the first polycrystalline silicon film is a, and the film at the time of forming the second polycrystalline silicon film is When the thickness is b and the distance between the first polycrystalline silicon films is c, the relationship of b ≦ a = x <c / 2 is satisfied.

The first polycrystalline silicon film and the second polycrystalline silicon film are doped with the same kind of impurities. The sidewall spacer is formed by anisotropic dry etching. The thickness of the second insulating film is 2
0 ° to 40 °.

[0030]

Embodiments of the present invention will be described below with reference to the drawings.

First Embodiment First, as shown in FIG. 1, a film having a thickness of, for example, 8
A 0 ° gate oxide film 12 is formed, and a first polycrystalline silicon film 13 having a thickness of, for example, 1500 ° is formed on gate oxide film 12. This first polycrystalline silicon film 1
3, a silicon nitride film 14 serving as an etching mask material having a thickness of, for example, 1500 ° is formed.

Next, as shown in FIG. 2, a resist 14a is formed on the silicon nitride film 14, and the resist 14a
a is patterned by photolithography. Using the patterned resist 14a as a mask, the silicon nitride film 14 is removed by anisotropic dry etching. Then, the resist 14a is wet-etched.
Is removed.

Next, as shown in FIG. 3, the first polycrystalline silicon film 13 and the gate oxide film 12 are etched by anisotropic dry etching using the patterned silicon nitride film 14 as a mask.

Next, as shown in FIG. 4, the silicon substrate 11 is removed to a desired depth by anisotropic dry etching, and a groove 15 is formed in the silicon substrate 11.
Thereafter, as shown in FIG. 5, in order to recover the damage of the etched surface of the silicon substrate 11,
Then, oxide film 16 having a thickness of, for example, 100 ° is formed on the exposed surface of first polycrystalline silicon film 13.

Next, as shown in FIG. 6, a buried insulating film 17 having a thickness of, for example, 6000.degree. Is formed on the entire surface, and the groove 15 is buried. Next, the buried insulating film 17 is flattened to a desired height by the CMP method, and the surface of the silicon nitride film 14 is exposed. Thereafter, as shown in FIG. 7, the silicon nitride film 14 is removed by wet etching, and an element region 11a and an element isolation region 11b are formed.

Next, as shown in FIG. 8, the buried insulating film 17 and the oxide film 16 are removed, and the upper portion of the first polycrystalline silicon film 13 is exposed. Next, as shown in FIG.
A second polycrystalline silicon film 18 having a thickness of, for example, 600 ° is formed on the entire surface. Here, the second polycrystalline silicon film 1
8 is doped with the same kind of impurities as the first polycrystalline silicon film 13. Next, as shown in FIG. 10, second polycrystalline silicon film 18 is removed by anisotropic dry etching, and side wall spacers 18 a are formed on the side surfaces of first polycrystalline silicon film 13.

Next, as shown in FIG. 11, an ONO film 19 having a thickness of, for example, 120 ° is formed on the entire surface. Next, as shown in FIG.
A third polysilicon film 20 having a thickness of, for example, 500 .ANG. Is formed thereon.
Is formed.

Thereafter, in order to form word lines, the high melting point silicide film 21 is formed by anisotropic dry etching.
Third polycrystalline silicon film 20, ONO film 19, second polycrystalline silicon film 18, and first polycrystalline silicon film 13
Are sequentially processed. Thus, a memory cell (not shown) is formed.

Next, referring to FIG. 13 to FIG.
Side wall spacer 18 for securing a large surface area of the O film
The condition under which the thickness x of a becomes maximum will be described.

First, the range of the thickness b of the second polycrystalline silicon film 18 will be described as a first condition. FIG.
As shown in FIG. 5, the height a of the gate electrode 22 and the film thickness of the second polycrystalline silicon film 18 are set in order to appropriately form the side wall spacer 18a on the side surface of the gate electrode 22 composed of the first polycrystalline silicon film 13. The thickness b satisfies the relationship of Expression (3).

A ≧ b (3) Next, as a second condition, as shown in FIG. 14, the thickness b of the second polycrystalline silicon film 18 is equal to the distance c between the gate electrodes 22. If the distance is greater than / 2, the space between the gate electrodes 22 is buried with the second polycrystalline silicon film 18, and the adjacent gate electrodes 22 are in contact with each other. Therefore,
As shown in Expression (4), the thickness b of the second polycrystalline silicon film 18 is required to be smaller than a half of the distance c between the gate electrodes 22.

B <c / 2 (4) Next, as a third condition, the thickness x of the side wall spacer 18a
Will be described. The thickness x of the side wall spacer 18a is determined by the thickness b of the second polycrystalline silicon film 18. As shown in FIGS. 15A and 15B, when the height a of the gate electrode 22 is twice the height 2a, the second polycrystalline silicon film 18 can be formed with a double thickness 2b.
Therefore, in order to maximize the thickness b of the second polycrystalline silicon film 18, the thickness b of the second polycrystalline silicon film 18 and the height a of the gate electrode 22 may be made equal. That is, when the thickness x of the side wall spacer 18a is made equal to the height a of the gate electrode 22, the thickness x of the side wall spacer 18a becomes the maximum thickness.

As described above, according to the first to third conditions, when the relationship of the expression (5) is satisfied, the thickness x of the side wall spacer becomes the maximum thickness, and the surface area of the ONO film is sufficiently increased. Can be secured.

B ≦ a = x <c / 2 (5) Next, using the equation (5), the design of the height a2 of the gate electrode 22b and the thickness x of the side wall spacer 18a according to the first embodiment. Calculate the value.

As shown in FIG. 16, the height of the conventional gate electrode 22a is a1 (0.06 μm), the distance between the gate electrodes 22a is c (0.175 μm), and the wing length of the gate electrode 22a is W (0.06 μm), and the cross-sectional area of one Wing length portion is S1 (= W × a1). As shown in FIG. 17, the height of the gate electrode 22b according to the first embodiment is a2, the distance between the gate electrodes 22b is c, the thickness of the side wall spacer 18a is x, and the height of the one side wall spacer 18a is The cross-sectional area is S2 (= 2πx / 4).

Here, in order to secure a larger surface area of the ONO film (not shown), it is desired to make the surface area of the gate electrode 22b according to the first embodiment larger than that of the conventional gate electrode 22a. . Therefore, from S1 <S2, the condition of the thickness x of the side wall spacer is obtained as shown in Expression (7).

X> 4 W / π (6) x> 0.076 μm (7) As shown in the equation (5), the adjacent side wall spacers 1
The thickness x of the side wall spacer is set to be smaller than half the distance c between the gate electrodes 22b so that the gate electrodes 8a do not touch each other. Therefore, when the distance c between the gate electrodes 22b is 0.175 μm, the range of the thickness x of the side wall spacer is obtained as shown in Expression (8).

0.076 μm <x <0.0875 μm (8) From the expression (5), the height a2 of the gate electrode 22 b
Is equal to the thickness x of the side wall spacer, so that the range of the height a2 of the gate electrode 22b is determined as shown in Expression (9).

0.076 μm <a 2 <0.0875 μm (9) As described above, the distance c between the gate electrodes 22 b is set to
When the thickness is 0.175 μm, the height a of the gate electrode 22b
2 and the thickness x of the side wall spacer 18a is, for example, 0.08 μm.
m. Thereby, the cross-sectional area S according to the prior art is
1 is 0.34 μm ^TwoHowever, in the first embodiment,
The cross-sectional area S2 is 0.3512 μm^TwoBecomes Therefore,
The surface area of the ONO film can be increased compared to the prior art.
You.

According to the first embodiment, the thickness of the side wall spacer 18a is adjusted to form the side wall spacer 18a. For this reason, it is possible to separate adjacent gate electrodes without forming a slit portion in the related art, and to form an element having device characteristics equivalent to those of the related art. Therefore, since fine device element design can be performed, the reliability of the semiconductor device can be improved.

[Second Embodiment] The second embodiment is an example in which the surface area of the ONO film can be secured more than in the first embodiment.
In the second embodiment, the description of the same steps as in the first embodiment will be omitted, and only different steps will be described.

First, as shown in FIGS. 1 to 8, the buried insulating film 17 and the oxide film 16 are removed and the upper portion of the first polycrystalline silicon film 13 is exposed, as in the first embodiment. . Thereafter, as shown in FIG. 18, oxide film 23 is formed to cover exposed first polycrystalline silicon film 13. Here, the thickness of the oxide film 23 is, for example, 20 to 4
If the angle is set to 0 °, a direct current is generated, so that an electrical connection can be made with a second polycrystalline silicon film 18 described later.

Next, as shown in FIG. 19, a second polycrystalline silicon film 18 is formed on the entire surface. Next, as shown in FIG. 20, the second polycrystalline silicon film 18 is removed by anisotropic dry etching, and the first polycrystalline silicon film 1 is removed.
Sidewall spacers 18a are formed on the side surfaces of oxide film 23 via oxide film 23.

Next, as shown in FIG. 21, the side wall spacer 18a made of the second polycrystalline silicon film 18 and a part of the first polycrystalline silicon film 13 are etched back, and the upper part of the side wall spacer 18a and the second polycrystalline silicon film 13 are removed. 1 polycrystalline silicon film 13
A concave portion 24 is formed at the upper end portion of FIG. At this time, the oxide film 23 is removed at the same time. Here, the etch back is performed by lowering the selectivity (etching rate ratio) between the second polycrystalline silicon film 18 and the oxide film 23. Next, isotropic etching or wet processing such as CDE (Chemical Dry Etching) is performed.

Thereafter, as shown in FIGS.
The ONO film 19, the third polycrystalline silicon film 20, and the high melting point silicide film 21 are formed in the same manner as in the embodiment. Thus, a memory cell (not shown) is formed.

According to the second embodiment, the same effects as in the first embodiment can be obtained. Further, the side wall spacer 18a
And a concave portion 24 is formed in the upper portion of the first polycrystalline silicon film 13. Therefore, ON formed in a later process
The surface area of the O film 19 can be increased.

In addition, the present invention can be implemented with various modifications without departing from the scope of the invention.

[0058]

As described above, according to the present invention, it is possible to provide a semiconductor device capable of designing a fine device element and improving reliability, and a method of manufacturing the same.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a manufacturing process of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a manufacturing step of the semiconductor device according to the first embodiment of the present invention, following FIG. 1;

FIG. 3 is a sectional view showing a manufacturing step of the semiconductor device according to the first embodiment of the present invention, following FIG. 2;

FIG. 4 is a sectional view showing a manufacturing step of the semiconductor device according to the first embodiment of the present invention, following FIG. 3;

FIG. 5 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment of the present invention, following FIG. 4;

FIG. 6 is a sectional view showing a manufacturing step of the semiconductor device according to the first embodiment of the present invention, following FIG. 5;

FIG. 7 is a sectional view showing a manufacturing step of the semiconductor device according to the first embodiment of the present invention, following FIG. 6;

FIG. 8 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment of the present invention, following FIG. 7;

FIG. 9 is a sectional view illustrating a manufacturing step of the semiconductor device according to the first embodiment of the present invention, following FIG. 8;

FIG. 10 is a sectional view showing a manufacturing step of the semiconductor device according to the first embodiment of the present invention, following FIG. 9;

FIG. 11 is a sectional view showing a manufacturing step of the semiconductor device according to the first embodiment of the present invention, following FIG. 10;

FIG. 12 is a sectional view showing a manufacturing step of the semiconductor device according to the first embodiment of the present invention, following FIG. 11;

FIG. 13 is a diagram showing a relationship between the height a of the gate electrode and the thickness b of the second polycrystalline silicon film according to the first embodiment of the present invention.

FIG. 14 is a diagram showing a relationship between a thickness b of a second polycrystalline silicon film and a distance c between gate electrodes according to the first embodiment of the present invention.

FIGS. 15A and 15B are diagrams showing a relationship between a height a of a gate electrode and a thickness b of a second polycrystalline silicon film.

FIG. 16 is a sectional view illustrating a manufacturing step of the semiconductor device according to the first embodiment of the present invention, following FIG. 3;

FIG. 17 is a sectional view illustrating a manufacturing step of the semiconductor device according to the first embodiment of the present invention, following FIG. 4;

FIG. 18 is a sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 19 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment of the present invention, following FIG. 1;

FIG. 20 is a sectional view illustrating a manufacturing step of the semiconductor device according to the first embodiment of the present invention, following FIG. 2;

FIG. 21 is a sectional view showing a manufacturing step of the semiconductor device according to the first embodiment of the present invention, following FIG. 3;

FIG. 22 is a sectional view illustrating a manufacturing step of the semiconductor device according to the first embodiment of the present invention, following FIG. 4;

FIG. 23 is a sectional view showing a manufacturing process of a semiconductor device according to a conventional technique.

FIG. 24 is a sectional view showing a manufacturing step of the semiconductor device according to the conventional technique, following FIG. 23;

FIG. 25 is a sectional view showing a manufacturing step of the semiconductor device according to the related art, following FIG. 24;

FIG. 26 is a sectional view showing a manufacturing step of the semiconductor device according to the conventional technique, following FIG. 25;

FIG. 27 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the conventional technique, following FIG. 26;

FIG. 28 is a sectional view showing a manufacturing step of the semiconductor device according to the conventional technique, following FIG. 27;

FIG. 29 is a cross-sectional view showing a manufacturing step of the conventional semiconductor device, following FIG. 28;

FIG. 30 is a sectional view showing a manufacturing step of the semiconductor device according to the conventional technique, following FIG. 29;

FIG. 31 is a sectional view showing a manufacturing step of a conventional semiconductor device, following FIG. 30;

FIG. 32 is a sectional view showing a manufacturing step of the semiconductor device according to the related art, following FIG. 31;

FIG. 33 is a sectional view showing a manufacturing step of a conventional semiconductor device, following FIG. 32;

[Explanation of symbols]

 Reference Signs List 11: silicon substrate, 11a: element region, 11b: element isolation region, 12: gate oxide film, 13: first polycrystalline silicon film, 14: silicon nitride film, 14a, 14b: resist, 15: groove portion, 16, 23: oxide film, 17: buried insulating film, 18: second polycrystalline silicon film, 18a: side wall spacer, 18b: slit portion, 19: ONO film, 20: third polycrystalline silicon film, 21: high melting point Silicide films, 22, 22a, 22b: gate electrode, 24: recess.

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) 5F001 AA03 AA25 AA43 AA63 AB08 AB09 AC02 AD51 AD52 AD60 AG10 AG29 5F083 EP03 EP23 EP27 EP55 ER03 ER14 ER19 GA09 GA22 JA04 JA35 NA01 PR09 5F101 BA07 BA17 BA28 BA36 BB05 BD33 BH14 BH15

Claims (15)

[Claims] A trench for isolating an element region in a semiconductor substrate; a gate oxide film formed on the element region; a first polycrystalline silicon film formed on the gate oxide film; A first insulating film that exposes an upper part of the first polycrystalline silicon film and fills the trench, and a second polycrystalline silicon formed on a side surface of the upper part of the exposed first polycrystalline silicon film A semiconductor device comprising: a sidewall spacer made of a film; and an ONO film formed on the entire surface. 2. The method according to claim 1, wherein the thickness of the side wall spacer is x,
A is the distance from the surface of the insulating film to the surface of the first polycrystalline silicon film, b is the film thickness when the second polycrystalline silicon film is formed, and the distance between the first polycrystalline silicon films is 2. The semiconductor device according to claim 1, wherein when the distance is c, a relationship of b ≦ a = x <c / 2 is satisfied. 3. A second insulating film formed between the first polysilicon film and the sidewall spacer, and formed on an upper portion of the sidewall spacer and an upper end of the first polysilicon film. The semiconductor device according to claim 1, further comprising: a formed concave portion. 4. A second insulating film formed between the first polycrystalline silicon film and the side wall spacer, and formed on an upper portion of the side wall spacer and an upper end of the first polycrystalline silicon film. The thickness of the sidewall spacer is x, the distance from the surface of the first insulating film to the surface of the first polycrystalline silicon film is a, the second polycrystalline silicon is The film thickness when forming the film is b,
2. The semiconductor device according to claim 1, wherein when a distance between the first polycrystalline silicon films is c, a relationship of b ≦ a = x <c / 2 is satisfied. 5. A second insulating film formed between the first polysilicon film and the sidewall spacer, and formed on an upper portion of the sidewall spacer and an upper end of the first polysilicon film. The semiconductor device according to claim 1, further comprising: a recessed portion, wherein a thickness of the second insulating film is 20 ° to 40 °. 6. The first polycrystalline silicon film and the second polycrystalline silicon film.
2. The semiconductor device according to claim 1, wherein said polycrystalline silicon film is doped with the same kind of impurity. 7. A step of forming a gate oxide film on a semiconductor substrate, a step of forming a first polysilicon film on the gate oxide film, and a step of forming a first polysilicon film on the first polysilicon film. Forming and patterning one insulating film; and using the patterned first insulating film as a mask,
Removing the first polycrystalline silicon film and the gate oxide film and exposing the surface of the semiconductor substrate; removing the semiconductor substrate in the exposed region to a desired depth; Forming a groove, forming an oxide film on the exposed surfaces of the semiconductor substrate and the first polycrystalline silicon film, forming a second insulating film on the entire surface, and forming the groove A step of embedding, a step of flattening the second insulating film and exposing a surface of the first insulating film, a step of removing the first insulating film, and a step of removing the second insulating film And the oxide film is removed.
Exposing an upper portion of the polycrystalline silicon film, forming a second polycrystalline silicon film on the entire surface, removing the second polycrystalline silicon film, and removing the first polycrystalline silicon film. Forming a sidewall spacer on the side surface of the semiconductor device, and forming an ONO film on the entire surface. 8. The method according to claim 1, wherein the thickness of the side wall spacer is x,
A is the distance from the surface of the insulating film to the surface of the first polycrystalline silicon film, b is the film thickness when the second polycrystalline silicon film is formed, and the distance between the first polycrystalline silicon films is 8. The method of manufacturing a semiconductor device according to claim 7, wherein when the distance is c, a relationship of b ≦ a = x <c / 2 is satisfied. 9. The first polycrystalline silicon film and the second polycrystalline silicon film.
8. The method according to claim 7, wherein the polycrystalline silicon film is doped with the same kind of impurity. 10. The method according to claim 7, wherein said side wall spacer is formed by anisotropic dry etching. 11. A step of forming a gate oxide film on a semiconductor substrate, a step of forming a first polysilicon film on the gate oxide film, and a step of forming a first polysilicon film on the first polysilicon film. Forming and patterning one insulating film; and using the patterned first insulating film as a mask,
Removing the first polycrystalline silicon film and the gate oxide film and exposing the surface of the semiconductor substrate; and removing the semiconductor substrate in the exposed region to a desired depth. Forming a groove portion; forming an oxide film on the exposed surfaces of the semiconductor substrate and the first polycrystalline silicon film; forming a second insulating film on the entire surface; A step of embedding, a step of planarizing the second insulating film and exposing a surface of the first insulating film, a step of removing the first insulating film, and a step of removing the second insulating film And the oxide film is removed.
Exposing an upper portion of the polycrystalline silicon film, forming a third insulating film so as to cover the exposed upper portion of the first polycrystalline silicon film, and forming a second polycrystalline silicon film on the entire surface. Forming a crystalline silicon film; removing the second polycrystalline silicon film and the third insulating film; and forming the third polycrystalline silicon film on a side surface of the first polycrystalline silicon film.
Forming a side wall spacer via the insulating film; and etching back the side wall spacer and a part of the first polycrystalline silicon film, thereby forming an upper portion of the side wall spacer and an upper end portion of the first polycrystalline silicon film. A method of manufacturing a semiconductor device, comprising: a step of forming a concave portion in the substrate; and a step of forming an ONO film on the entire surface. 12. The thickness of the sidewall spacer is x, the distance from the surface of the first insulating film to the surface of the first polycrystalline silicon film is a, and the thickness of the second polycrystalline silicon film is 12. The semiconductor device according to claim 11, wherein when a thickness of the first polycrystalline silicon film is b and a distance between the first polycrystalline silicon films is c, a relationship of b ≦ a = x <c / 2 is satisfied. Manufacturing method. 13. The method according to claim 11, wherein the first polycrystalline silicon film and the second polycrystalline silicon film are doped with the same kind of impurity. 14. The method according to claim 11, wherein the sidewall spacer is formed by anisotropic dry etching. 15. The method according to claim 11, wherein the thickness of the second insulating film is 20 ° to 40 °.