KR100215695B1 - Method for fabricating capacitor of semiconductor device - Google Patents

Abstract

The present invention relates to a method of manufacturing a capacitor of a semiconductor device, and more particularly to a method of manufacturing a capacitor of a semiconductor device capable of increasing the surface area of the charge storage electrode of the capacitor on a silicon on insulator (SOI) substrate. According to the method of manufacturing a semiconductor capacitor, a capacitor of a semiconductor device is embedded in an inner surface of an SOI substrate, and then a subsequent process is performed on the exposed silicon surface to form a capacitor electrode having an increased surface area, and a low power and High speed can be provided, and the characteristics and reliability of the device are improved.

Description

Capacitor Manufacturing Method of Semiconductor Device

1 is a view for explaining a charge storage electrode forming method of a DRAM capacitor of a conventional semiconductor device

2 (a) to 2 (d) are cross-sectional views showing main parts of a capacitor manufacturing method of a semiconductor device according to an embodiment of the present invention.

Explanation of symbols for main parts of the drawings

11: semiconductor substrate 12: field oxide film

l3: gate electrode 13A: spacer

14 nitride film 15 interlayer insulating film

16,18: mask pattern 17 ': storage node electrode

The present invention relates to a method for manufacturing a capacitor of a semiconductor device, and more particularly to a method for manufacturing a capacitor of a semiconductor device capable of increasing the surface area of the charge storage electrode of the capacitor on a silicon on insulator (SOI) substrate.

Recently, with the development of semiconductor manufacturing technology, the demand for memory devices has soared, and the demand for high integrated capacity requiring high capacitance in a small area has been required.

As a method for maximizing the capacity of the capacitor, a method of using an insulator having a high dielectric constant between dielectrics between electrodes or a method of increasing the area of a storage node electrode of a capacitor has been proposed. The proposed method first uses a relatively high dielectric constant film such as an ONO (oxide-nitride-oxide) film or a Ta ₂ O ₅ film as a dielectric between electrodes of the capacitor, and expands the storage node electrode area of the DRAM capacitor. As a method of stacking, a planar or trench type three-dimensional structure has been proposed in the planar capacitor structure, and a double stack fin type and a cylinder type which are more advanced structures are presently developed. And electrodes were prepared in a stack- trench merge.

Here, the method of manufacturing a capacitor of a conventional semiconductor device will be described with reference to FIG. 1 attached to the drawing. First, as shown in the drawing, the element and the device are separated in a predetermined region on the initialized semiconductor substrate 1. The field oxide film 2 is formed in place by a known method.

Then, a gate insulating film 3 is deposited on the structure to a predetermined thickness. In this case, the gate insulating film may be formed of a material that maintains high cleanliness and has high insulation breakdown voltage.

Thereafter, the first polysilicon for forming the gate electrode is formed on the gate insulating layer 3 to have a predetermined thickness, and the gate electrode 4 is formed by etching to a predetermined shape. In general, in the case of current DRAM, two transistors share one drain electrode for low power driving, or four transistors share one drain electrode for even lower power driving, so that most of field oxide and field oxide film are usually used. Two to four gate electrodes 4 are formed per cell.

Then, an insulating film having a predetermined thickness is deposited on the entire structure, and anisotropic blanket etching is performed to form spacers 4A on both side walls of the gate electrode.

Then, impurity ions of the opposite type to the substrate type are ion implanted into the exposed substrate surface to form source and drain electrodes (not shown).

Subsequently, the first IPO layer 5 is formed on the entire structure, the contact hole for forming the storage node electrode is formed, and then the polysilicon 6 for the storage node electrode is formed to a predetermined thickness on the entire structure. , A predetermined portion is etched. A capacitor of a semiconductor device is formed by forming a dielectric film 7 and a polysilicon 8 for a plate electrode on the polysilicon 6 for a storage node electrode.

However, according to the conventional method as described above, there is a problem that it is difficult to meet the high-integration capacity required by the current semiconductor device, and thus, the characteristics and reliability of the semiconductor device are deteriorated.

In addition, in the current highly integrated semiconductor device, as the distance between the devices becomes closer, the power consumption of the device is considerably increased due to the RC delay time due to parasitic capacitance and the leakage current in the junction region, resulting in high speed and low speed of the semiconductor device. There is an inherent problem on the substrate that does not meet the demand for power.

Accordingly, the present invention is to solve the above-mentioned conventional problems, and in forming a capacitor electrode of a semiconductor device, by forming a capacitor electrode having an enlarged surface area on an SOI substrate that provides low power and high speed of the device, An object of the present invention is to provide a method for manufacturing a capacitor of a semiconductor device capable of improving the refresh characteristics and reliability of the semiconductor device.

In order to achieve the above object of the present invention, the present invention comprises the steps of forming a selective oxide film in place of the silicon wafer; Etching the resultant to expose the substrate; Stacking a first polysilicon film and an oxide film on the structure, and etching the first polysilicon film and the oxide film to a predetermined size; Depositing a second polysilicon layer on the structure and blanket etching to form a polysilicon spacer; Applying a photoresist film on the resultant, and forming a photoresist pattern so that an oxide film formed by etching is exposed; Removing the photoresist pattern; Sequentially stacking a dielectric film, a polysilicon film for plate electrodes, a nitride film, and a buffer film on the entire structure surface and polishing the surface to be flattened; Preparing a handling wafer to be attached to the formed silicon wafer; Depositing a planarization insulating film on the handling wafer; Attaching to contact the buffer film of the silicon wafer and the planarization film of the handling wafer; And polishing the silicon wafer surface to expose a silicon film.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 (a) to (e) are cross-sectional views showing main parts of a capacitor manufacturing method of a semiconductor device according to an embodiment of the present invention.

First, as shown in FIG. 2A, the device isolation film 12 is formed in place on the silicon layer 11 of the silicon wafer 100 on which the device is to be formed. Then, the surface of the SOI substrate is etched back. An etch back region 11A is formed.

Subsequently, the first polysilicon and the oxide film for the storage node of the capacitor electrode are sequentially formed on the structure, and the first polysilicon pattern 13 and the oxide film pattern 14 are formed by etching a predetermined portion.

As shown in FIG. 2B, second polysilicon for the storage node is formed on the structure, and then a blanket is etched to form polysilicon spacers 15 on both sidewalls of the oxide layer pattern 14. To form.

Subsequently, as shown in FIG. 2C, a photosensitive film is coated on the resultant product, and the photosensitive film pattern 16 is formed by exposing and developing the oxide film existing inside the polysilicon spacer 15 to be exposed. Next, the exposed oxide film is removed by HF solution.

Thereafter, as shown in FIG. 2 (d), the photoresist pattern 16 is removed by a conventional method, and a thin film of ONO (16: oxide nitride oxide) (ONO) is formed on the structure, and on top of the structure. Polysilicon is deposited to form a plate electrode of the capacitor, and then a predetermined portion is etched to form the plate electrode 17. Subsequently, a nitride film 18 is formed on the plate electrode 17, a thick film buffer film is formed, and the buffer film is polished by a chemical mechanical polishing method to form a flat wafer surface.

Then, as shown in FIG. 2E, a SOI substrate having a planarization insulating film formed on top of the buffer film and on the silicon wafer, for example, a capacitor having an increased surface area therein by bonding to a handling wafer having a BPSG film formed thereon. To form. Then, the exposed silicon substrate 100 is chemically mechanically polished until the underlying field oxide film is exposed to expose the silicon layer to form the capacitor electrode of the desired semiconductor element.

Although not shown in the subsequent steps, the semiconductor DRAM device is formed by forming a word line, a source, and a drain bit line on the exposed silicon layer by a known method.

As described in detail above, according to the present invention, in the method of manufacturing a semiconductor capacitor, a capacitor of a semiconductor element is embedded in an inner surface of an SOI substrate, and then a capacitor electrode having a surface area increased by performing a subsequent process on the exposed silicon surface. In addition to providing a low power and high speed of the device can be provided, the characteristics and reliability of the device is improved.

Various other modifications of the invention are apparent to those skilled in the art without departing from the scope and spirit of the invention, and may be made immediately. Accordingly, the claims appended hereto are not intended to be limited to those described herein, but rather, the claims are intended to cover all of the patentable novelties present in the present invention, including all features that are treated as equivalent to those skilled in the art to which this invention belongs. Interpreted as encompassing features.

Claims (1)

Forming a selective oxide film in place on the silicon wafer; Etching the resultant to expose the substrate; Stacking a first polysilicon film and an oxide film on the structure, and etching the first polysilicon film and the oxide film to a predetermined size; Depositing a second polysilicon layer on the structure and blanket etching to form a polysilicon spacer; Applying a photoresist film on the resultant, and forming a photoresist pattern so that an oxide film formed by etching is exposed; Removing the photoresist pattern; Sequentially stacking a dielectric film, a polysilicon film for plate electrodes, a nitride film, and a buffer film on the entire structure surface and polishing the surface to be flattened; Preparing a handling wafer to be attached to the formed silicon wafer; Depositing a planarization insulating film on the handling wafer; Attaching to contact the buffer film of the silicon wafer and the planarization film of the handling wafer; And polishing the silicon wafer surface to expose a silicon film.