KR100278643B1 - Semiconductor Memory Device Manufacturing Method - Google Patents
Semiconductor Memory Device Manufacturing Method Download PDFInfo
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- KR100278643B1 KR100278643B1 KR1019920019306A KR920019306A KR100278643B1 KR 100278643 B1 KR100278643 B1 KR 100278643B1 KR 1019920019306 A KR1019920019306 A KR 1019920019306A KR 920019306 A KR920019306 A KR 920019306A KR 100278643 B1 KR100278643 B1 KR 100278643B1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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Abstract
본 발명은 셀커패시턴스를 증가시킬 수 있는 반도체 메모리장치 제조방법에 관한 것으로, 반도체기판 위에 제1 절연층을 형성하고 식각하여 제1 콘택홀을 형성한다. 제1콘택홀 내의 반도체 기판에 접촉하는 제1 도전층을 형성하고, 그 상에 제2 절연층을 형성한 후, 순차적으로 패터닝하여 제2절연층 패턴 및 제1도전층 패턴을 형성한다. 제2절연층 패턴 상에 제2도전층을 형성하고 에치 백하고 제2절연층 패턴의 측벽에 제1도전층 패턴에 연결되는 제2도전층 패턴을 형성한다. 제2절연층 패턴을 선택적으로 제거하고, 결과물 상에 제2도전층 패턴을 덮는 두께로 제3 절연층을 형성하고 페터닝하여 제1 도전층의 일부를 노출시키는 제2 콘택홀을 가지는 제3절연층 패턴을 형성한다. 제2콘택홀 내에 노출되는 제1도전층 패턴에 연결되는 실린더 형태의 제3도전층을 형성한다. 제3도전층의 제3절연층 패턴 상을 덮는 부분을 선택적으로 제거하여 제3도전층 패턴, 제2도전층 패턴 및 제1도전층 패턴으로 이루어지는 커패시터의 스토리지 노드를 노출한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor memory device capable of increasing cell capacitance. The present invention forms a first contact layer by etching and forming a first insulating layer on a semiconductor substrate. A first conductive layer is formed in contact with the semiconductor substrate in the first contact hole, a second insulating layer is formed thereon, and then patterned sequentially to form a second insulating layer pattern and a first conductive layer pattern. A second conductive layer is formed and etched back on the second insulating layer pattern, and a second conductive layer pattern connected to the first conductive layer pattern is formed on sidewalls of the second insulating layer pattern. A third having a second contact hole for selectively removing the second insulating layer pattern and forming and patterning a third insulating layer to a thickness covering the second conductive layer pattern on the resultant to expose a portion of the first conductive layer An insulating layer pattern is formed. A third conductive layer having a cylindrical shape connected to the first conductive layer pattern exposed in the second contact hole is formed. A portion of the third conductive layer covering the third insulating layer pattern is selectively removed to expose the storage node of the capacitor including the third conductive layer pattern, the second conductive layer pattern, and the first conductive layer pattern.
Description
제1도 내지 제4도는 종래의 방법에 의한 반도체 메모리장치의 제조방법을 설명하기 위한 단면도들.1 through 4 are cross-sectional views illustrating a method of manufacturing a semiconductor memory device by a conventional method.
제5도 내지 제12도는 본 발명에 의한 반도체 메모리장치의 제조방법을 설명하기 위한 단면도들.5 to 12 are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to the present invention.
제13도는 종래의 스택형, 실린더형 커패시터와 본 발명에 의한 커패시터의 셀커패시턴스를 비교하기 위한 사시도.Figure 13 is a perspective view for comparing the cell capacitance of the conventional stacked, cylindrical capacitor and the capacitor according to the present invention.
본 발명은 반도체 메모리장치 제조방법에 관한 것으로, 특히 정전용량을 증가시키기 위하여 종래의 스택형 커패시터와 실린더형 커패시터를 병합한 새로운 구조의 커패시터를 포함하는 반도체 메모리장치 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to a method of manufacturing a semiconductor memory device including a capacitor having a new structure in which a conventional stacked capacitor and a cylindrical capacitor are integrated to increase capacitance.
반도체장치의 제조가술의 발달로 반도체 기억장치의 집적도는 약3년마다 4배로 증대해 오고 있다. 이러한 집적도의 향상은 기억단위인 메모리 셀의 면적축소에 기인해 왔다. 그러나, 메모리 셀의 면적축소는 필연적으로 데이터 기억을 위한 정전용량의 감소를 가져와서 정보독출능력을 저하시키고 소프트 에러(soft error)율을 증가시킬 뿐만아니라, 저전압에서의 소자의 동작을 어렵게 하여 작동시 전력소모를 과다하게 하기 때문에 반도체장치의 고집적화를 위해서는 반드시 해결해야 할 과제이다.`With the development of semiconductor device manufacturing techniques, the density of semiconductor memory devices has increased four times every three years. This improvement in density has been due to the reduction of the area of the memory cell as a storage unit. However, the reduction of the area of memory cells inevitably leads to a reduction in the capacitance for data storage, thereby lowering the information reading capability and increasing the soft error rate, and making the operation of the device at low voltage difficult. It is a problem that must be solved for high integration of semiconductor devices because it consumes too much power.
통상, 약 1.5㎛2의 메모리셀 면적을 가지는 64Mb급 디램(DRAM)에 있어서는 일반적인 2차원적인 스택형 메모리셀을 사용한다면 Ta2O5와 같은 고유전물질을 사용하더라도 충분한 커패시턴스를 얻기가 힘들기 때문에, 3차원적인 구조의 스택형 커패시터를 제안하여 커패시턴스 향상을 도모하고 있다. 예를 들어, 이중스택(Double Stack)구조, 핀(Fin)구조, 원통현 전극(Cylindrical Electrode)구조, 스프레드 스택(Spread Stack)구조 및 박스(Box)구조는 메모리셀의 셀커패시턴스 증가를 위해 제안된 3차원적 구조의 스토리지전극들이다.In general, in the case of 64Mb DRAM having a memory cell area of about 1.5 μm 2 , it is difficult to obtain sufficient capacitance even when using a general two-dimensional stack type memory cell using a high dielectric material such as Ta 2 O 5 . Therefore, the stack capacitor of the three-dimensional structure is proposed to improve the capacitance. For example, a double stack structure, a fin structure, a cylindrical electrode structure, a spread stack structure, and a box structure are proposed to increase cell capacitance of a memory cell. 3D structured storage electrodes.
3차원적 스택형 커패시터구조에 있어서, 특히 원통구조는 원통의 외면 뿐만아니라 내면까지 유효커패시터 영역으로 이용할 수 있어 64Mb급 메모리셀이나 그 이상급으로 고집적되는 메모리셀에 적합한 구조로 채택되고 있는데, 현재는 원통내부에 원기둥 또는 다른 원통을 첨가함으로써 셀커패시턴스를 향상시키기 위한 커패시터구조가 제안되고 있다.In the three-dimensional stack type capacitor structure, especially the cylindrical structure can be used as an effective capacitor area not only on the outer surface of the cylinder but also on the inner surface, so it is adopted as a structure suitable for 64 Mb-class memory cells or higher density memory cells. A capacitor structure has been proposed for improving cell capacitance by adding a cylinder or other cylinder inside the cylinder.
제1도 내지 제4도는 종래의 방법에 의한 반도체 메모리장치의 제조방법을 설명하기 위해 도시된 단면도로서, 원통내부에 또다른 원통이 첨가된 구조의 스토리지전극 형성방법을 설명한다. 이는 1991년 IEEE지에 발표된 논문. “Crown-Shaped Stacked-Capacitor Cell for 1.5-V Operation 64-Mb DRAM’s”을 참조한다.1 to 4 are cross-sectional views for explaining a method of manufacturing a semiconductor memory device by a conventional method, and explain a method of forming a storage electrode having another cylinder added inside the cylinder. This is a paper published in IEEE in 1991. See "Crown-Shaped Stacked-Capacitor Cell for 1.5-V Operation 64-Mb DRAM's."
제1도는, 필드산화막(101)에 의해 환성영역 및 배활성영역을 구분되어진 반도체기판(100) 상의 상기 활성영역에, 하나의 비트라인(6)과 드레인영역(5)을 공유하고 각각이 하나씩의 소오스영역(4) 및 게이트전극(2)을 구비하는 트랜지스터를 형성하는 공정, 결과물 전면에 상기 트랜지스터를 다른 도전층들(이 후의 공정에 의해 형성될 도전층)로 부터 절연시키기 위한 절연층(8)을 형성하는 공정, 결과물 전면에 평탄화층(10)을 형성하는 공정, 상기 소오스영역(4) 상에 적층되어 있는 절연층 및 평탄화층을 부분적으로 제거하여 콘택홀을 형성하는 공정, 상기 콘택홀을 제1의 다결정실리콘으로 채움으로써 기동전극(16)을 형성하는 공정, 결과물 전면에 제1의 이산화실리콘층(12), 실리콘 나이트라이드층(14) 및 제2의 이산화실리콘층(18)을 적층하는 공정, 각 셀단위로 한정되고 상기 기동전극(16)의 표면이 노출되도록 적층된 물질층에 우물을 형성하는 공정, 결과물 전면에 제2의 다결정실리콘을 증착하여 제1의 다결정실리콘층(20)을 형성하는 공정, 및 제3의 이산화실리콘층을 형성한 후 이방성식각함으로써 상기 우물의 내부 측벽에 제3의 이산화실리콘층으로 된 스페이서(22)를 형성하는 공정에 의해 형성된 반도체장치를 도시한다.1 shows one bit line 6 and one drain region 5 in the active region on the semiconductor substrate 100 in which the annular region and the back active region are separated by the field oxide film 101, and each one is one. Forming a transistor having a source region 4 and a gate electrode 2 of the insulating layer; an insulating layer for insulating the transistor from the other conductive layers (conductive layer to be formed by a subsequent process) 8) forming, forming the planarization layer 10 on the entire surface of the resultant, forming a contact hole by partially removing the insulating layer and the planarization layer stacked on the source region 4, the contact Forming the starting electrode 16 by filling the hole with the first polysilicon; the first silicon dioxide layer 12, the silicon nitride layer 14, and the second silicon dioxide layer 18 on the entire surface of the resultant Lamination process, each cell unit Forming a well in the stacked material layer to expose the surface of the starting electrode 16, and depositing a second polysilicon on the entire surface of the resultant to form the first polysilicon layer 20; And forming a spacer 22 of a third silicon dioxide layer on the inner sidewall of the well by anisotropically etching the third silicon dioxide layer after forming the third silicon dioxide layer.
제2도는, 스페이서가 형성된 상기 반도체기판 전면에 제3의 다결정실리콘을 증착하여 제2의 다결정실리콘층(24)을 형성하는 공정, 및 상기 제2의 다결정실리콘층의 표면이 노출되지 않도록 결과물 전면에 제4의 이산화실리콘층(26)을 형성하는 공정에 의해 형성된 반도체장치를 도시한다.2 is a step of forming a second polysilicon layer 24 by depositing a third polysilicon on the entire surface of the semiconductor substrate on which the spacer is formed, and the entire surface of the resulting product so that the surface of the second polysilicon layer is not exposed. The semiconductor device formed by the process of forming the 4th silicon dioxide layer 26 in FIG.
제3도는 스페이서(22)의 최상부 표면의 높이 정도까지 상기 제4의 이산화실리콘층을 에치백하는 공정, 및 표면으로 노출된 상기 제2의 다결정실리콘층을 이방성식각으로 제거한 후 상기 이방성식각에 의해 표면으로 노출된 상기 제1의 다결정실리콘층을 이방성식각함으로써 스토리지전극(28)을 형성하는 공정에 의해 형성된 반도체장치를 도시한다.3 is a step of etching back the fourth silicon dioxide layer to the height of the top surface of the spacer 22, and removing the second polysilicon layer exposed to the surface by anisotropic etching, followed by the anisotropic etching. A semiconductor device formed by a process of forming the storage electrode 28 by anisotropically etching the first polysilicon layer exposed to the surface is shown.
제4도는 제4의 이산화실리콘층, 스페이서 및 제2의 이산화실리콘층을 제거하는 공정, 상기 스토리지전극(28) 전면에 유전체막(30)을 형성하는 공정, 및 결과물 전면에 제4의 다결정실리콘을 증착하여 플레이트전극(32)을 형성하는 공정에 의해 형성된 반도체장치를 도시한다.4 is a step of removing the fourth silicon dioxide layer, the spacer and the second silicon dioxide layer, forming the dielectric film 30 on the entire surface of the storage electrode 28, and the fourth polysilicon on the entire surface of the resultant. The semiconductor device formed by the process of depositing and forming the plate electrode 32 is shown.
상술한 종래 방법에 의한 반도체 메모리장치의 제조방법에 따르면, 원통내부에 또다른 원통이 첨가된 스토리지전극을 형성할 수 있어 셀커패시턴스를 향상시킬 수는 있으나. 다음과 같은 문제점들이 있다.According to the manufacturing method of the semiconductor memory device according to the conventional method described above, it is possible to form a storage electrode to which another cylinder is added to the inside of the cylinder, thereby improving cell capacitance. There are the following problems.
첫째, 기동전극(제1도에서 설명) 형성을 위해 콘택홀을 형성한 후 제1의 다결정실리콘을 채울 때, 상기 제1의 다결정실리콘이 채워지는 상태에 따라 그 상부에 형성되는 원동의 모양이 좌우되기 때문에 콘택홀 부분에만 상기 제1의 다결정실리콘을 정확하게 채우는 것이 중요한 데, 그 공정이 매우 어렵다.First, when the first polycrystalline silicon is filled after the contact hole is formed to form the starting electrode (described in FIG. 1), the shape of the circular motion formed on the upper portion of the first polycrystalline silicon is changed. It is important to precisely fill the first polysilicon only in the contact hole portion, because the process is very difficult.
둘째, 우물(제1도에서 설명)을 형성하기 위해 상기 제2의 이산화실리콘층을 이방성식각하는 공정시, 상기 우물은 그 측벽이 경사지도록 형성되기가 쉬운데, 이는 플레이트전극 형성시 셀 사이에 구멍(void)을 형성하는 메모리장치의 전기적 특성을 저하시킨다.Second, in the process of anisotropically etching the second silicon dioxide layer to form a well (described in FIG. 1), the well is easily formed such that its sidewalls are inclined, which is a hole between cells in forming a plate electrode. Deteriorates the electrical characteristics of the memory device forming the void.
세째, 제4의 이산화실리콘을 에치백할 때(제3도에서 설명), 그 정도를 조절하기가 힘들기 때문에 균일한 셀커패시턴스 확보가 어렵다.Third, when etching back the fourth silicon dioxide (described in FIG. 3), it is difficult to control the degree, so it is difficult to secure uniform cell capacitance.
네째, 제1의 다결정실리콘층을 형성한 후 제2의 다결정실리콘층을 형성할 때(제2도에서 설명), 상기 제1의 다결정실리콘층 표면에 얇은 자연산화막이 생성되어 메모리장치의 전기적 특성을 저하시킨다.Fourth, when the second polysilicon layer is formed after the first polysilicon layer is formed (described in FIG. 2), a thin natural oxide film is formed on the surface of the first polysilicon layer, thereby providing electrical characteristics of the memory device. Lowers.
다섯째, 원통전극을 끝부분이 뾰족하게 형성되므로 누설전류가 생길 가능성이 많다.Fifth, since the end of the cylindrical electrode is sharply formed, there is a high possibility of leakage current.
따라서, 본 발명의 목적은 셀커패시턴스를 증가시켜 고집적 메모리장치에 유용하게 적용할 수 있는 반도체 메모리장치를 제공함에 있다.Accordingly, an object of the present invention is to provide a semiconductor memory device that can be usefully applied to a highly integrated memory device by increasing cell capacitance.
본 발명의 다른 목적은 상기 반도체 메모리장치를 제조하기 위한 그 적합한 제조방법을 제공함에 있다.Another object of the present invention is to provide a suitable manufacturing method for manufacturing the semiconductor memory device.
상기 목적을 달성하기 위한 본 발명에 의한 반도체 메모리장치의 제조방법은, 반도체기판 위에 제1 절연층을 형성하는 공정; 상기 제1 절연층을 식각하는 상기 반도체기판을 노출시키는 제1 콘택홀을 형성하는 공정; 상기 절연층 상에 상기 제1콘택홀 내의 상기 반도체 기판에 접촉하는 제1 도전층을 형성하는 공정; 상기 제1도전층 상에 제2 절연층을 형성하는 공정; 상기 제2절연층 및 상기 제1도전층을 순차적으로 패터닝하여 제2절연층 패턴 및 제1도전층 패턴을 형성하는 공정; 상기 제2절연층 패턴 상에 제2도전층을 형성하고 에치 백하여 상기 제2절연층 패턴의 측벽에 상기 제1도전층 패턴에 연결되는 제2도전층 패턴을 형성하는 공정; 상기 제2절연층 패턴을 선택적으로 제거하고, 결과물 상에 상기 제2도전층 패턴을 덮는 두께로 제3 절연층을 형성하는 공정; 상기 제3절연층을 패터닝하여 상기 제1 도전층의 일부를 노출시키는 제2 콘택홀을 가지는 제3절연층 패턴을 형성하는 공정; 상기 제3절연층 패턴 상에 상기 제2콘택홀 내에 노출되는 상기 제1도전층 패턴에 연결되며 상기 제2콘택홀의 형상에 의해서 상기 제2콘택홀 내에 형성되는 부분이 실리던 형태를 이루는 제3도전층을 형성하는 공정; 상기 제3절연층 패턴을 노출하도록 상기 제3도전층의 상기 제3절연층 패턴 상을 덮는 부분을 선택적으로 식각하여 제3도전층 패턴을 형성하는 공정; 및 상기 제3절연층 패턴을 선택적으로 제거하여 상기 제3도전층 패턴, 상기 제2도전층 패턴 및 상기 제1도전층 패턴으로 이루어지는 커패시터의 스토리지 노드를 노출하는 공정을 포함하는 것을 특징으로 한다.A method of manufacturing a semiconductor memory device according to the present invention for achieving the above object comprises the steps of forming a first insulating layer on a semiconductor substrate; Forming a first contact hole exposing the semiconductor substrate to etch the first insulating layer; Forming a first conductive layer in contact with the semiconductor substrate in the first contact hole on the insulating layer; Forming a second insulating layer on the first conductive layer; Forming a second insulating layer pattern and a first conductive layer pattern by sequentially patterning the second insulating layer and the first conductive layer; Forming a second conductive layer on the second insulating layer pattern and etching back to form a second conductive layer pattern connected to the first conductive layer pattern on sidewalls of the second insulating layer pattern; Selectively removing the second insulating layer pattern, and forming a third insulating layer on the resultant to have a thickness covering the second conductive layer pattern; Patterning the third insulating layer to form a third insulating layer pattern having a second contact hole exposing a portion of the first conductive layer; A third portion connected to the first conductive layer pattern exposed in the second contact hole on the third insulating layer pattern and having a portion formed in the second contact hole due to the shape of the second contact hole; Forming a conductive layer; Forming a third conductive layer pattern by selectively etching a portion of the third conductive layer covering the third insulating layer pattern so as to expose the third insulating layer pattern; And selectively removing the third insulating layer pattern to expose a storage node of a capacitor including the third conductive layer pattern, the second conductive layer pattern, and the first conductive layer pattern.
이하, 첨부한 도면을 참조하여 본 발명에 대해 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail with respect to the present invention.
제5도 내지 제12도는 본 발명에 따른 반도체 메모리장치의 제조방법의 일실시예를 설명하기 위해 도시한 단면도들이다.5 through 12 are cross-sectional views illustrating an exemplary embodiment of a method of manufacturing a semiconductor memory device according to the present invention.
제5도는 반도체기판 상에 절연층 및 콘택홀을 형성하는 공정을 도시한 것으로, 필드산화막(101)에 의해 활성영역 및 비활성영역으로 구분되어진 반도체기판(100)의 상기 활성영역에, 하나의 드레인영역(34)과 하나의 비트라인(37)을 서로 공유하여 각각이 하나씩의 소오스영역(35)과 게이트전극(33)을 구비하는 두 개의 트랜지스터를 형성한 후, 결과물 전면에 다른 도전층(이 후의 공정에서 형성됨)들로부터 상기 트랜지스터를 전기적으로 분리시키기 위하여 절연물질의 도포한 후 평탄화하여 제1절연층(38)을 형성한다. 이어서, 상기 제1절연층(38) 위에 포토레지스트패턴(40)을 형성한 후, 상기 포토레지스트패턴(40)에 의해 노출된 소오스영역상의 물질들을 제거하여 상기 소오스영역을 표면으로 노출시킴으로써 스토리지전극을 소오스영역에 접촉시키기 위한 제1콘택홀(42)을 형성한다.5 shows a process of forming an insulating layer and a contact hole on a semiconductor substrate, in which one drain is formed in the active region of the semiconductor substrate 100 divided into an active region and an inactive region by the field oxide film 101. After sharing the region 34 and one bit line 37 with each other to form two transistors each having one source region 35 and a gate electrode 33, the other conductive layer ( The first insulating layer 38 is formed by applying an insulating material and then flattening the insulating material to electrically isolate the transistor from the following processes). Subsequently, after forming the photoresist pattern 40 on the first insulating layer 38, the storage electrode by removing the material on the source region exposed by the photoresist pattern 40 to expose the source region to the surface To form a first contact hole 42 for contacting the source region.
제6도는 제1도전층(44)을 형성하는 공정을 도시한 것으로서, 결과물 전면에 예컨대 불순물이 도우프된 다결정실리콘을 도포하거나, 다결정실리콘을 도포한 후 POCl3및 아세닉(As)을 이온주입하여 도우핑하거나 또는 비정질실리콘을 도포한 후 같은 방법으로 도우핑하는 방법등을 사용하여 상기 평탄화된 제1절연층(38)상에 제1도전층(44)을 형성한다. 이때, 상기 제1도전층(44)은 스토리지전극의 단자역할을 하는 것으로서, 두께는 약 500Å∼3,500Å정도로 형성하는 것이 바람직하다.FIG. 6 illustrates a process of forming the first conductive layer 44, and for example, polysilicon doped with impurities or the polysilicon is coated on the entire surface of the resultant, followed by ionization of POCl 3 and arsenic (As). The first conductive layer 44 is formed on the planarized first insulating layer 38 by implanting, doping, or applying amorphous silicon and then doping in the same manner. In this case, the first conductive layer 44 serves as a terminal of the storage electrode, and the thickness of the first conductive layer 44 is preferably about 500 kPa to about 3,500 kPa.
제7도는 제1도전층패턴(44′), 제2절연층패턴(46) 및 제2도전층 형성을 위한 포토레지스트패턴(48)을 형성하는 공정을 도시한 것으로서, 상기 도전층(44) 위에 층간절연막으로 예컨대 BPSG(Boro-Phosporous Silicate Glass), PECVD 산화막과 같은 CVD산화막 또는 HTO(High Temperature Oxide)와 같은 절연물질을 도포하여 제2절연층을 형성한다. 이는 후에 형성될 실린더 커패시터의 측벽 원통을 형성하기 위한 것이다. 이어서, 상기 제2절연층 위에 각 셀 단위로 한정된 모양의 포토레지스트패턴(48)을 형성한 후, 상기 포토레지스트패턴(48)을 식각마스크로 하고, 상기 제2절연층 및 제1도전층을 식각대상물로 한 이방성식각 공정을 차례로 행하여 제2절연층패턴(46) 및 제1도전층패턴(44′)을 형성한다.FIG. 7 illustrates a process of forming the first conductive layer pattern 44 ', the second insulating layer pattern 46, and the photoresist pattern 48 for forming the second conductive layer. The conductive layer 44 A second insulating layer is formed by applying an insulating material such as BPSG (Boro-Phosporous Silicate Glass), a CVD oxide film such as a PECVD oxide film, or a high temperature oxide (HTO) as an interlayer insulating film thereon. This is for forming the side wall cylinder of the cylinder capacitor to be formed later. Subsequently, after the photoresist pattern 48 having a shape defined for each cell unit is formed on the second insulating layer, the photoresist pattern 48 is used as an etching mask, and the second insulating layer and the first conductive layer are formed. An anisotropic etching process as an etching target is sequentially performed to form the second insulating layer pattern 46 and the first conductive layer pattern 44 '.
제8도는 제2도전층 패턴(50′)을 형성하는 공정을 도시한 것으로서, 포토레지스트패턴을 제거한 후 상기 제2절연층패턴(46) 위에 상기 제1도전층을 형성한 물질과 동일한 물질을 도포하여 제2도전층을 형성한 후, 상기 제2도전층을 에치백(etch back)함으로써 제2절연층패턴(46)의 측벽에 원통형의 제2도전층패턴(50′)을 형성함으로써 상기 제1도전층패턴과 함께 실린더형 스토리지전극 패턴을 형성하도록 한다.FIG. 8 illustrates a process of forming the second conductive layer pattern 50 '. The same material as that of forming the first conductive layer on the second insulating layer pattern 46 after removing the photoresist pattern is shown. After coating to form the second conductive layer, the second conductive layer is etched back to form a cylindrical second conductive layer pattern 50 ′ on the sidewall of the second insulating layer pattern 46. The cylindrical storage electrode pattern is formed together with the first conductive layer pattern.
제9도는 제3절연층패턴(54)을 형성하는 공정을 도시한 것으로서, 결과물 전면에 약 1,000Å∼5,000Å 정도의 두께로, 예컨대 PBSG 또는 PECVD산화막과 같은 절연물질을 도포한 후 평탄화하여 제3절연층을 형성한다. 이어서, 상기 제3절연층을 이방성식각함으로써 이미 형성된 실린더 스토리지전극 패턴(제1도전층패턴과 제2도전층패턴을 통칭함)(52)의 콘택홀 부분이 노출되어 후에 형성될 스택 커패시터의 스토리지전극과 접촉될 수 있도록 하기 위한 제2콘택홀을 포함하는 제3절연층패턴(54)을 형성한다.FIG. 9 illustrates a process of forming the third insulating layer pattern 54. A thickness of about 1,000 GPa to 5,000 GPa is applied to the entire surface of the resultant, for example, by applying an insulating material such as PBSG or PECVD oxide to planarization. 3 form an insulating layer; Subsequently, the contact hole portion of the cylinder storage electrode pattern (generally referred to as the first conductive layer pattern and the second conductive layer pattern) 52 formed by anisotropically etching the third insulating layer is exposed to store the stack capacitor to be formed later. A third insulating layer pattern 54 including a second contact hole for contacting the electrode is formed.
제10도는 제3도전층(56)을 형성하는 공정을 도시한 것으로서, 결과물 전면에 상기 제1도전층 및 제2도전층을 형성한 물질과 동일한 물질을 도포함으로써 스택 커패시터의 스토리지전극을 형성하기 위한 제3도전층(56)을 형성한다.FIG. 10 illustrates a process of forming the third conductive layer 56. The storage electrode of the stack capacitor is formed by applying the same material to the first conductive layer and the second conductive layer on the entire surface of the resultant. A third conductive layer 56 for forming is formed.
제11도는 제3도전층패턴(56′)을 형성하는 공정을 도시한 것으로서, 상기 제3도전층위에 포토레지스트패턴(도시되지 않음)을 형성한 후, 상기 포토레지스트패턴(도시되지 않음)을 식각마스크로 하고, 상기 제3도전층을 식각대상물로 한 이방성식각 공정을 결과물 전면에 행함으로써, 도시된 바와 같이 실린더 캐패시터의 스토리지전극 패턴(52) 위에 스택 커패시터의 스토리지전극 패턴(56′)을 형성한다.FIG. 11 illustrates a process of forming a third conductive layer pattern 56 '. After forming a photoresist pattern (not shown) on the third conductive layer, the photoresist pattern (not shown) is formed. By performing an anisotropic etching process using the third conductive layer as an etch target on the entire surface of the resultant as an etch mask, the storage electrode pattern 56 ′ of the stack capacitor is formed on the storage electrode pattern 52 of the cylinder capacitor as shown. Form.
제12도는 유전체막(60) 및 플레이트전극(62) 형성공정을 도시한 것으로서, 결과물 전면에 고유전 물질을 도포함으로써 커패시터의 유전체막(60)을 형성하고, 이어서 결과물 전면에 예컨대 불순물이 도우프된 다결정실리콘과 같은 도전물질을 도포한 후 이방성식각함으로써 플레트전극(62)을 형성한다.FIG. 12 shows the process of forming the dielectric film 60 and the plate electrode 62. The dielectric film 60 of the capacitor is formed by applying a high dielectric material on the entire surface of the resultant material, and then, for example, impurities are doped on the entire surface of the resultant material. The plated electrode 62 is formed by anisotropic etching after applying a conductive material such as polycrystalline silicon.
이로써, 하부는 실린더형 커패시터로 형성되며, 상부는 스택형 커패시터로 이루어진 실린더-스택 병합형의 커패시터를 완성한다.Thus, the lower part is formed of a cylindrical capacitor, and the upper part completes a cylinder-stack merge type capacitor consisting of a stacked capacitor.
제13도는 종래의 스택형 커패시터(A), 실린더형 커패시터(B) 및 본 발명에 의한 커패시터(C)의 셀커패시턴스를 비교하기 위하여 도시한 사시도로서, 동일한 셀면적(1.0x0.4㎛2)을 적용하였을 때 본 발명에 의한 실린더-스택 병합형 커패시터(26.2fF/cell)는 종래의 스택형 커패시터(7.37fF/cell)에 비해 255%, 실린더형 커패시터(13.8fF/cell)에 비해 90%의 셀커패시턴스의 증가를 나타내었다.13 is a perspective view for comparing the cell capacitance of the conventional stacked capacitor (A), the cylindrical capacitor (B) and the capacitor (C) according to the present invention, the same cell area (1.0x0.4㎛ 2 ) According to the present invention, the cylinder stack stack-type capacitor (26.2fF / cell) is 255% compared to the conventional stacked capacitor (7.37fF / cell) and 90% compared to the cylindrical capacitor (13.8fF / cell). An increase in cell capacitance of is shown.
상술한 본 발명에 의한 반도체 메모리장치 및 그 제조방법에 따르면, 종래의 스택형 또는 실린더형의 커패시터에 비해 스토리지전극의 유효면적을 극대화할 수 있으므로, 셀커패시턴스를 증가시킬 수 있으며, 기존 래티클(Reticle)의 변경없이 복잡한 공정을 거치지 않고도 제조할 수 있는 이점이 있다.According to the semiconductor memory device and the manufacturing method thereof according to the present invention described above, the effective area of the storage electrode can be maximized as compared to the conventional stacked or cylindrical capacitor, thereby increasing the cell capacitance and the existing reticle ( There is an advantage that can be manufactured without a complicated process without changing the reticle).
본 발명은 상기 실시예에 한정되지 않으며, 본 발명의 기술적 사상내에서 당분야의 통상의 지식을 가진 자에 의해 많은 변형이 가능함은 물론이다.The present invention is not limited to the above embodiments, and many modifications are possible by those skilled in the art within the technical idea of the present invention.
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| KR100374555B1 (en) * | 2000-11-13 | 2003-03-04 | 주식회사 하이닉스반도체 | Fabricating method of capacitor |
| KR20220047431A (en) | 2020-10-08 | 2022-04-18 | 삼성전자주식회사 | Semiconductor devices and data storage system including the same |
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| US5108943A (en) * | 1991-01-02 | 1992-04-28 | Micron Technology, Inc. | Mushroom double stacked capacitor |
| KR920013718A (en) * | 1990-12-18 | 1992-07-29 | 문정환 | Capacitor Manufacturing Method for High Density Morse Devices |
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| KR920013718A (en) * | 1990-12-18 | 1992-07-29 | 문정환 | Capacitor Manufacturing Method for High Density Morse Devices |
| US5108943A (en) * | 1991-01-02 | 1992-04-28 | Micron Technology, Inc. | Mushroom double stacked capacitor |
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