JP2671359B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
JP2671359B2
JP2671359B2 JP6511688A JP6511688A JP2671359B2 JP 2671359 B2 JP2671359 B2 JP 2671359B2 JP 6511688 A JP6511688 A JP 6511688A JP 6511688 A JP6511688 A JP 6511688A JP 2671359 B2 JP2671359 B2 JP 2671359B2
Authority
JP
Japan
Prior art keywords
opening
semiconductor device
film
insulating film
void
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP6511688A
Other languages
Japanese (ja)
Other versions
JPH01238034A (en
Inventor
信彰 山盛
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP6511688A priority Critical patent/JP2671359B2/en
Publication of JPH01238034A publication Critical patent/JPH01238034A/en
Application granted granted Critical
Publication of JP2671359B2 publication Critical patent/JP2671359B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関する。The present invention relates to a method for manufacturing a semiconductor device.

〔従来の技術〕[Conventional technology]

半導体装置の素子分離方式の一つとしてV字型溝を形
成して絶縁層を充填する溝充填法(Trench isolation)
が知られている。
Trench isolation method of forming a V-shaped groove and filling an insulating layer as one of element isolation methods of a semiconductor device
It has been known.

第2図(a),(b)は従来の半導体装置の製造方法
を説明するための工程順に示した半導体チップの断面図
である。
2 (a) and 2 (b) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a conventional method of manufacturing a semiconductor device.

第2図(a)に示すように、シリコン基板1の上にホ
トレジスト膜3を形成してパターニングし幅約1μmの
開口部4を設ける。次に、第2図(b)に示すように、
KOHによる異法性エッチングによりホトレジスト膜3を
マスクとしてシリコン基板1をエッチングしV字型の溝
7を形成する。
As shown in FIG. 2A, a photoresist film 3 is formed on the silicon substrate 1 and patterned to form an opening 4 having a width of about 1 μm. Next, as shown in FIG. 2 (b),
The silicon substrate 1 is etched by using the photoresist film 3 as a mask by the anisotropic etching with KOH to form a V-shaped groove 7.

〔発明が解決しようとする課題〕[Problems to be solved by the invention]

上述した従来の半導体装置の製造方法は、エッチング
方法としてKOH等の溶液を使用する為、ホトレジストパ
ターンからのサイドエッチが避けられず、従って幅が1
μm未満のV字型の溝の形成が困難であるという欠点が
あった。
In the above-described conventional method for manufacturing a semiconductor device, since a solution such as KOH is used as an etching method, side etching from the photoresist pattern is unavoidable, so that the width is 1
There is a drawback that it is difficult to form a V-shaped groove of less than μm.

本発明の目的は幅が1μm未満の溝充填法による素子
分離層を形成することにより集積度を向上させる半導体
装置の製造方法を提供することにある。
An object of the present invention is to provide a method for manufacturing a semiconductor device in which the degree of integration is improved by forming an element isolation layer having a width of less than 1 μm by a groove filling method.

〔課題を解決するための手段〕[Means for solving the problem]

本発明の半導体装置の製造方法は、半導体基板上に第
1の絶縁膜を形成する工程と、前記第1の絶縁膜を選択
的にエッチングして幅が約1μmの開口部を設ける工程
と、前記開口部を含む表面に第2の絶縁膜を堆積して前
記開口部内にボイドを生じさせる工程と、異方性エッチ
ングにより前記第2の絶縁膜の全面をエッチバックし且
つ前記ボイドの下部の前記半導体基板にV字型の溝を形
成する工程とを含んで構成される。
A method of manufacturing a semiconductor device according to the present invention comprises a step of forming a first insulating film on a semiconductor substrate, a step of selectively etching the first insulating film to provide an opening having a width of about 1 μm, Depositing a second insulating film on the surface including the opening to form a void in the opening; and etching back the entire surface of the second insulating film by anisotropic etching to form a void in the lower portion of the void. And a step of forming a V-shaped groove in the semiconductor substrate.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.

第1図(a)〜(e)は本発明の一実施例を説明する
ための工程順に示した半導体チップの断面図である。
1 (a) to 1 (e) are sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention.

まず、第1図(a)に示すように、シリコン基板1の
上に窒化シリコン膜2を例えばCVD法により堆積する。
次に、窒化シリコン膜2の上にホトレジスト膜3を塗布
してパターニングした後ホトレジスト膜3をマスクにCF
4+H2ガスによるプラズマエッチングにより窒化シリコ
ン膜2をエッチングして約1μm幅の開口部4を形成す
る。
First, as shown in FIG. 1A, a silicon nitride film 2 is deposited on a silicon substrate 1 by, for example, a CVD method.
Next, a photoresist film 3 is applied on the silicon nitride film 2 and patterned, and then CF is used with the photoresist film 3 as a mask.
The silicon nitride film 2 is etched by plasma etching using 4 + H 2 gas to form an opening 4 having a width of about 1 μm.

次に、第1図(b)に示すように、ホトレジスト膜3
を例えばO2プラズマを用いて除去し、開口部4を含む表
面にCVD法により酸化シリコン膜5を堆積する。この際
に、開口部4の内側は段差被覆性が悪くなり空間(以下
ボイドと記す)6が形成される。
Next, as shown in FIG. 1B, the photoresist film 3
Are removed by using, for example, O 2 plasma, and a silicon oxide film 5 is deposited on the surface including the opening 4 by the CVD method. At this time, the step coverage is deteriorated inside the opening 4, and a space (hereinafter referred to as a void) 6 is formed.

次に、第1図(c)に示すように、全表面をイオンミ
リングして酸化シリコン膜5をエッチバックする。この
とき、開口部4にボイド6があるため、ボイド6の下部
の絶縁膜5が除去されると共にシリコン基板1の上部も
順次エッチングされて幅1μm未満のV字型の溝7が形
成される。
Next, as shown in FIG. 1C, the entire surface is ion milled to etch back the silicon oxide film 5. At this time, since there is a void 6 in the opening 4, the insulating film 5 under the void 6 is removed and the upper portion of the silicon substrate 1 is also sequentially etched to form a V-shaped groove 7 having a width of less than 1 μm. .

次に、第1図(d)に示すように、マスクに使用した
酸化シリコン膜5を例えば弗酸により、窒化シリコン膜
2を例えば熱リン酸により順次除去した後、溝7を含む
表面にBPSG膜8を堆積する。
Next, as shown in FIG. 1D, the silicon oxide film 5 used for the mask is sequentially removed by, for example, hydrofluoric acid and the silicon nitride film 2 by, for example, hot phosphoric acid, and then BPSG is formed on the surface including the groove 7. The film 8 is deposited.

次に、第1図(e)に示すように、CF4+H2プラズマ
によりBPSG膜8をエッチバックして、溝7に埋込まれた
BPSG膜8を残し、素子分離用の埋込層とする。
Next, as shown in FIG. 1 (e), the BPSG film 8 was etched back by CF 4 + H 2 plasma and buried in the groove 7.
The BPSG film 8 is left as a buried layer for element isolation.

なお、ここで、窒化シリコン膜2の代りにCVD法で形
成した酸化シリコン膜を用いても良い。
Here, instead of the silicon nitride film 2, a silicon oxide film formed by a CVD method may be used.

〔発明の効果〕〔The invention's effect〕

以上説明したように本発明は、シリコン基板上に設け
た第1の絶縁膜に約1μmの幅の開口部を設け、該開口
部に堆積した第2の絶縁膜にボイドを生じさせ、このボ
イドを利用して異方性エッチングにより、シリコン基板
にV字型の溝を設けることにより、幅1μm未満の素子
分離層を得ることができ、半導体装置の高集積化を向上
させるという効果を有する。
As described above, according to the present invention, an opening having a width of about 1 μm is provided in the first insulating film provided on the silicon substrate, and a void is generated in the second insulating film deposited in the opening. By providing a V-shaped groove in the silicon substrate by anisotropic etching utilizing the above, an element isolation layer having a width of less than 1 μm can be obtained, which has the effect of improving the integration degree of the semiconductor device.

【図面の簡単な説明】[Brief description of the drawings]

第1図(a)〜(e)は本発明の一実施例を説明するた
めの工程順に示した半導体チップの断面図、第2図
(a),(b)は従来の半導体装置の製造方法を説明す
るための工程順に示した半導体チップの断面図である。 1……シリコン基板、2……窒化シリコン膜、3……ホ
トレジスト膜、4……開口部、5……酸化シリコン膜、
6……ボイド、7……溝、8……BPSG膜。
1 (a) to 1 (e) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention, and FIGS. 2 (a) and 2 (b) show a conventional method of manufacturing a semiconductor device. FIG. 4 is a cross-sectional view of a semiconductor chip shown in the order of steps for explaining the method. 1 ... Silicon substrate, 2 ... Silicon nitride film, 3 ... Photoresist film, 4 ... Opening part, 5 ... Silicon oxide film,
6 ... Void, 7 ... Groove, 8 ... BPSG film.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】半導体基板上に第1の絶縁膜を形成する工
程と、前記第1の絶縁膜を選択的にエッチングして幅が
約1μmの開口部を設ける工程と、前記開口部を含む表
面に第2の絶縁膜を堆積して前記開口部内にボイドを生
じさせる工程と、異方性エッチングにより前記第2の絶
縁膜の全面をエッチバックし且つ前記ボイドの下部の前
記半導体基板にV字型の溝を形成する工程とを含むこと
を特徴とする半導体装置の製造方法。
1. A method comprising: forming a first insulating film on a semiconductor substrate; selectively etching the first insulating film to form an opening having a width of about 1 μm; and including the opening. A step of depositing a second insulating film on the surface to generate a void in the opening; and a step of etching back the entire surface of the second insulating film by anisotropic etching and applying V to the semiconductor substrate below the void. And a step of forming a V-shaped groove.
JP6511688A 1988-03-17 1988-03-17 Method for manufacturing semiconductor device Expired - Lifetime JP2671359B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6511688A JP2671359B2 (en) 1988-03-17 1988-03-17 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6511688A JP2671359B2 (en) 1988-03-17 1988-03-17 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH01238034A JPH01238034A (en) 1989-09-22
JP2671359B2 true JP2671359B2 (en) 1997-10-29

Family

ID=13277594

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6511688A Expired - Lifetime JP2671359B2 (en) 1988-03-17 1988-03-17 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2671359B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3092478B2 (en) * 1995-06-16 2000-09-25 日本電気株式会社 Method for manufacturing semiconductor device

Also Published As

Publication number Publication date
JPH01238034A (en) 1989-09-22

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