JPH04303942A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form an element isolation film whose reliability is high by a method wherein before an insulator is filled into a groove, a silicon substrate is thermally oxidized, a second thermal oxide film is formed, an undercut part in a first thermal oxide film is buried by the expansion of a volume due to a thermal oxidation operation, and a dent is eliminated. CONSTITUTION:An Si substrate 1 is thermally oxidized; an oxide film 2 is formed on the surface; and a silicon nitride film 3 and a PSG film 4 are deposited on it. An element-isolation pattern is exposed to light and developed; a resist film 5 having an opening 5a is former. The PSG film 4, the silicon nitride film 3 and the thermal oxide film 2 are etched from the opening 5a by making use of the resist film 5 as a mask; the Si substrate 1 is revealed. The resist film 5 is stripped; after that, the Si substrate 1 is etched by making use of the PSG film 4 as a mask; and a groove 6 is formed. The remaining PSG film 4 is removed. The surface of the Si substrate 1 which has been revealed inside the groove 6 is thermally oxidized; a thermal oxide film 8 is formed. After that, a silicon oxide film 9 is deposited; the groove 6 is buried. The silicon oxide film 9 is polished.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for separating elements formed on a silicon substrate.

[0002] Device isolation of semiconductor devices is usually performed using LOCO
This method is carried out using the S method, but this method inevitably creates a step due to the volume expansion associated with silicon oxidation, and also creates a bird's beak under the mask. This has become an obstacle.

[0003] Therefore, an attempt has been made to dig a trench in a silicon substrate, fill the trench with an insulator, and then flatten the surface to isolate the devices. However, this method has not yet been established and has various problems.

0004

2. Description of the Related Art FIGS. 3(a) to 3(e) are step-by-step sectional views for explaining the problems of the conventional method.The problems of the conventional method will be explained below with reference to these figures.

Referring to FIG. 3A, a Si substrate 1 is thermally oxidized to form a thermal oxide film 2, and a silicon nitrogen film 3 and a PSG film 4 are deposited thereon. A resist is applied thereon, and an element isolation pattern is exposed and developed using photolithography to form a resist mask 5 having openings 5a.

Using the resist mask 5 as a mask, the PSG film 4, silicon nitrogen film 3, and thermal oxide film 2 are etched by reactive ion etching (RIE) to expose the Si substrate 1.

FIG. 3(b) After removing the reference resist mask 5, the Si substrate 1 is etched by RIE using the PSG film 4 as a mask to form a groove 6.

FIG. 3(c) The reference PGS film 4 is removed by etching with dilute hydrofluoric acid. At this time, the thermal oxide film 2 under the silicon nitride film 3 is also etched, creating an undercut 7.

FIG. 3(d) A silicon oxide film 9 is deposited on the entire surface of the reference surface by the CVD method, and grooves 6 are formed.
Embed. FIG. 3(e) The reference silicon oxide film 9 is removed by polishing, leaving the silicon oxide film 9 only in the groove 6, and forming an element isolation film 10. During polishing, the silicon nitrogen film 3 acts as a stopper.

However, coverage of the undercut 7 portion is poor during deposition of the silicon oxide film 9, and a cavity 12 is formed. This cavity 12 remains at the upper end of the element isolation film 10 even after polishing, and therefore has an adverse effect on the subsequent element formation process.

[0011]

SUMMARY OF THE INVENTION In view of the above-mentioned problems, the present invention provides a method for eliminating poor coverage at the upper end of an element isolation film 10 during deposition of a silicon oxide film 9 and forming a highly reliable element isolation film. The purpose is to provide.

0012

[Means for solving the problem] Figures 1(a) to (e)
FIG. 2(a) is a process-order cross-sectional view showing the first embodiment.
-(e) are step-by-step sectional views showing the second embodiment.

The above problem is solved by thermally oxidizing the silicon substrate 1 to form the first thermal oxide film 2, and then removing the nitride film 3 and the glass film 4.
The glass film 4 is deposited in this order and anisotropically etched using a mask 5 having an element isolation pattern.
a step of etching the nitride film 3 and the first thermal oxide film 2; a step of etching the silicon substrate 1 by anisotropic etching using the glass film 4 as a mask to form a groove 6; a step of removing the film 4 by wet etching, and a second step of thermally oxidizing the silicon substrate 1 and burying the undercut 7 generated in the first thermal oxide film 2 under the nitride film 3 by the wet etching. A step of forming a thermal oxide film 8, a step of depositing an insulator 9 on the entire surface to fill the trench 6, and a step of removing the insulator 9 on the nitride film 3 and filling the trench 6 with the insulator 9. and a step of leaving the silicon substrate 1
The problem is solved by a method of manufacturing a semiconductor device in which an element isolation film 10 is formed.

Further, after thermally oxidizing the silicon substrate 1 to form a thermal oxide film 2, a step of depositing a nitride film 3, a silicon oxide film 11, and a glass film 4 in this order, and a mask 5 having an element isolation pattern are performed. a step of etching the glass film 4, the silicon oxide film 11, the nitride film 3, and the thermal oxide film 2 by anisotropic etching using the glass film 4 as a mask; and etching the silicon substrate by anisotropic etching using the glass film 4 as a mask. 1 to form a groove 6, a step of removing the glass film 4 by wet etching, and an undercut of the thermal oxide film 2 and the silicon oxide film 11 caused by the wet etching to form a groove 6 in the upper part of the groove 6. a step of etching and removing the eaves portion 3a of the nitride film 3 protruding from the nitride film 3 using the remaining silicon oxide film 11 as a mask; a step of depositing an insulator 9 on the entire surface to fill the groove 6; a step of removing the insulator 9 and the silicon oxide film 11 on the silicon substrate 3 and leaving the insulator 9 in the groove 6, and forming an element isolation film 10 on the silicon substrate 1. solved by.

[0015]

[Operation] In the present invention, before embedding the insulator 9 in the groove 6,
The second thermal oxide film 8 is formed by thermally oxidizing the silicon substrate 1, and the undercut portion of the first thermal oxide film is buried due to the volume expansion caused by the thermal oxidation, thereby eliminating the depression. 9 is embedded in the groove 6, no poor coverage is caused.

Furthermore, before burying the insulator 9 in the groove 6, the eaves 3a of the nitride film 3 covering the undercut portion of the thermal oxide film 2 are removed by etching to eliminate the depression. When the object 9 is embedded in the groove 6, poor coverage is not caused.

Therefore, a highly reliable device isolation film can be formed.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1(a) to 1(e) are step-by-step cross-sectional views showing a first embodiment, and the first embodiment will be described below with reference to these figures.

FIG. 1(a) A reference Si substrate 1 is thermally oxidized to have a surface thickness of, for example, 100 Å.
A thermal oxide film 2 is formed thereon, and a silicon nitride film 3 having a thickness of, for example, 1500 Å and a PSG film 4 having a thickness of about 5000 Å containing 8% P are sequentially deposited thereon by the CVD method.

A resist is applied to the entire surface, and an element isolation pattern is exposed and developed using a conventional photolithography technique to form a resist mask 5 having openings 5a. Reactive ion etching (RIE) using a fluorocarbon-based etching gas using the resist mask 5 as a mask
As a result, the PSG film 4, silicon nitrogen film 3, and thermal oxide film 2 are etched through the opening 5a, and the Si substrate 1 is exposed.

FIG. 1(b) After peeling off the reference resist mask 5, the Si substrate 1 is etched by RIE using a carbon chloride-based etching gas using the PSG film 4 as a mask to form a groove with a depth of approximately 0.6 μm. 6
form.

Referring to FIG. 1(c), the remaining PGS film 4 is removed by etching with dilute hydrofluoric acid. The etching time is 0.5 to 2 minutes, and at this time, the thermal oxide film 2 under the silicon nitride film 3 is also etched, creating an undercut 7 of 500 to 1000 Å in the lateral direction.

FIG. 1(d) The surface of the Si substrate 1 exposed within the reference groove 6 is thermally oxidized to form a thermal oxide film 8 that completely covers the undercut 7. By thermally oxidizing a portion with a thickness of 300 to 500 Å, the undercut 7 could be completely closed.

Thereafter, a silicon oxide film 9 is deposited to a thickness of about 1 μm over the entire surface by CVD to fill the trenches 6. FIG. 1(e) The reference silicon oxide film 9 is removed by polishing, leaving the silicon oxide film 9 only in the groove 6, and forming an element isolation film 10. During polishing, the silicon nitrogen film 3 acts as a stopper.

In this manner, a highly reliable device isolation film completely filled with an insulator could be formed. Next, a second embodiment will be described.

FIG. 2(a) A reference Si substrate 1 is thermally oxidized to have a thickness of, for example, 300 Å on the surface.
A thermal oxide film 2 is formed thereon, and a silicon nitride film 3 having a thickness of, for example, 1500 Å and a silicon oxide film 11 having a thickness of 3000 Å, for example, are sequentially deposited thereon by the CVD method. Thereafter, heat treatment is performed at 900° C. for 30 minutes in a nitrogen atmosphere. This heat treatment is performed to bring the etching rate of the silicon oxide film 11 closer to that of the thermal oxide film 2.

After this, an 8% film is applied on the silicon oxide film 11.
A PSG film 4 containing P and having a thickness of about 8000 Å is deposited. A resist is applied to the entire surface, and an element isolation pattern is exposed and developed using normal photolithography technology to form the opening 5a.
A resist mask 5 is formed. Using the resist mask 5 as a mask, the PSG film 4, silicon oxide film 11, silicon nitrogen film 3, and thermal oxide film 2 are etched through the opening 5a by RIE using a fluorocarbon-based etching gas, and the Si substrate 1 is exposed. do.

FIG. 2(b) After peeling off the reference resist mask 5, the Si substrate 1 is etched by RIE using a carbon chloride-based etching gas using the PSG film 4 as a mask to form a groove with a depth of approximately 0.6 μm. 6
form.

Referring to FIG. 2(c), the remaining PGS film 4 is removed by etching with dilute hydrofluoric acid. Etching time is 0.5 to 2 minutes. At this time,
The silicon oxide film 11 and the thermal oxide film 2 above and below the silicon nitride film 3 are also etched in the lateral direction, with a thickness of 500 to 10 mm etched in the lateral direction.
This results in an undercut 7 of 00 Å. Silicon oxide film 1
1 is etched slightly more than the thermal oxide film 2, and as a result, an eaves portion 3a protruding above the groove 6 is formed in the silicon nitrogen film 3.

Referring to FIG. 2(d), the silicon nitride film eaves 3a protruding above the grooves 6 are removed by RIE using a carbon chloride-based etching gas.

Thereafter, a silicon oxide film 9 is deposited on the entire surface by CVD to a thickness of about 1 μm, and the trenches 6 are filled. Before depositing the silicon oxide film 9, a step of thinly thermally oxidizing the surface of the Si substrate 1 within the groove 6 may be added.

FIG. 2E: The reference silicon oxide film 9 is removed by polishing, leaving the silicon oxide film 9 only in the groove 6, and forming an element isolation film 10. During polishing, the silicon nitrogen film 3 acts as a stopper.

In this way, a highly reliable element isolation film completely filled with an insulator could be formed. In addition, the PSG film in the first example and the second example is as follows:
It serves as a mask when etching a Si substrate, and is not necessarily limited to PSG films;
A glass film other than the PSG film can be used as long as the etching selectivity of the substrate is high.

Furthermore, although the silicon oxide film 9 deposited on the entire surface was left in the groove 6 by polishing in the above embodiment, RIE
It can also be left in the groove 6 by etching back using.

[0035]

[Effect of the invention] As explained above, according to the present invention,
The insulator can be completely buried in the silicon substrate 1 and the element isolation film 10 can be formed without causing poor coverage.

The present invention contributes to miniaturization and high integration of devices by forming highly reliable device isolation films.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(e) are step-by-step cross-sectional views showing a first embodiment.

FIGS. 2(a) to 2(e) are step-by-step cross-sectional views showing a second embodiment.

FIGS. 3(a) to 3(e) are cross-sectional views in the order of steps for explaining conventional problems.

[Explanation of symbols]

1, the Si substrate 2 is a thermal oxide film, the first thermal oxide film 3 is a nitride film, the silicon nitride film 3a is a glass film, and the PSG film 5 is a mask, and a resist mask 5a. The opening 6, the groove 7, the undercut 8 are thermal oxide films, the second thermal oxide film 9 is an insulator, and is a silicon oxide film, and the CVD oxide film 10 is an element isolation film.

Claims (2)

[Claims] Claim 1: A step of thermally oxidizing a silicon substrate (1) to form a first thermal oxide film (2), and then depositing a nitride film (3) and a glass film (4) in this order, and device isolation. etching the glass film (4), the nitride film (3), and the first thermal oxide film (2) by anisotropic etching using a patterned mask (5); ) to form a groove (6) by anisotropic etching using the silicon substrate (1) as a mask, a step of removing the glass film (4) by wet etching, and a step of removing the glass film (4) by wet etching. The first layer under the nitride film (3) is thermally oxidized and wet etched.
A process of forming a second thermal oxide film (8) to fill in the undercut (7) that has occurred in the thermal oxide film (2), and filling the trench (6) by depositing an insulator (9) on the entire surface. and a step of removing the insulator (9) on the nitride film (3) and leaving the insulator (9) in the groove (6), and forming an element isolation layer on the silicon substrate (1). A method for manufacturing a semiconductor device, comprising forming a film (10). [Claim 2] A step of thermally oxidizing a silicon substrate (1) to form a thermal oxide film (2), and then depositing a nitride film (3), a silicon oxide film (11), and a glass film (4) in this order. Then, the glass film (4), the silicon oxide film (11), the nitride film (3), and the thermal oxide film (2) are etched by anisotropic etching using a mask (5) having an element isolation pattern. and the glass film (4)
etching the silicon substrate (1) by anisotropic etching using as a mask to form a groove (6);
A process of removing the glass film (4) by wet etching, and removing the thermal oxide film (2) produced by the wet etching.
The eaves part (3a) of the nitride film (3) that protrudes above the groove (6) due to the undercut of the silicon oxide film (11) is etched and removed using the remaining silicon oxide film (11) as a mask. process and insulating material (9
) to fill the groove (6), and removing the insulator (9) and the silicon oxide film (11) on the nitride film (3) and filling the groove (6) with the insulator. (9) A method for manufacturing a semiconductor device, comprising the steps of: (9) forming an element isolation film (10) on the silicon substrate (1);