JPH05315439A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a manufacturing method wherein adverse influence is not exerted upon characteristics by completing the cap of BPSG film in a trench, regarding the manufacturing method of a semiconductor device wherein deep trenches and shallow trenches which are different in depth are used for forming element isolation regions. CONSTITUTION:In a semiconductor device, a plurality of element isolation regions different in depth are formed on a substrate 1, which are constituted of shallow trenches 2 and deep trenches 3 formed in the shallow trenches. The title manufacturing method consists of the following; a process for forming the shallow trenches 2 and the deep trenches 3, a process for burying filling material 6 in the shallow trenches 2 and the deep trenches 3 and coating the surface with said material, a process which performs etching-back so as to leave the filling material 6 in the deep trenches, a process for flattening the filling material 6 in the shallow trenches 2 by reflowing, and a process for filling the shallow trenches with cap material 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device using deep trenches and shallow trenches having different depths to form element isolation regions.

In recent years, LSIs have been actively required to have high speed and high integration. To do this, reduce parasitic capacitance and parasitic resistance,
Device flattening and element miniaturization are important. For this reason, it is necessary to use shallow trenches to separate devices from the conventional selective oxidation separation.

Further, it is required that the conventional deep trench element isolation can be performed at the same time as the shallow trench in the filling process and the filling material does not give much stress to the substrate.

[0004]

2. Description of the Related Art FIG. 3 is an explanatory view of a conventional example. In the figure, 27 is a Si substrate, 28 is a shallow trench, 29 is a wide convex portion, 30 is a narrow convex portion, 31 is a deep trench, and 32 is a BPS.
G film, 33 is a sidewall residue, and 34 is a CVDSiO ₂ film.

In the conventional element isolation region forming method as shown in the schematic cross-sectional view in FIG. 3 in order of process, the shallow trench 28 and the shallow trench 28 are formed as shown in FIG.
After forming the deep trench 31 in the Si substrate 27, as shown in FIG.
As shown in (b), Si is used as a filling material in the trench.
The substrate 27 has a thermal expansion coefficient relatively close to that of other filling materials,
Boron-doped phosphosilicate glass, that is, the BPSG film 32, which is easily reflowed by heating, is buried in the shallow trench 28 and the deep trench 31.

However, as shown in FIG.
When the reflow process is performed to flatten the G film 32, the reflow process is performed between the narrow convex portion 30 and the wide convex portion 29 of the remaining substrate surface (the convex portion viewed from the shallow trench) when the shallow trench 28 is formed. The flow of the BPSG film at the time of etching is different, and the BPSG film on the wide convex portion 29 does not completely flow, so that the surface is not flat, and as shown in FIG.
In the step of etching back the upper BPSG film by anisotropic dry etching or the like to fill only in the trench, the BPSG film 32 remains on the sidewall of the shallow trench 28 as a sidewall residue.

Therefore, as shown in FIG. 3E, C using the BPSG film 32 in the trench as a cap material is used.
Even if the VDSiO ₂ film 34 is capped, the sidewall residue 33 is exposed from the cap surface, so that the diffusion layers such as the base and collector of the bipolar device adjacent to the shallow trench 28 and the source and drain of the MOS device are doped with boron or phosphorus. There has been a problem that impurities of opposite conductivity type diffuse and have an adverse effect. In particular, in a bipolar element, impurities diffuse into the adjacent collector layer, the collector contact resistance increases, and the characteristics deteriorate.

[0008]

Therefore, since the cap of the BPSG film in the trench cannot be well formed and the device is manufactured while the surface of the BPSG film 32 is exposed, diffusion of boron or phosphorus into the Si substrate is caused. Will adversely affect the characteristics.

In view of the above points, the present invention performs the entire surface etching to the top of the deep trench in advance before the reflow of the BPSG film to planarize the BPSG film, complete the cap of the BPSG film, and improve the characteristics. The purpose is not to adversely affect.

[0010]

FIG. 1 illustrates the principle of the present invention. In the figure, 1 is a substrate, 2 is a shallow trench, 3 is a deep trench, 4 is a wide recess, 5 is a narrow recess, 6 is a filling material, 7 is a sidewall residue, and 8 is a cap material.

The above problem is caused by the filling material 6, which is BPS.
After the G film is deposited, the entire surface is etched before reflowing to remove the thick BPSG film on the large area of the surface of the substrate 1 which becomes the wide convex portion of the shallow trench 2, and then the side wall of the shallow trench 2 is removed. B left as residue 7
The PSG film may be reflowed and flattened.

After that, a cap material 8 such as a CVDSiO ₂ film is deposited on the substrate 1 on the filling material 6 flattened in the shallow trench 2 and the filling material 6 in the shallow trench 2 is covered. Then, polishing is performed to flatten the entire semiconductor device surface.

That is, an object of the present invention is to provide a semiconductor device using a plurality of element isolation regions having different depths such as a shallow trench 2 and a deep trench 3 on a substrate 1 as shown in FIG. , The surface of the substrate 1 is selectively etched to form shallow trenches 2,
A step of selectively etching the bottom surface of the shallow trench 2 to form a deep trench 3, and filling the shallow trench 2 and the deep trench 3 on the substrate 1 as shown in FIG. Then, a step of coating the filling material 6 and a step of etching back the filling material 6 while leaving the filling material 6 in the deep trench as shown in FIG. 1C, and a step of etching the filling material 6 as shown in FIG. A step of reflowing the filling material 6 in the shallow trench 2 to flatten it, and FIG.
The filling material 6 in the shallow trench 2 as shown in FIG.
It is achieved by including a step of filling the surface with the cap material 8 up to approximately the same surface as the surface of the substrate 1.

[0014]

In the present invention, since the BPSG on the side wall of the convex portion is likely to become thick after reflow on a pattern having a wide convex portion of the shallow trench, it is flattened by reflow after etching back.

[0015]

FIG. 2 is a schematic sectional view in order of the steps of an embodiment of the present invention. In the figure, 9 is a Si substrate, 10 is a buried diffusion layer, 11
Is an epitaxial layer, 12 is a shallow trench, 13 is a deep trench, 14 is a convex portion, 15 is a BPSG film, 16 is a sidewall residue, 17 is a CVDSiO ₂ film, 18 is a collector contact diffusion layer, 19 is a base extraction electrode, and 20 is A cover SiO ₂ film, 21 is a base, 22 is an emitter extraction electrode, 23 is an emitter, 24 is an emitter electrode, 25 is a base electrode, and 26 is a collector electrode.

As shown in FIG. 2 (a), a buried diffusion layer 10 is formed in advance, and a shallow trench 2 is formed to a depth of 1 μm on a substrate 9 on which an epitaxial layer 11 has been grown. Deep trench 13 to 3μ
It is formed to a depth of m.

As shown in FIG. 2B, on the Si substrate 9,
The shallow trench 12 and the deep trench 13 are filled with a BPSG film 15 of 1 μm as a filling material by the CVD method.
Deposit to a thickness of m. As shown in FIG. 2 (c), BP
The SG film is entirely etched by wet and dry etching. Then, the BPSG film 15 remains as a side wall residue on the side wall of the convex portion which is the surface of the substrate left by the trench formation, that is, on the side wall of the shallow trench 12.

As shown in FIG. 2D, in order to eliminate the side wall residue, reflow is performed at 900 to 1,000 ° C. for 30 to 60 minutes to flatten the BPSG film 15 in the shallow trench 12.

As shown in FIG. 2 (e), the shallow trench 2 is filled up with a CVD SiO ₂ film 17 as a cap material by using Si.
A 1 μm thick layer is deposited on the substrate 15 and polishing is performed to planarize the surface of the Si substrate 9.

After that, the emitter self-aligned bipolar transistor to which the present invention is applied is completed by a normal process.

[0021]

As described above, according to the present invention,
Since the BPSG film is pre-etched and then reflowed for both a pattern having a wide convex portion and a narrow pattern for the shallow trench, the surface of the BPSG film is not exposed at the side wall portion of the shallow trench, and the characteristics are not adversely affected.

Therefore, ideal element isolation can be formed, which greatly contributes to high speed and high integration of the device.

[Brief description of drawings]

FIG. 1 is an explanatory view of the principle of the present invention.

FIG. 2 is a schematic cross-sectional view in order of the processes of an embodiment of the present invention.

FIG. 3 is an explanatory diagram of a conventional example.

[Explanation of symbols]

1 Substrate 2 Shallow Trench 3 Deep Trench 4 Wide Recess 5 Narrow Recess 6 Filling Material 7 Sidewall Residue 8 Cap Material 9 Si Substrate 10 Buried Diffusion Layer 11 Epitaxial Layer 12 Shallow Trench 13 Deep Trench 14 Convexity 15 BPSG Film 16 Sidewall Residue 17 CVDSiO ₂ film 18 collector contact diffusion layer 19 base extraction electrode 20 cover SiO ₂ film 21 base 22 emitter extraction electrode 23 emitter 24 emitter electrode 25 base electrode 26 collector electrode

Claims (2)

[Claims] 1. A semiconductor device comprising a substrate (1), a shallow trench (2), a deep trench (3) in the shallow trench, and a plurality of element isolation regions having different depths. The shallow trench (2) is formed by selectively etching the surface of the substrate (1) to form the shallow trench (2).
A step of selectively etching the bottom surface to form a deep trench (3), filling the shallow trench (2) and the deep trench (3) on the substrate (1), and filling material (6) And the step of etching back the filling material (6) while leaving the deep trench (3) in the deep trench (3), and reflowing the filling material (6) in the shallow trench (2) to flatten it. And a step of filling the surface of the filling material (6) in the shallow trench (2) with a cap material (8) up to substantially the same surface as the substrate (1). Production method. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the filling material (6) is made of a BPSG film, and the cap material (8) is made of a vapor phase grown silicon dioxide film.