JPH05315442A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To fill a trench with filling material like an insulating film, without generating cavities, when element isolation regions are formed by using a plurality of trenches different in depth, regarding the formation of element isolation regions in an LSI. CONSTITUTION:The manufacturing method is constituted of the following; a process forming shallow trenches 2 on an Si substrate 1 in a semiconductor device having trench type element isolation regions different in depth, a process filling the shallow trenches 2 and depositing an SiO2 film 3 on the Si substrate 1, a process forming deep trenches on the Si substrate 1 which trenches penetrate the SiO2 film 3 and are deeper than at least the shallow trenches, a process depositing a BPSG film 5 on the Si substrate 1 so as to fill the deep trenches, and a process etching-back the BPSG film 5 and the SiO2 film 3 on the Si substrate 1 until the surface of the Si substrate 1 is exposed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the formation of element isolation regions in LSI. In recent years, along with the demand for large-capacity and high-speed LSI, it is necessary to miniaturize the element isolation region.

[0002]

2. Description of the Related Art FIG. 4 is an explanatory view of a conventional example. In the figure, 30 is a Si substrate, 31 is a field SiO ₂ film, 32 is a trench, 33 is a trench SiO ₂ film, 34 is a poly-Si film, and 35 is a cap.
It is a SiO ₂ film.

Recently, in a bipolar device, a trench isolation method has been used as a method of forming an element isolation region because a selective oxidation method is not very suitable for miniaturization of an element. Combination of selective oxidation and deep trench as shown in Fig. 4 or
There were many structures having only deep trenches as shown in (b).

However, these element isolation region forming methods also have a problem in that there is a limit to miniaturization and an increase in wiring capacitance. Therefore, recently, a structure in which a shallow trench (shallow groove) and a deep trench are combined has been proposed, but a cavity is generated when the filling material is filled in the trench, or a polycrystalline silicon ( When the poly-Si) film is filled, there is a problem that a defect occurs in the Si substrate or the like due to a difference in thermal expansion coefficient during cap oxidation of the surface of the poly-Si film.

[0005]

Therefore, in a miniaturized trench, it is difficult to fill the inside of the trench with a conventional filling material so as not to form a cavity, and the device is miniaturized and the parasitic capacitance is reduced. Was a hindrance to the progress.

In view of the above points, the present invention is directed to formation of an element isolation region using a plurality of trenches having different depths.
It is provided for the purpose of filling a filling material such as an insulating film without forming voids in the trench.

[0007]

FIG. 1 illustrates the principle of the present invention. In the figure, 1 is a substrate, 2 is a first recess, and 3
Is a first filler, 4 is a second recess, and 5 is a second filler.

After forming the first recess 2 which becomes a shallow trench in the substrate 1, the inside of the first recess 2 is filled and a first filling material 3 such as an insulator is deposited on the substrate 1. Next, the second concave portion 4 to be a deep trench is formed, the inside thereof is filled, and the second filling material 5 such as an insulator is deposited on the substrate 1.

Subsequently, the first filler and the second filler are simultaneously etched back until the surface of the substrate 1 is exposed,
A plurality of trench type element isolation regions having different depths are formed. That is, an object of the present invention is to provide a semiconductor device having trench type element isolation regions having different depths as shown in FIG.
As shown in FIG. 1A, a step of forming a first recess 2 in the substrate 1 and as shown in FIG. 1B, the first recess 2 is filled on the substrate 1 to form a first recess 2. The step of depositing the filling material 3 of the above, and as shown in FIG. 1 (c), the first filling material 3 is penetrated through the substrate 1 to form a second recess 4 deeper than at least the first recess 2 And a step of depositing a second filling material 5 on the substrate 1 as shown in FIG. 1D, and filling the second recess 4 with the second filling material 5. This is accomplished by removing the second filler 5 and the first filler 3 on the substrate 1 until the surface of the substrate 1 is exposed, as shown.

[0010]

In the present invention, for trenches having different depths,
Since different kinds of fillers can be used, it is possible to select and use a filler that does not cause voids in the trench when the filler is filled in the trench.

If an insulator is used as the filling material,
Since the cap oxidation is not required, the problem of defects such as the substrate which is a problem at the time of cap oxidation does not occur, and the element isolation region can be miniaturized and the parasitic capacitance can be reduced.

[0012]

2 and 3 are explanatory views of an embodiment of the present invention, which are schematic sectional views in order of steps.

In the figure, 6 is a Si substrate, 7 is a high-concentration buried diffusion layer, 8 is an epitaxial layer, 9 is a SiO ₂ film, and 10 is Si _3.
N ₄ film, 11 poly-Si film, 12 resist film, 13 shallow trench, 14 thermal SiO ₂ film, 15 CVD SiO ₂ film, 16 resist film, 17 deep trench, 18 trench SiO ₂ film, 19
Is a Si ₃ N ₄ film, 20 is a BPSG film, 21 is a collector contact diffusion layer, 22 is a poly-Si base extraction electrode, 23 is a base diffusion layer, 24 is a cover SiO ₂ film, 25 is a poly-Si emitter extraction electrode, 2
6 is an emitter diffusion layer, 27 is an emitter electrode, 28 is a base electrode, and 29 is a collector electrode.

An example of manufacturing an emitter self-aligned bipolar transistor to which the trench filling method of the present invention is applied in forming an element isolation region on a Si substrate is shown in FIG.
This will be described with reference to FIG.

First, as shown in FIG. 2A, arsenic is ion-implanted on a P-type Si substrate 6 to form an n ⁺ -type high-concentration buried diffusion layer 7. As shown in FIG. 2B, an n-type epitaxial layer is formed to a thickness of 1.5 μm.

As shown in FIG. 2C, the SiO ₂ film 9
Å, Si ₃ N ₄ film 10 is formed to a thickness of 2,000 Å, and poly Si film 11 is formed to a thickness of 1,000 Å. As shown in FIG. 2D, the resist film
Using 12 as a mask, poly-Si film 11, Si ₃ N 4 film 10, SiO ₂ film 9
Is etched, and a shallow trench is formed in the epitaxial layer 8 to a depth of about 4,000 Å using the Si ₃ N ₄ film 10 as a mask.

As shown in FIG. 2 (e), the inside of the shallow trench 13 is thermally oxidized to cover the surface with a thermal SiO ₂ film 14 to a thickness of 200 Å, and then the CVD SiO ₂ film is shallow trenched by the CVD method. Simultaneously with embedding in 13 and depositing on the Si substrate 6 with a thickness of about 6,000Å.

As shown in FIG. 3 (f), the CVD SiO ₂ film 15 is etched using the resist film 16 as a mask, and further,
A deep trench 17 reaching the Si substrate 6 is formed to a depth of about 4.5 μm.

As shown in FIG. 3 (g), the inside of the deep trench 17 is oxidized to cover the surface with the trench SiO ₂ film 18, and the entire surface of the Si substrate 6 including the deep trench 17 is subjected to CV.
The Si ₃ N ₄ film 19 is formed to a thickness of 300 Å by the D method.

After that, the BPSG film 20 is formed into a deep trench.
After filling the inside of 17 and depositing on the Si substrate 6 to a thickness of about 1.5 μm, the surface is flattened by reflowing for 30 minutes at 950 ° C. in wet (O ₂ ).

As shown in FIG. 3H, the BPSG film 20 and the CVD SiO ₂ film 15 on the surface of the Si substrate 6 are made flush with the surface of the epitaxial layer 8 on the Si substrate 6 by dry etching or polishing. Until then, the Si ₃ N ₄ film 10 is used as a stopper to etch back.

The Si ₃ N ₄ film 10 and the SiO ₂ film 9 are removed by etching to flatten the surface of the Si substrate 6. After that, a bipolar transistor is completed as shown in FIG. 3 (i) using a conventional emitter self-aligned bipolar transistor manufacturing method.

In the embodiment, BPSG is used as the second filling material to be embedded in the deep trench, but SOG may be used. In this case, a reflow step for flattening after coating is unnecessary, and the temperature is 800 ° C. or lower. The above heat treatment is sufficient, and it is possible to lower the heat treatment temperature.

In any case, there is no need to form a cap SiO ₂ film as in the case where a poly-Si film is buried in a trench, and problems such as defect generation of a Si substrate are eliminated, and miniaturization can be easily performed. It

[0025]

As described above, according to the present invention,
CVDSiO ₂ film and BPSG, or CVDSiO ₂ film and SOG
As described above, for the trenches having different depths, a filler such as an insulating film suitable for each trench can be selected, and different fillers are etched back at the same time. Can be formed.

Therefore, the present invention can realize an element isolation region which is fine and has a reduced parasitic capacitance, and greatly contributes to the increase in the capacity and the speed of the element.

[Brief description of drawings]

FIG. 1 is an explanatory view of the principle of the present invention.

FIG. 2 is an explanatory diagram (1) of an embodiment of the present invention.

FIG. 3 is an explanatory diagram of an embodiment of the present invention (part 2).

FIG. 4 is an explanatory diagram of a conventional example.

[Explanation of symbols]

1 Substrate 2 First Recess 3 First Filler 4 Second Recess 5 Second Filler 6 Si Substrate 7 High Density Buried Diffusion Layer 8 Epitaxial Layer 9 SiO ₂ Film 10 Si ₃ N ₄ Film 11 Poly Si Film 12 resist film 13 shallow trench 14 thermal SiO ₂ film 15 CVD SiO ₂ film 16 resist film 17 deep trenches 18 trench SiO ₂ film 19 Si ₃ N ₄ film 20 BPSG film 21 collector contact diffusion layer 22 of poly Si-based extraction electrode 23 base diffusion layer 24 Cover SiO ₂ film 25 Poly-Si emitter extraction electrode 26 Emitter diffusion layer 27 Emitter electrode 28 Base electrode 29 Collector electrode

Claims (3)

[Claims] 1. In a semiconductor device having trench-type element isolation regions of different depths, a step of forming a first recess (2) in a substrate (1), and a step of forming the first recess (2) in the substrate (1). Filling the first recess (2) and depositing the first filling material (3), and penetrating the first filling material (3) through the substrate (1), at least the first filling material (3) Forming a second recess (4) deeper than the recess (2), and filling the second recess (4) on the substrate (1) and depositing a second filling material (5) A step of removing the second filling material (5) and the first filling material (3) on the substrate (1) until the surface of the substrate (1) is exposed. Device manufacturing method. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the first filling material is vapor grown silicon dioxide, and the second filling material is boron-doped phosphosilicate glass. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the first filling material is vapor grown silicon dioxide, and the second filling material is spin-on-glass.