JPS6325708B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit device, and more particularly to the structure of an element isolation region that electrically isolates elements incorporated in an integrated circuit device.

Generally, in a semiconductor integrated circuit device, many elements are incorporated into one semiconductor substrate.
In order for these elements to function independently, they must be electrically insulated.

Conventionally, for this purpose, for example, in integrated circuit devices using a silicon semiconductor substrate, a silicon oxide film obtained by oxidizing a silicon substrate has been used.As a method of forming this silicon oxide film into an arbitrary pattern, Selective oxidation methods are widely used. In this method, the silicon surface is exposed only in the portion where the silicon oxide film is to be formed, the other portions are covered with a silicon nitride film, and the silicon surface is selectively oxidized. However, this method has the following drawbacks. First, distortion occurs in the substrate due to oxidation at high temperatures for a long period of time. Second, the silicon oxide film grows laterally up to the portion covered with the silicon nitride film and penetrates beneath it, which impedes improvement in the degree of integration. Thirdly, it requires oxidation for a long time and is poor in mass productivity.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an integrated circuit device that eliminates the above-mentioned drawbacks, has an element isolation structure that occupies a small area, and can improve integration density.

An integrated circuit device of the present invention includes a concave groove provided in an element isolation region of a semiconductor substrate, a silicon oxide film provided on the surface of the concave groove, and a silicon nitride film formed on the silicon oxide film. and borophosphorus glass that fills the groove.

In the integrated circuit device of the present invention, the element isolation region is almost limited to the vertical groove portion, so the isolation region does not spread laterally as in the conventional selective oxidation method, making it easy to achieve high integration. The boron phosphorus glass film that fills the groove has high fluidity and can be reflowed at a relatively low temperature, so the groove can be completely filled with a boron phosphorus glass film with a thickness that is approximately the same as the depth of the groove, and the element surface can be easily In addition, the stress caused by the expansion of the silicon substrate during heat treatment during device fabrication is absorbed by the highly fluid boron phosphorus glass film, making it possible to planarize the silicon substrate near the device isolation region. It also has the effect of minimizing the generated distortion.

Next, in order to better understand the present invention, the present invention will be explained using drawings.

FIGS. 1A to 1E are cross-sectional views showing the manufacturing process order for explaining the manufacturing method of the present invention.

First, as shown in FIG. 1A, a photoresist film 102 is selectively provided on the surface of the P-type silicon substrate 101 so that the area where the element isolation region is to be formed is exposed. Using this photoresist film 102 as a mask, the substrate 101 is etched using an etching method that does not involve side etching, such as a reactive ion etching method, to form concave grooves 1.
03 will be provided. Further, using the photoresist film 102 as a mask, an acceptor type impurity such as boron is ion-implanted to form a P ⁺ region 104 on the bottom surface of the groove 103.

Next, as shown in FIG. 1b, the photoresist film 102 is removed, and the silicon substrate 101 is entirely oxidized to form a silicon oxide film 1 with a thickness of 1000 to 2000 Å.
05 will be provided. A silicon nitride film 106 is provided on this silicon oxide film 105 to a thickness of about 1000 Å. Next, using deivolein, phosphine, silane, and oxygen as source gases, the borophosphorus glass 1 was deposited on the silicon nitride film 106 at a temperature of about 400°C.
Figure 1c forming 07.

Further, as shown in FIG. 1d, heat treatment is performed in a steam or nitrogen atmosphere at 950 DEG C. to 1000 DEG C. to fluidize the boron phosphorus glass 107 and flatten the wafer surface.

Finally, as shown in FIG. 1e, the silicon oxide film 105, the silicon oxide film 1
06. The boron phosphorus glass 107 is selectively etched away using photoresist to complete the element isolation region. Thereafter, active elements are formed in areas other than the grooves 103 by a conventional method to obtain an integrated circuit device of the present invention. It is desirable that the process temperature during the manufacture of this active element be lower than the planarization temperature shown in FIG.

In the element isolation region formed by the manufacturing method described above, the concave groove 103 is formed using an etching method with less side etching such as reactive ion etching, and the silicon oxide film 105 obtained by oxidizing the groove 103 is used. Since the thickness of the trench 103 is about 1000 to 2000 Å, the width of the element isolation region in the lateral direction from the wall surface of the trench 103 is only about 1000 Å. Furthermore, the silicon oxide film 105 is covered with a silicon nitride film 106. Therefore, even when flattening the boron phosphorus glass, the width of the element isolation region can be made almost the same as the width of the trench 103 to prevent boron and phosphorus from diffusing to the side surfaces, resulting in a high-density integrated circuit. It has the advantage of being suitable for

Furthermore, since the boron phosphorus glass film 107 is a highly fluid material, the stress caused by thermal expansion of the silicon substrate is absorbed by the boron phosphorus glass, resulting in extremely small strain on the silicon substrate, which improves the characteristics of active elements adjacent to the element isolation region. also has the advantage of being very good.

Furthermore, most of the material filling the groove 103 is boron phosphorus glass, and as mentioned above, the boron phosphorus glass has high fluidity and can easily flatten the surface, making the lithography process after forming the element isolation region easy. Moreover, it has the advantage that there is little risk of disconnection of the aluminum (Al) wiring formed in the final stage, and it is extremely easy to mass-produce.

FIG. 2 is a sectional view of a second embodiment of the invention. In this second embodiment, the silicon substrate 1 is etched by slightly etching the entire surface of the substrate by reactive ion etching after the process explained in FIG.
The silicon oxide film 105, silicon nitride film 106, and boron phosphorus glass 107 remaining on the surface of 01 other than the element isolation region are removed. This second embodiment has the advantage that the silicon oxide film 105 and the silicon nitride film 106 can be easily removed from the surface of the region where the element is to be incorporated without a mask, thereby simplifying the process. Similarly, after the step explained in FIG. 1d, the boron phosphorus glass 107 is first etched with a hydrofluoric acid-based etching solution, then the silicon nitride film 106 is etched with an etching solution containing phosphoric acid, and finally the silicon nitride film 106 is etched with an etching solution containing phosphoric acid. Furthermore, by removing the silicon oxide film 105 using a hydrofluoric acid etching solution, element isolation regions can be determined without a mask, which greatly helps in improving the degree of integration.

As described in detail above, according to the present invention, it is possible to obtain an integrated circuit device that has an element isolation region that occupies a small area, has an improved integration density, and can be mass-produced.

[Brief explanation of the drawing]

1A to 1E are cross-sectional views of the manufacturing process order for explaining the manufacturing method of the first embodiment of the present invention, and FIG. 2 is a cross-sectional view of the second embodiment of the present invention. 101... P type silicon substrate, 102... Photoresist film, 103... Groove, 104... P type region, 105... Silicon oxide film, 106... Silicon nitride film, 107... Boron phosphorous glass.

Claims (1)

[Claims] 1. A concave groove formed on one main surface of a semiconductor substrate, a silicon oxide film provided on the surface of the concave groove, a silicon nitride film formed on the silicon oxide film, and the concave groove. An integrated circuit device comprising an element isolation region including boron phosphorus glass formed on the silicon nitride film within the silicon nitride film.