JPS57180146A - Formation of elements isolation region - Google Patents

Formation of elements isolation region

Info

Publication number
JPS57180146A
JPS57180146A JP6552881A JP6552881A JPS57180146A JP S57180146 A JPS57180146 A JP S57180146A JP 6552881 A JP6552881 A JP 6552881A JP 6552881 A JP6552881 A JP 6552881A JP S57180146 A JPS57180146 A JP S57180146A
Authority
JP
Japan
Prior art keywords
layers
grooves
buried
isolation
sio2
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6552881A
Other languages
Japanese (ja)
Other versions
JPS6139735B2 (en
Inventor
Junji Sakurai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP6552881A priority Critical patent/JPS57180146A/en
Publication of JPS57180146A publication Critical patent/JPS57180146A/en
Publication of JPS6139735B2 publication Critical patent/JPS6139735B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Bipolar Transistors (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To enhance yield of an IC by a method wherein non-single crystal Si layers are buried in isolation grooves provided for isolation between elements, and heat treatment is performed to convert the layers thereof into SiO2 layers from the upper faces toward the insides and the opening parts, and are used for isolation between the elements. CONSTITUTION:A photo resist pattern 4 is formed on a layer 3 of a P type Si substrate 1 consisting of N<+> type buried layers 2 and the N type epitaxial layer 3, etching is performed using the pattern thereof as the mask, and the isolation grooves 5 to enter the substrate 1 are dug to form the islands shape containing the layers 2 respectively in the layers 3. Then an SiO2 film 6 and an Si3N4 film 7 are adhered being laminated on the whole surface containing the side walls of the grooves 5, and the unsingle crystal Si layers 8 are piled up thereon being made to be disconnected in the grooves 5. Then the upper parts of the layers 8 in the grooves 5 are buried with negative resist layers 9, and etching is performed to remove the layers 8 on the surface together with the film 7. Then the layers 9 in the grooves 5 are removed to expose the layers 8 buried in the grooves 5, and heat treatment is performed to convert the buried layers into the SiO2 films 10 expanding volume thereof to be used as the isolation regions 11.
JP6552881A 1981-04-30 1981-04-30 Formation of elements isolation region Granted JPS57180146A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6552881A JPS57180146A (en) 1981-04-30 1981-04-30 Formation of elements isolation region

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6552881A JPS57180146A (en) 1981-04-30 1981-04-30 Formation of elements isolation region

Publications (2)

Publication Number Publication Date
JPS57180146A true JPS57180146A (en) 1982-11-06
JPS6139735B2 JPS6139735B2 (en) 1986-09-05

Family

ID=13289597

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6552881A Granted JPS57180146A (en) 1981-04-30 1981-04-30 Formation of elements isolation region

Country Status (1)

Country Link
JP (1) JPS57180146A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59106133A (en) * 1982-12-09 1984-06-19 Nec Corp Integrated circuit device
JPS6097661A (en) * 1983-11-02 1985-05-31 Hitachi Ltd Semiconductor integrated circuit device

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0446418Y2 (en) * 1986-05-26 1992-10-30
JPH0542174Y2 (en) * 1987-08-26 1993-10-25
JPH0439935Y2 (en) * 1987-09-28 1992-09-18

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59106133A (en) * 1982-12-09 1984-06-19 Nec Corp Integrated circuit device
JPS6325708B2 (en) * 1982-12-09 1988-05-26 Nippon Electric Co
JPS6097661A (en) * 1983-11-02 1985-05-31 Hitachi Ltd Semiconductor integrated circuit device

Also Published As

Publication number Publication date
JPS6139735B2 (en) 1986-09-05

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