JPS57100734A - Etching method for semiconductor substrate - Google Patents
Etching method for semiconductor substrateInfo
- Publication number
- JPS57100734A JPS57100734A JP17667480A JP17667480A JPS57100734A JP S57100734 A JPS57100734 A JP S57100734A JP 17667480 A JP17667480 A JP 17667480A JP 17667480 A JP17667480 A JP 17667480A JP S57100734 A JPS57100734 A JP S57100734A
- Authority
- JP
- Japan
- Prior art keywords
- etching
- region
- silicon dioxide
- depth
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000005530 etching Methods 0.000 title abstract 7
- 239000000758 substrate Substances 0.000 title abstract 5
- 238000000034 method Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 10
- 235000012239 silicon dioxide Nutrition 0.000 abstract 5
- 239000000377 silicon dioxide Substances 0.000 abstract 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 239000000463 material Substances 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Weting (AREA)
Abstract
PURPOSE:To form recess regions of different depth on the same substrate by utilizing the difference of etching rate between the substrate and the mask with the etchant. CONSTITUTION:A silicon dioxide film 2 is formed on a silicon substrate 1, the silicon dioxide film of shallow recess region is removed, the silicon dioxide film 4 is formed in a thickness of 600mum at the part 3, a region 5 removed with the silicon dioxide film of the deep recess region is formed by etching, the substrate 1 and the silicon dioxide becoming mask materials start etching with an etchant for simultaneously etching both, the etching is continued until the film 4 of shallow recess region is removed, the depth of the deep region becomes 25mum, the etching is further proceeded, and is stopped when the depth of the shallow region 8 becomes 15mum, and then the depth of the deep recess region 6 becomes 40mum.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17667480A JPS57100734A (en) | 1980-12-15 | 1980-12-15 | Etching method for semiconductor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17667480A JPS57100734A (en) | 1980-12-15 | 1980-12-15 | Etching method for semiconductor substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57100734A true JPS57100734A (en) | 1982-06-23 |
| JPS6359532B2 JPS6359532B2 (en) | 1988-11-21 |
Family
ID=16017733
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17667480A Granted JPS57100734A (en) | 1980-12-15 | 1980-12-15 | Etching method for semiconductor substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57100734A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5683546A (en) * | 1992-10-23 | 1997-11-04 | Ricoh Seiki Company, Ltd. | Method of etching silicon substrate at different etching rates for different planes of the silicon to form an air bridge |
| CN109445245A (en) * | 2018-10-15 | 2019-03-08 | 上海华虹宏力半导体制造有限公司 | A kind of method of mask plate, wafer, crystal grain and plasma etching sliver |
-
1980
- 1980-12-15 JP JP17667480A patent/JPS57100734A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5683546A (en) * | 1992-10-23 | 1997-11-04 | Ricoh Seiki Company, Ltd. | Method of etching silicon substrate at different etching rates for different planes of the silicon to form an air bridge |
| CN109445245A (en) * | 2018-10-15 | 2019-03-08 | 上海华虹宏力半导体制造有限公司 | A kind of method of mask plate, wafer, crystal grain and plasma etching sliver |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6359532B2 (en) | 1988-11-21 |
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