JPS57154855A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS57154855A
JPS57154855A JP4011081A JP4011081A JPS57154855A JP S57154855 A JPS57154855 A JP S57154855A JP 4011081 A JP4011081 A JP 4011081A JP 4011081 A JP4011081 A JP 4011081A JP S57154855 A JPS57154855 A JP S57154855A
Authority
JP
Japan
Prior art keywords
formed
region
element
manufacture
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4011081A
Inventor
Kenji Murakami
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP4011081A priority Critical patent/JPS57154855A/en
Publication of JPS57154855A publication Critical patent/JPS57154855A/en
Application status is Pending legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76281Lateral isolation by selective oxidation of silicon

Abstract

PURPOSE:To easily control the impurity density when an element is formed by a method wherein the element is isolated by forming a dielectric region in a semiconductor substrate. CONSTITUTION:A photoresist film 2 is formed on the expected element forming region 4 on the semiconductor substrate 1. Then, an anisotropic etching is performed using the film 2 as a mask, and a groove 5 is formed. Subsequently, the films 6 and 7 located on the bottom 5a are removed. Then, a dielectric region 8 is formed by performing thermal oxidation. Accordingly, the region 4 can be isolated dielectrically from the substrate 1 using the region 8.
JP4011081A 1981-03-19 1981-03-19 Manufacture of semiconductor device Pending JPS57154855A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4011081A JPS57154855A (en) 1981-03-19 1981-03-19 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4011081A JPS57154855A (en) 1981-03-19 1981-03-19 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS57154855A true JPS57154855A (en) 1982-09-24

Family

ID=12571712

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4011081A Pending JPS57154855A (en) 1981-03-19 1981-03-19 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS57154855A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6072243A (en) * 1983-09-28 1985-04-24 Matsushita Electric Ind Co Ltd Semiconductor ic device
JPS6074452A (en) * 1983-09-29 1985-04-26 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
JPS60127740A (en) * 1983-12-15 1985-07-08 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit device
EP0978872A1 (en) * 1998-08-03 2000-02-09 SGS-THOMSON MICROELECTRONICS S.r.l. An inexpensive method of manufacturing an SOI wafer
US6110798A (en) * 1996-01-05 2000-08-29 Micron Technology, Inc. Method of fabricating an isolation structure on a semiconductor substrate
US6339004B1 (en) * 1999-03-25 2002-01-15 Anam Semiconductor Inc. Method of forming shallow trench isolation for preventing torn oxide
US6350657B1 (en) 1998-08-03 2002-02-26 Stmicroelectronics S.R.L. Inexpensive method of manufacturing an SOI wafer
US6465865B1 (en) 1996-01-05 2002-10-15 Micron Technology, Inc. Isolated structure and method of fabricating such a structure on a substrate

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5612749A (en) * 1979-07-12 1981-02-07 Matsushita Electric Ind Co Ltd Production of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5612749A (en) * 1979-07-12 1981-02-07 Matsushita Electric Ind Co Ltd Production of semiconductor device

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6072243A (en) * 1983-09-28 1985-04-24 Matsushita Electric Ind Co Ltd Semiconductor ic device
JPS6074452A (en) * 1983-09-29 1985-04-26 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
JPS60127740A (en) * 1983-12-15 1985-07-08 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit device
US6559032B2 (en) 1996-01-05 2003-05-06 Micron Technology, Inc. Method of fabricating an isolation structure on a semiconductor substrate
US6110798A (en) * 1996-01-05 2000-08-29 Micron Technology, Inc. Method of fabricating an isolation structure on a semiconductor substrate
US6465865B1 (en) 1996-01-05 2002-10-15 Micron Technology, Inc. Isolated structure and method of fabricating such a structure on a substrate
US6479370B2 (en) 1996-01-05 2002-11-12 Micron Technology, Inc. Isolated structure and method of fabricating such a structure on a substrate
US6350657B1 (en) 1998-08-03 2002-02-26 Stmicroelectronics S.R.L. Inexpensive method of manufacturing an SOI wafer
EP0978872A1 (en) * 1998-08-03 2000-02-09 SGS-THOMSON MICROELECTRONICS S.r.l. An inexpensive method of manufacturing an SOI wafer
US6339004B1 (en) * 1999-03-25 2002-01-15 Anam Semiconductor Inc. Method of forming shallow trench isolation for preventing torn oxide

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