JPS5527659A - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor deviceInfo
- Publication number
- JPS5527659A JPS5527659A JP10108378A JP10108378A JPS5527659A JP S5527659 A JPS5527659 A JP S5527659A JP 10108378 A JP10108378 A JP 10108378A JP 10108378 A JP10108378 A JP 10108378A JP S5527659 A JPS5527659 A JP S5527659A
- Authority
- JP
- Japan
- Prior art keywords
- film
- glass layer
- openings
- semiconductor substrate
- selectively
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
PURPOSE: To prevent the occurrence of pin holes in a phosphor glass layer by performing the connection of metallic wiring and a semiconductor substrate in the openings formed in the phosphor glass layer.
CONSTITUTION: On a p-type semiconductor substrate 11, insulating films 12 and 13 consisting of silicon oxide films are formed selectively, and after openings 14 are formed in the silicon film 12, a polycrystalline silicon film 15 is overlapped over the surface and an oxidation resistant insulating film 16 is formed. Next, forming the first pattern of 17, 18, 19, etc., on the films 15 and 16 and using it as a mask, the film 13 is etched and the semiconductor substrate 11 is exposed. Next, after forming a phosphor glass layer 20 all over the surface, openings 21 are formed, the film 16 is exposed selectively, the surface of the glass layer 20 is smoothed by a heat treatment at a high temperature, and at the same time, impurities are duffused from the film 15 and the glass layer 20 to the substrate 11, and thus the n-type duffusion layer 22 of sources, drains, etc., is formed. Next, the selectively exposed film 16 is removed to expose the film 15, and a metallic wiring layer 23 is formed.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10108378A JPS5527659A (en) | 1978-08-18 | 1978-08-18 | Method of manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10108378A JPS5527659A (en) | 1978-08-18 | 1978-08-18 | Method of manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5527659A true JPS5527659A (en) | 1980-02-27 |
| JPS6115579B2 JPS6115579B2 (en) | 1986-04-24 |
Family
ID=14291195
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10108378A Granted JPS5527659A (en) | 1978-08-18 | 1978-08-18 | Method of manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5527659A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4499653A (en) * | 1983-11-03 | 1985-02-19 | Westinghouse Electric Corp. | Small dimension field effect transistor using phosphorous doped silicon glass reflow process |
| JPS61181147A (en) * | 1985-02-06 | 1986-08-13 | Nec Corp | Manufacture of semiconductor device |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR0126400B1 (en) * | 1989-02-17 | 1997-12-24 | 로버트 엔.콘 | Method for detecting protective layer on composite materials |
-
1978
- 1978-08-18 JP JP10108378A patent/JPS5527659A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4499653A (en) * | 1983-11-03 | 1985-02-19 | Westinghouse Electric Corp. | Small dimension field effect transistor using phosphorous doped silicon glass reflow process |
| JPS61181147A (en) * | 1985-02-06 | 1986-08-13 | Nec Corp | Manufacture of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6115579B2 (en) | 1986-04-24 |
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