JPS5527662A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device

Info

Publication number
JPS5527662A
JPS5527662A JP10108678A JP10108678A JPS5527662A JP S5527662 A JPS5527662 A JP S5527662A JP 10108678 A JP10108678 A JP 10108678A JP 10108678 A JP10108678 A JP 10108678A JP S5527662 A JPS5527662 A JP S5527662A
Authority
JP
Japan
Prior art keywords
film
pattern
semiconductor substrate
conductor film
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10108678A
Other languages
Japanese (ja)
Inventor
Kazuhiko Tsuji
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP10108678A priority Critical patent/JPS5527662A/en
Publication of JPS5527662A publication Critical patent/JPS5527662A/en
Pending legal-status Critical Current

Links

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: To prevent poor contact with a semiconductor substrate by covering the semiconductor substrate with the first coductor film to protect the surface of the semiconductor substrate from being stained by photo-sensitive resin films, developers, etc.
CONSTITUTION: Forming an insulator film 12 with opening holes on a semiconductor substrate 11, an impurity duffusion layer 13 is formed, and on the layer, the first conductor layer 14 is formed all over, the first pattern 15 is formed with a photo- sensitive resin film, and using the first pattern 15 as a mask, the conductor film 14 is made thinner by etching. Next, the second conductor film 17 is formed all over the surface and a photo-sensitive resin film 18 is formed in a pattern inverse to the first pattern 15. Next, after etching the second conductor film 17 using the resin film 18 as a mask, the resin films 15 and 18 are removed, and using a pattern 19 formed with the conductor film 17 as a mask, the first conductor film 14 is etched and a bilateral conductor film 21 is formed.
COPYRIGHT: (C)1980,JPO&Japio
JP10108678A 1978-08-18 1978-08-18 Method of manufacturing semiconductor device Pending JPS5527662A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10108678A JPS5527662A (en) 1978-08-18 1978-08-18 Method of manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10108678A JPS5527662A (en) 1978-08-18 1978-08-18 Method of manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
JPS5527662A true JPS5527662A (en) 1980-02-27

Family

ID=14291281

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10108678A Pending JPS5527662A (en) 1978-08-18 1978-08-18 Method of manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPS5527662A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180023964A (en) 2015-07-28 2018-03-07 키타가와고우교가부시끼가이샤 Manufacturing method of reverse osmosis membrane

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180023964A (en) 2015-07-28 2018-03-07 키타가와고우교가부시끼가이샤 Manufacturing method of reverse osmosis membrane

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