JPS6473643A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6473643A
JPS6473643A JP23030687A JP23030687A JPS6473643A JP S6473643 A JPS6473643 A JP S6473643A JP 23030687 A JP23030687 A JP 23030687A JP 23030687 A JP23030687 A JP 23030687A JP S6473643 A JPS6473643 A JP S6473643A
Authority
JP
Japan
Prior art keywords
film
etching
mask
insulating film
patterns
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23030687A
Other languages
Japanese (ja)
Inventor
Shinji Sugaya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP23030687A priority Critical patent/JPS6473643A/en
Publication of JPS6473643A publication Critical patent/JPS6473643A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To prevent a disconnection due to stress migration from occurring by covering an insulating film becoming a mask for etching on a second conductor film, forming a resist pattern corresponding to a wiring pattern, sequentially patterning the insulating film, the second film and a first conductor film, and removing by dry etching means etching residue on a substrate with the insulating film for an etching mask as a mask. CONSTITUTION:An impurity diffused region 3 and a first inter layer insulating film 4, such as source/drain regions are formed on a region formed by a field oxide film 2 on a silicon substrate 1, and a contact window 5 for exposing the region 3 is formed. Then, it is covered with an Al-Si alloy film 6, a TiN film 7, and an SiO2 film 8. Thereafter, first and second resist patterns 9A, 9B corresponding to wiring patterns are formed on the film 8. Subsequently, with the patters 9A, 9B as masks the films 8, 7, 6 are sequentially patterned. Then, the patterns 9A, 9B are removed. Thereafter, with the same film 8 as a mask Si residue 10 covering the film 4 is removed. In this case, the film 7 is protected without etching.
JP23030687A 1987-09-14 1987-09-14 Manufacture of semiconductor device Pending JPS6473643A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23030687A JPS6473643A (en) 1987-09-14 1987-09-14 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23030687A JPS6473643A (en) 1987-09-14 1987-09-14 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6473643A true JPS6473643A (en) 1989-03-17

Family

ID=16905765

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23030687A Pending JPS6473643A (en) 1987-09-14 1987-09-14 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6473643A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07235539A (en) * 1994-02-25 1995-09-05 Sony Corp Multilayer wiring and dry etching thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07235539A (en) * 1994-02-25 1995-09-05 Sony Corp Multilayer wiring and dry etching thereof

Similar Documents

Publication Publication Date Title
US3699646A (en) Integrated circuit structure and method for making integrated circuit structure
KR940016513A (en) Low resistance contact formation method of semiconductor device
EP0724292A3 (en) Method for forming multilevel interconnections in a semiconductor device
GB2106713A (en) Method of making an integrated circuit
JPS6489470A (en) Manufacture of semiconductor device
KR100443064B1 (en) Image Reversal Method for Forming Small Scale Structures in Integrated Circuits
KR100190365B1 (en) Semiconductor device manufacturing of photomask & forming method thereof
EP0779556B1 (en) Method of fabricating a semiconductor device
JPH02260441A (en) Semiconductor element
KR0122315B1 (en) Micro-patterning method of semiconductor
JPS6473643A (en) Manufacture of semiconductor device
JPH02117153A (en) Method of forming semiconductor element
JPS5660030A (en) Manufacture of semiconductor device
JPS5527659A (en) Method of manufacturing semiconductor device
JP2817226B2 (en) Method for manufacturing semiconductor device
KR100187654B1 (en) Method of fabricating semiconductor device
JPS5461490A (en) Multi-layer wiring forming method in semiconductor device
JPS5648151A (en) Wiring formation of semiconductor device
JPS54162490A (en) Manufacture of semiconductor device
KR100252892B1 (en) Method for forming metal-line of semiconductor device
JPS5455375A (en) Production of semiconductor device
KR100257081B1 (en) Method of forming wiring in semiconductor device using oxidation of polysilicon
KR0166488B1 (en) Fine contact forming method in the semiconductor device
KR960026194A (en) Manufacturing Method of Semiconductor Device
JPH0391243A (en) Manufacture of semiconductor device