JPS6236390B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit device, and more particularly to the structure of an element isolation region that electrically isolates elements incorporated in an integrated circuit device.

Generally, in a semiconductor integrated circuit device, many elements are incorporated into one semiconductor substrate.
In order for these elements to function independently, they must be electrically insulated. In order to achieve this electrical insulation, it is necessary to separate the elements with a substance that is considered to be an electrical insulator.

Conventionally, for this purpose, a silicon oxide film obtained by oxidizing a silicon substrate has been used, for example, in an integrated circuit device using a silicon semiconductor substrate. A method called the LOCOS method is widely used to form this silicon oxide film into an arbitrary pattern. In this method, the silicon surface is exposed only in the portion where the silicon oxide film is to be formed, the other portions are covered with a silicon nitride film, and the silicon surface is selectively oxidized. However, in the LOCOS method, the silicon oxide film that grows in the area not covered with the silicon nitride film grows laterally to the area covered with the silicon nitride film. When the thickness of the silicon oxide film in that part becomes about 1.0 μm, it extends laterally by 1.5 to 2.0 μm and penetrates under the silicon nitride film. In integrated circuit devices, the goal is to further improve the integration density in the future, but the problem of lateral spreading of the silicon oxide film is that the element isolation region becomes wider than the intended width. This has the disadvantage that the area in which the elements are incorporated becomes narrower, which impedes improvement in the degree of integration.

The present invention provides an integrated circuit device which eliminates the above-mentioned drawbacks, has an element isolation structure that occupies a small area, and can improve the integration density.

An integrated circuit device of the present invention includes a concave groove provided in an element isolation region of a semiconductor substrate, a first silicon oxide film provided on the surface of the concave groove, and a first silicon oxide film formed to cover the silicon oxide film. A silicon nitride film, a second silicon oxide film obtained by oxidizing polysilicon formed on the silicon nitride film, and a silica film obtained by heat-treating a silica film formed on the second silicon oxide film. and a third silicon oxide film.

Next, embodiments of the present invention will be described using the drawings.

1A to 1E are cross-sectional views showing the order of manufacturing steps for explaining the manufacturing method of the first embodiment of the present invention.

First, as shown in FIG.
2 will be provided. Using this photoresist film 12 as a mask, the substrate 11 is etched to form concave grooves 13 using an etching method that does not involve side etching, such as reactive ion etching. Further, using the photoresist film 12 as a mask, an acceptor type impurity such as boron is ion-implanted to form a P-type region 14 on the bottom surface of the groove 13.

Next, as shown in FIG. 1B, the photoresist film 12 is removed and the silicon substrate 11 is entirely oxidized to form a silicon oxide film 15 having a thickness of 1000 to 2000 Å. A silicon nitride film 16 with a thickness of several thousand angstroms is provided on this silicon oxide film 15, and a polysilicon film 17 is formed thereon.

Next, as shown in FIG. 1c, a silica film 18 is formed on the polysilicon film 17 by a coating method.

Next, as shown in FIG. 1d, the silica film 18 is changed into a third silicon oxide film 20 by heat treatment in an oxidizing atmosphere at 1000 to 1100°C, and the polysilicon film 17 is also changed into a second silicon oxide film. Change it to 19.

Finally, as shown in FIG. 1e, the first, second, third silicon oxide films 15,
19, 20, the silicon nitride film 16 is selectively etched away using photoresist to complete the element isolation region.

Using the manufacturing method explained above, the concave groove 13
For the formation of the groove 13, an etching method with less side etching, such as reactive ion etching, is used. The extent of the element isolation region in the lateral direction from the wall surface is only about 1000 Å, and furthermore, since the first silicon oxide film 15 is covered with the silicon nitride film 16, the silicon oxide film 20 is removed after the silicon film 18 is applied. There is a great advantage that the width of the element isolation region can be made almost the same as the width of the trench 13 because the side surfaces of the structure 13 are not oxidized at all during oxidation to change the structure.

Furthermore, the volume expansion when the polysilicon film 17 is oxidized and changes to the silicon oxide film 19 is as follows.
The volumetric shrinkage that the silica film 18 undergoes during heat treatment is compensated for and canceled out, and the strain exerted on the silicon substrate 11 by the element isolation region can be minimized, allowing the P-N junction of the elements formed within the silicon substrate 11 to be minimized. Even if P- is in contact with the element isolation region,
It also has the great advantage that the reverse leakage current of the N junction can be made extremely small and good device characteristics can be obtained.

FIG. 2 is a sectional view of a second embodiment of the invention.

In this second embodiment, the entire surface of the substrate is slightly etched by reactive ion etching after the process described in FIG. The silicon oxide film 15, silicon nitride film 16, second oxide film 19, and third silicon oxide film 20 are removed. In this second embodiment as well, each insulating film is etched, but since it is thick when viewed in the depth direction, only the necessary amount remains for sufficient device isolation, and silicon can be easily etched from the surface of the region where the device is to be incorporated without a mask. Oxide films 15, 19, 20 and silicon oxide film 16
It has the advantage that it is removed. Similarly, after the step explained in FIG. 1d, the silicon oxide films 20 and 19 are first etched with a hydrofluoric acid-based etching solution, then the silicon nitride film 16 is etched with an etching solution containing phosphoric acid, and finally the silicon nitride film 16 is etched with an etching solution containing phosphoric acid. Furthermore, a method of removing the silicon oxide film 15 using a hydrofluoric acid-based etching solution allows the element isolation regions to be determined without a mask, which greatly helps in improving the degree of integration.

As described in detail above, according to the present invention, it is possible to obtain an integrated circuit device that has an element isolation region that occupies a small area and improves the integration density, so that the present invention is highly effective.

[Brief explanation of the drawing]

1A to 1E are cross-sectional views of the manufacturing process order for explaining the manufacturing method of the first embodiment of the present invention, and FIG. 2 is a cross-sectional view of the second embodiment of the present invention. DESCRIPTION OF SYMBOLS 11... P-type silicon substrate, 12... Photoresist film, 13... Groove, 14... P-type region, 15...
...First silicon oxide film, 16... Silicon nitride film, 17... Polysilicon film, 18... Silica film, 19... Second silicon oxide film, 20...
...Third silicon oxide film.

Claims (1)

[Claims] 1. A concave groove provided in an element isolation region of a semiconductor substrate, a first silicon oxide film provided on the surface of the concave groove, a silicon nitride film formed to cover the silicon oxide film, and a silicon nitride film formed to cover the silicon oxide film. A second silicon oxide film obtained by oxidizing polysilicon formed on a nitride film, and a third silicon oxide film obtained by heat treating a silica film formed on the second silicon oxide film. An integrated circuit device comprising an element isolation region comprising: