JPH01143231A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01143231A JPH01143231A JP30091187A JP30091187A JPH01143231A JP H01143231 A JPH01143231 A JP H01143231A JP 30091187 A JP30091187 A JP 30091187A JP 30091187 A JP30091187 A JP 30091187A JP H01143231 A JPH01143231 A JP H01143231A
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline silicon
- silicon film
- insulating layer
- film
- insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 31
- 238000005530 etching Methods 0.000 claims abstract description 14
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 6
- 239000001301 oxygen Substances 0.000 claims abstract description 5
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 5
- 238000002955 isolation Methods 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 7
- 238000010438 heat treatment Methods 0.000 claims description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- -1 oxygen ions Chemical class 0.000 abstract description 5
- 239000012535 impurity Substances 0.000 abstract description 4
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 3
- 230000001133 acceleration Effects 0.000 abstract description 3
- 239000011261 inert gas Substances 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 3
- 238000007669 thermal treatment Methods 0.000 abstract 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 239000002023 wood Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
Ｃ産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特に絶縁分離溝
の形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION C. Industrial Application Field The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming an isolation trench.
従来、この種の半導体装置の製造方法は、まず、第２図
（ａ）に示すように、例えば表面にＮ型不純物層２を有
するＰ型半導体（シリコン）基板１に所定パターンの講
３を形成し、しかる後に、第２図（ｂ ）に示すように
、溝３の表面に酸化又はＣＶＤ法で絶縁膜４をつけ、そ
の後に分離部を埋込むために多結晶シリコン［５を成長
させ、次に、第２図（ｃ）に示すように、エッチハック
法を用いて全面エツチングにより千世化を行なって素子
領域表面を露出させることにより絶縁分離溝を形成して
いた。Conventionally, in the manufacturing method of this type of semiconductor device, first, as shown in FIG. 2(a), a predetermined pattern 3 is formed on a P-type semiconductor (silicon) substrate 1 having, for example, an N-type impurity layer 2 on the surface. After that, as shown in FIG. 2(b), an insulating film 4 is formed on the surface of the groove 3 by oxidation or CVD, and then polycrystalline silicon [5] is grown to fill the isolation part. Next, as shown in FIG. 2(c), the entire surface is etched using the etch hack method to expose the surface of the element region, thereby forming an insulating isolation groove.
ト述した従来の半導体装置の製造方法は、多結晶シリコ
ンＨ９のエッチバックにより平坦化を行なっているので
、多結晶シリコン膜成長時の気相条件及び基板状態によ
って結晶粒径等が大きく変化し、エツチング速度がばら
つくためともずれは７１４部と素子形成部の間で段差か
できやすい。又、渚内部に残った。多結晶シリコンの表
面形状もいびつになり、その後の工程に於いて段差被覆
性の悪い電極配線が形成され易く品質又は歩留が低下す
るという欠点がある。In the conventional semiconductor device manufacturing method described above, the polycrystalline silicon H9 is planarized by etching back, so the crystal grain size etc. vary greatly depending on the gas phase conditions and substrate conditions during polycrystalline silicon film growth. Also, due to variations in etching speed, misalignment tends to create a step between the 714 portion and the element forming portion. Also, it remained inside the beach. The surface shape of the polycrystalline silicon also becomes distorted, and electrode wiring with poor step coverage is likely to be formed in subsequent steps, resulting in a reduction in quality and yield.
本発明の半導体装置の製造方法は、半導体基板の一主表
面から厚さ方向に向って所定形状の溝を形成する工程と
、前記溝の表面に絶縁膜を被着したのち多結晶シリコン
膜を堆積させる工程と、前記多結晶シリコン膜に窒素又
は酸素をイオン注入したのち熱処理を行ない前記絶縁膜
と前記多結晶シリコン膜の界面近傍に絶縁層を形成する
工程と、前記多結晶シリコン膜をエツチングして前記絶
縁層を露出させる工程とにより絶縁分離溝を形成すると
いうものである。The method for manufacturing a semiconductor device of the present invention includes the steps of forming a groove of a predetermined shape in the thickness direction from one main surface of a semiconductor substrate, and depositing an insulating film on the surface of the groove, and then depositing a polycrystalline silicon film. a step of depositing, a step of ion-implanting nitrogen or oxygen into the polycrystalline silicon film and then performing heat treatment to form an insulating layer near the interface between the insulating film and the polycrystalline silicon film, and etching the polycrystalline silicon film. and exposing the insulating layer to form an insulating isolation trench.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ）〜（ｄ）は本発明の一実施例を説明するた
めの工程順に配置した半導体チップの断面図である。FIGS. 1(a) to 1(d) are cross-sectional views of semiconductor chips arranged in the order of steps for explaining one embodiment of the present invention.
まず、第１図（ａ）に示すように、表面にＮ型不純物層
２をエピタキシャル成長法により形成したＰ型半導体基
板１（シリコン）の表向に幅１μｍの溝３をホトリソグ
ラフィー技術とエツチング技術を用いて形成する。First, as shown in FIG. 1(a), a groove 3 with a width of 1 μm is formed on the surface of a P-type semiconductor substrate 1 (silicon) on which an N-type impurity layer 2 is formed by epitaxial growth using photolithography and etching techniques. Form using.
次に第１図（ｂ）に示すように、薄い酸化シリコンから
なる絶縁膜４を形成し、しかる後に渦３を埋込むために
多結晶シリコンｌ模５を厚さ１）ｔｍ成長する。ここま
では従来例と同しで、ろる。次に、第１図（Ｃ）に示す
ように、加速電圧４６０ｋｅｖ、 ドーズ量１×１０１
３〜１０Ｘ１０ ”ｃｍ−３の条件（投影飛程ＲＰか多
結晶シリコン膜５の厚さ１μｍ前後になるように）て多
結晶シリコン１１９５に、窒素をイオン注入し、しかる
漫に不活性カス雰囲気中で温度０００〜］００（−）℃
で熱処理を行ない。窒化シリコンからなる絶縁１１ｕ
５の界面に形成する。Next, as shown in FIG. 1(b), a thin insulating film 4 made of silicon oxide is formed, and then a polycrystalline silicon layer 5 is grown to a thickness of 1) tm in order to bury the vortex 3. Up to this point, it's the same as the conventional example. Next, as shown in FIG. 1(C), the acceleration voltage was 460 kev and the dose was 1×101
Nitrogen ions are implanted into polycrystalline silicon 1195 under conditions of 3 to 10 x 10" cm-3 (so that the projected range RP or the thickness of the polycrystalline silicon film 5 is approximately 1 μm), and then an inert gas atmosphere is introduced. Temperature inside: 000~]00(-)℃
Heat treatment is performed. Insulation 11u made of silicon nitride
Formed at the interface of No.5.
次に第１図＜（」）に示すように、多結晶シリコン膜５
をエツチング技術を用いて除去し、絶縁層０を露出させ
絶縁分離溝を形成する。絶縁層６がエツチング阻止層と
なり表面は極めて平坦に仕上る。多結晶シリコン膜５の
エツチング方法は、窒化シリコンと選択性のあるもので
あればどのような方法てもよい。例えは、ウェットエツ
チングならＨＮＯ３（２０）十ＨＦ （１）を用いれば
よく、ドライエツヂンクならＳ Ｆ ｆ、やＣ（：Ｊ’
４を用いれはよい。Next, as shown in FIG.
is removed using an etching technique to expose the insulating layer 0 and form an insulating isolation trench. The insulating layer 6 serves as an etching prevention layer and the surface is finished extremely flat. The polycrystalline silicon film 5 may be etched by any method as long as it is selective to silicon nitride. For example, for wet etching, HNO3 (20) and HF (1) can be used, and for dry etching, use S F f, or C (:J'
It is good to use 4.
なお、多結晶シリコン膜５の堆積厚さは、表面か平坦に
なるよう渦幅の数倍にｊπぶとよい。あるいは、堆積後
にエッチハック法により平坦化してからイオン注入を行
うようにしてもよい。Note that the deposited thickness of the polycrystalline silicon film 5 is preferably several times the vortex width by jπ so that the surface is flat. Alternatively, the ion implantation may be performed after planarization by an etch hack method after deposition.
又、Ｑ ｉの代りに酸素をイオン注入してもよい、すな
わち、投影飛程Ｒｐか１μｍになるように、加速電圧４
２０ｋｅｖで、ドーズ景１×１０１４〜１０ Ｘ １０
１４ｃｍ−３の注入を行なった後、不活性ガス中におい
て温度１０００〜１２００℃て熱処理を行ない、酸化シ
リコン絶縁層６を形成してもよいのである。In addition, oxygen ions may be implanted instead of Qi, that is, the acceleration voltage is set to 4 so that the projected range Rp becomes 1 μm.
At 20kev, dose view 1 x 1014 ~ 10 x 10
After implantation of 14 cm<-3>, heat treatment may be performed at a temperature of 1000 to 1200[deg.] C. in an inert gas to form the silicon oxide insulating layer 6.
以上説明したように本発明は、渦形成後に堆積した多結
晶シリコン膜に窒素又は酸素をイオン注入し、その後に
所定の温度で熱処理を行ない、多結晶シリコン膜内に絶
縁層を形成することにより、その後に絶縁分離領域を平
坦化するために多結晶シリコン膜のエツチングを行なう
とき、絶縁層と多結晶シリコ１ン膜のエツチングの選択
比により絶縁層上部でエツチングか止まり容喝に平坦化
か出来る。このろに絶縁分離領域がフラットになり、段
差被覆性のよい電極配線を形成できるので半導体装置の
高品質化、高歩留化を実現することかできる効果がある
。As explained above, the present invention implants nitrogen or oxygen ions into a polycrystalline silicon film deposited after vortex formation, and then performs heat treatment at a predetermined temperature to form an insulating layer within the polycrystalline silicon film. Then, when etching the polycrystalline silicon film to planarize the isolation region, depending on the etching selectivity between the insulating layer and the polycrystalline silicon film, the etching may stop at the top of the insulating layer or it may not be completely flattened. I can do it. In this way, the insulation isolation region becomes flat and electrode wiring with good step coverage can be formed, which has the effect of realizing high quality and high yield of semiconductor devices.
第１図（ａ）〜（ｄ）は本発明の一実施例を１悦明する
ための工程順に配置した半導木チップの断面図、第２図
（ａ）〜＜ｃ）は従来例を、′ｉ（ａ明するための工程
順に配置した半へ９体チップの断ｍ１［４である。
１１１．［）型半導体基板、２０．・Ｎ型不純物層、３
・・・溝、４・・・絶縁膜、５・・・多結晶シリコン膜
、６・・・絶縁層。FIGS. 1(a) to (d) are cross-sectional views of semiconductor wood chips arranged in the order of steps for carrying out one embodiment of the present invention, and FIGS. , 'i(a) is a section m1 [4] of a half-nine chip arranged in the order of steps to clarify. 111. [) type semiconductor substrate, 20.・N-type impurity layer, 3
... Groove, 4... Insulating film, 5... Polycrystalline silicon film, 6... Insulating layer.
Claims (1)
の溝を形成する工程と、前記溝の表面に絶縁膜を被着し
たのち多結晶シリコン膜を堆積させる工程と、前記多結
晶シリコン膜に窒素又は酸素をイオン注入したのち熱処
理を行ない前記絶縁膜と前記多結晶シリコン膜の界面近
傍に絶縁層を形成する工程と、前記多結晶シリコン膜を
エッチングして前記絶縁層を露出させる工程とにより絶
縁分離溝を形成することを特徴とする半導体装置の製造
方法。a step of forming a groove of a predetermined shape in the thickness direction from one main surface of a semiconductor substrate; a step of depositing a polycrystalline silicon film after depositing an insulating film on the surface of the groove; and a step of depositing a polycrystalline silicon film. a step of ion-implanting nitrogen or oxygen into the substrate and then performing heat treatment to form an insulating layer near the interface between the insulating film and the polycrystalline silicon film; a step of etching the polycrystalline silicon film to expose the insulating layer; 1. A method of manufacturing a semiconductor device, the method comprising: forming an insulating isolation trench.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30091187A JPH01143231A (en) | 1987-11-27 | 1987-11-27 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30091187A JPH01143231A (en) | 1987-11-27 | 1987-11-27 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01143231A true JPH01143231A (en) | 1989-06-05 |
Family
ID=17890611
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30091187A Pending JPH01143231A (en) | 1987-11-27 | 1987-11-27 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01143231A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5354706A (en) * | 1993-03-02 | 1994-10-11 | Lsi Logic Corporation | Formation of uniform dimension conductive lines on a semiconductor wafer |
| FR2774808A1 (en) * | 1998-02-09 | 1999-08-13 | United Microelectronics Corp | DOUBLE-DAMASCAN STRUCTURE AND MANUFACTURING METHOD THEREOF |
| NL1009459C2 (en) * | 1998-06-22 | 1999-12-27 | United Microelectronics Corp | Dual damascene structure for multilevel metallization and interconnect |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60111437A (en) * | 1983-11-22 | 1985-06-17 | Toshiba Corp | Manufacture of semiconductor device |
| JPS61166041A (en) * | 1985-01-17 | 1986-07-26 | Matsushita Electronics Corp | Dielectric isolation method |
-
1987
- 1987-11-27 JP JP30091187A patent/JPH01143231A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60111437A (en) * | 1983-11-22 | 1985-06-17 | Toshiba Corp | Manufacture of semiconductor device |
| JPS61166041A (en) * | 1985-01-17 | 1986-07-26 | Matsushita Electronics Corp | Dielectric isolation method |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5354706A (en) * | 1993-03-02 | 1994-10-11 | Lsi Logic Corporation | Formation of uniform dimension conductive lines on a semiconductor wafer |
| FR2774808A1 (en) * | 1998-02-09 | 1999-08-13 | United Microelectronics Corp | DOUBLE-DAMASCAN STRUCTURE AND MANUFACTURING METHOD THEREOF |
| NL1009459C2 (en) * | 1998-06-22 | 1999-12-27 | United Microelectronics Corp | Dual damascene structure for multilevel metallization and interconnect |
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