JPH04369852A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To enable the upsides of the isolated parts on the same substrate to be lessened in level dispersion by a method wherein the upside of a polycrystalline semiconductor layer buried in a groove is set at a certain level by control in a trench isolation method. CONSTITUTION:A polycrystalline semiconductor layer is formed on the whole surface of a substrate 21 filling a groove 24, an oxide film 22 is formed on the upside through the implantation of oxygen ions and a thermal treatment, and the polycrystalline semiconductor layer is etched back making the oxide film 22 serve as an etching terminal point, whereby the polycrystalline semiconductor layer is left only inside the groove.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor integrated circuit device, and more particularly to a method of manufacturing a trench isolation structure.

0002

2. Description of the Related Art In recent years, the degree of integration of semiconductor integrated circuit devices has rapidly progressed, and various methods have been implemented to increase the degree of miniaturization of elements. Particularly in bipolar semiconductor integrated circuit devices, along with the miniaturization of elements, improvements have also been made to element isolation technology, contributing to higher performance of the devices.

[0003] Recent device isolation techniques include a trench digging process using reactive ion etching technology (hereinafter referred to as RIE technology) that can be etched perpendicularly to the semiconductor substrate surface, and a trench backfilling process using polycrystalline silicon. Trench isolation technology that combines a planarization process has become mainstream, and is positioned as the most advanced technology for miniaturized element isolation.

A general method for manufacturing trench isolation structures will now be described with reference to FIGS. 4-6. First, Figure 4(a)
As shown in FIG. 2, an oxide film 12 with a thickness of about 1000 Å is formed by thermal oxidation on the surface of a semiconductor substrate 11 on which an N-type epitaxial layer is grown to a thickness of about 2 μm on a P-type silicon substrate. Next, an opening 13 is formed in the oxide film 12 using a known photolithographic etching technique, as shown in FIG. 4(b). Next, using the oxide film 12 as a mask, the semiconductor substrate 11 is etched through the opening 13 by RIE technique, and a groove 14 for trench isolation is formed in the substrate 11 as shown in FIG. 4(c).

Next, boron ions are implanted perpendicularly to the surface of the semiconductor substrate 11 under the conditions of an energy of 50 KeV and a dose of 1×10 13 ions/cm 2 , for example, to form the grooves 14 .
A P-type region (not shown) is formed at the bottom of the channel to serve as a channel stopper. After that, the semiconductor substrate 11 is
By oxidizing in a steam atmosphere at 000°C,
As shown in (a), an inner wall oxide film 15 with a thickness of about 2000 Å is grown on the inner wall of the trench 14. Then, as shown in FIG. Next, polycrystalline silicon 16 is produced on the entire surface of the substrate 11 including the grooves 14 by a known method using a low pressure CVD apparatus, as shown in FIG. 5(b). This polycrystalline silicon 16 is produced to a thickness sufficient to fill the groove 14. Subsequently, on the polycrystalline silicon 16,
As shown in (c), a photoresist 17 is applied using a spinner method to planarize the surface.

Thereafter, using a known RIE etching technique, the photoresist 17 and the polycrystalline silicon 16 are etched back at the same speed until the oxide film 12 is exposed, as shown in FIG. 16 is left only in the groove 14. Thereafter, a cap silicon oxide film 18 having a thickness of about 2000 Å is formed on the upper surface of the remaining polycrystalline silicon 16, as shown in FIG. 6(b). Conventional trench isolation is thus completed.

[0007]

However, in the conventional manufacturing method as described above, when the photoresist 17 and the polycrystalline silicon 16 are etched back at the same speed, the etching process is stopped when the oxide film 12 is exposed. Even if
Since the etching rate is high, it is very difficult to control the upper surface of the polycrystalline silicon 16 embedded in the groove 14 to a constant position. Furthermore, variations occur in the top surface position of the polycrystalline silicon 16 within the trench 14 even between multiple isolation portions on the same substrate, which impairs the flatness of the substrate and becomes a major hindrance to higher integration of semiconductor integrated circuit devices. There was a problem.

The present invention has been made in view of the above points, and it is possible to control the top surface of the buried polycrystalline semiconductor layer in the trench at a constant position, and eliminate variations in the top surface position among a plurality of separation parts on the same substrate. An object of the present invention is to provide a method for manufacturing a semiconductor integrated circuit device that can form excellent trench isolation.

[0009]

[Means for Solving the Problems] In the present invention, a groove is dug in the element isolation portion of a semiconductor substrate, a polycrystalline semiconductor layer is formed on the entire surface so as to fill the groove, and then oxygen ion implantation and heat treatment are performed. An oxide film is formed in the polycrystalline semiconductor layer on the upper surface of the trench, and the polycrystalline semiconductor layer is etched back using the oxide film as an etching end point, leaving the polycrystalline semiconductor layer only in the trench.

0010

[Operation] In the present invention, an oxide film is formed on the upper surface of the trench in the polycrystalline semiconductor layer, and this oxide film is used as the etching end point for etching back. The upper surface of the layer) can be controlled to be at a constant position on the upper surface of the groove, and there is no variation in the upper surface position even among a plurality of separation parts on the same substrate.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 1 to 3. First, as shown in FIG. 1(a), an oxide film with a thickness of 1000 to 10000 Å is formed by thermal oxidation on the surface of a semiconductor substrate 21 on which an N-type epitaxial layer is grown to a thickness of about 2 μm on a P-type silicon substrate. 22 is formed. Next, an opening 23 is formed in the oxide film 22 using a known photolithographic etching technique, as shown in FIG. 1(b). Next, using the oxide film 22 as a mask, the semiconductor substrate 21 is etched through the opening 23 by RIE technology,
A groove 24 for trench isolation is formed in the substrate 21 as shown in FIG. 1(c). Here, the etching conditions are as follows:
For example, using a mixed gas of SiCl4 and N2, approximately 0.
13.56MHz with a power density of 5W/cm2
Turn on RF power. As a result, an etching rate of about 1000 Å/min is obtained, and at this rate, when the thickness of the epitaxial layer is about 2 μm, the groove 24 is formed to a depth of about 3 μm. After forming the groove 24, the energy is 50 KeV, for example.
, boron ions were implanted vertically onto the surface of the semiconductor substrate 21 at a dose of 1×1013 ions/cm2.
A P-type region (not shown) is formed at the bottom of the groove 24 to serve as a channel stopper.

Next, by oxidizing the semiconductor substrate 21, as shown in FIG.
An inner wall oxide film 25 with a thickness of 0.000 Å is grown. Thereafter, polycrystalline silicon 26 is formed on the entire surface of the substrate 21 including the grooves 24 by a known method using a low pressure CVD apparatus, as shown in FIG. 2(b). The thickness of this polycrystalline silicon 26 may be sufficient as long as it can sufficiently fill the groove 24. Subsequently, a photoresist 2 is applied on the polycrystalline silicon 26 as shown in FIG. 2(c).
7 was applied using a spinner method to flatten the surface.

Thereafter, the photoresist 27 and the polycrystalline silicon 26 are etched back at the same speed using a known RIE technique. For example, using a mixed gas of SF6 and O2, applying power of about 0.2 W/cm2,
Photoresist 27 and polycrystalline silicon 2 at a rate of Å/min
Etch back 6. In this etch-back, as shown in FIG.
leave. Thereafter, oxygen ions (16O+) are implanted into the polycrystalline silicon 26 by ion implantation technology, as indicated by the arrows in the figure. For example, acceleration energy 150KeV
, at a dose of 1.2×1018 ions/cm2. After implanting the oxygen ions, heat treatment is performed to form the portion of the polycrystalline silicon 26 into which the oxygen ions have been implanted, that is, the top surface of the groove 24 of the polycrystalline silicon 26, as shown in FIG. 3(b). A cap silicon oxide film 28 is formed. Next, polycrystalline silicon 26 is etched back again using a known RIE technique. For example, S
Approximately 0.2W/cm2 using a mixed gas of F6 and O2
The polycrystalline silicon 26 is etched back at a rate of about 3000 Å/min. Then, as shown in FIG. 3(c), the oxide film 22 and the cap silicon oxide film 28
When the polycrystalline silicon 26 is exposed, the etching is terminated, leaving the polycrystalline silicon 26 only in the groove 24. This completes the trench isolation of one embodiment of the present invention.

[0014]

As described in detail above, according to the present invention, oxygen ion implantation and heat treatment are performed to oxidize the top surface of the trench in a polycrystalline semiconductor layer that is formed on the entire surface of the substrate by filling the trench. By forming a film and etching back the polycrystalline semiconductor layer using this oxide film as the etching end point, the top surface of the remaining polycrystalline semiconductor layer (buried polycrystalline semiconductor layer)
The top surface position of the groove can be controlled to be constant, and variations in the top surface position can be eliminated even among a plurality of separation parts on the same substrate. Therefore, in the subsequent manufacturing process, particularly in the wiring process, disconnections in the wiring due to the level difference on the top surface of the trench groove will not occur, and an improvement in the yield of semiconductor integrated circuit devices can be expected. Furthermore, the oxide film can be used as a cap oxide film, eliminating the need to newly generate a cap oxide film.

[Brief explanation of the drawing]

FIG. 1 is a process sectional view showing a part of an embodiment of the present invention.

FIG. 2 is a process sectional view showing a part of an embodiment of the present invention.

FIG. 3 is a process sectional view showing a part of an embodiment of the present invention.

FIG. 4 is a process sectional view showing a part of a conventional manufacturing method.

FIG. 5 is a process sectional view showing a part of a conventional manufacturing method.

FIG. 6 is a process sectional view showing a part of a conventional manufacturing method.

[Explanation of symbols]

21 Semiconductor substrate 24 groove 26 Polycrystalline silicon 28 Cap silicon oxide film

Claims (1)

[Claims] [Claim 1] A groove is dug in an element isolation part of a semiconductor substrate,
After forming a polycrystalline semiconductor layer over the entire surface so as to fill this groove, an oxide film is formed in the polycrystalline semiconductor layer on the upper surface of the groove by oxygen ion implantation and heat treatment, and this oxide film is used as the etching end point to form a polycrystalline semiconductor layer. A method for manufacturing a semiconductor integrated circuit device, characterized by etching back a crystalline semiconductor layer and leaving a polycrystalline semiconductor layer only in the groove.