JPH06314739A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To realize a semiconductor integrated circuit device having a trench isolating structure excellent in evenness by a method wherein an oxidation- resistant film is formed on a second recess on a silicon film, and then the silicon film is thermally oxidized. CONSTITUTION:A P-type silicon semiconductor substrate 101 is oxidized to form an oxide film 102, a resist pattern is formed on the oxide film 102 to serve as a mask, the oxide film 102 is selectively removed through the mask concerned to form openings 103, and grooves 104 are provided to the semiconductor substrate 101 using the oxide film 102 provided with the openings 103 as a mask. Boron ions are implanted into the semiconductor substrate 101 through the oxide film as a mask to form a P-type region which serves as a channel stopper on the base of the groove 104, the P-type region is oxidized to form an inner wall oxide film 105 inside the groove 104, and then a polycrystalline silicon 106 is formed, so that recesses 104a are formed on the surface of the polycrystalline silicon 106 corresponding to the grooves 104. Therefore, a silicon nitride film 107 is formed and anisotropically etched, and the polycrystalline silicon 106 is oxidized at a temperature of 1000 deg.C, whereby the polycrystalline silicon 106 can be flattened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having a trench isolation structure.

[0002]

2. Description of the Related Art In recent years, the integration of semiconductor integrated circuits has rapidly increased, and various methods have been devised to increase the degree of miniaturization of elements. In particular, in the bipolar semiconductor integrated circuit device, along with the miniaturization of the element, the element isolation technique has been improved, which contributes to the high integration of the device.

A recent element isolation technique is a trench digging process using an anisotropic reactive ion etching technique (hereinafter referred to as "RIE technique") capable of etching perpendicularly to a semiconductor substrate surface, and a trench made of polycrystalline silicon. Trench isolation technology that combines a backfilling process is the mainstream.

3A to 3H are manufacturing process diagrams of a semiconductor integrated circuit device having a conventional trench isolation structure.

As shown in FIG. 3A, a P-type silicon semiconductor substrate 301 on which an N-type epitaxial layer (not shown) having a thickness of about 2 μm is grown is oxidized in a steam atmosphere at 1000 ° C. An oxide film 302 having a thickness of 10000Å is formed.

Subsequently, a photoresist is coated on the oxide film 302, exposed and developed to form a resist pattern, and the oxide film 3 is formed using the resist pattern as a mask.
02 is selectively removed by a well-known etching method, and about 1.
An opening 303 having a width of 5 μm is formed (FIG. 3B).

Next, using the oxide film 302 as a mask, R
The groove 304 is formed in the silicon semiconductor substrate 301 by the IE technique.
To form. For example, using a mixed gas of SiCl ₄ and N ₂ , a power density of 0.32 W / cm ² and an RF power of 13.56 M
Performing RIE at Hz etches at a rate of about 1000Å / min. The depth of the groove is about 3 μm when the thickness of the N-type epitaxial layer is about 2 μm (FIG. 3).
(C)).

Next, using the oxide film 302 as a mask, boron ion implantation (energy 50 keV, dose 1 × 1) is performed.
(0 ¹³ ions / cm ² ) is performed to form a P-type region that serves as a channel stopper (not shown) at the bottom of the groove 304.

Next, by oxidizing in a water vapor atmosphere at 1000 ° C., an inner wall oxide film 305 of about 2000 Å is formed inside the groove 304 (FIG. 3D).

Successively, well-known CVD using a low pressure chemical vapor deposition (hereinafter referred to as CVD) apparatus
The polycrystalline silicon 306 is formed by the method. The thickness of the polycrystalline silicon 306 may be such that the groove 304 can be sufficiently filled (FIG. 3E). At this time, a recess 304a corresponding to the groove 304 is formed on the surface of the polycrystalline silicon.

Next, a photoresist 307 is applied by a spinner method of about 1 μm and heated at 100 ° C. for 30 minutes to be flattened (FIG. 3F).

Next, RI using a mixed gas of SF ₆ and O ₂
Photoresist 307 and polycrystalline silicon 3 by E
06 is etched until the oxide film 302 is exposed (FIG. 3G).

Then, thermal oxidation is performed in a water vapor atmosphere at 1000 ° C. to form a silicon oxide film 308 of about 2000 liters (FIG. 3 (h)).

[0014]

In the above manufacturing process,
As described with reference to FIG. 3E, the recess 304a is formed on the polycrystalline silicon 306, and the photoresist is formed thick to flatten the recess (FIG. 3).
After (f)), the photoresist and polycrystalline silicon are etched (FIG. 3 (g)).

However, since it is difficult to etch the photoresist and the polycrystalline silicon at the same rate, for example, when the etching rate of the photoresist is higher than that of the polycrystalline silicon, the portion corresponding to the concave portion is not formed. If it is small, it becomes a convex part. FIG. 3G shows the case of this recess.

Therefore, there is a problem in that wiring is broken due to the recesses or projections, or wiring failure such as electromigration occurs due to thin wiring.

Further, since two kinds of gases are used for etching the photoresist and the polycrystalline silicon, that is, O ₂ which is the etching gas of the photoresist and SF ₆ which is the etching gas of the polycrystalline silicon, foreign matter, For example, a large number of photoresist and SF ₆ reaction products or polycrystalline silicon and O ₂ reaction products are generated, and these foreign substances adhere to the wafer surface, causing a short circuit between wirings.

[0018]

According to the present invention, a step of preparing a semiconductor substrate having a first recess and a silicon film having a second recess corresponding to the first recess are formed on the semiconductor substrate. And a step of forming an oxidation resistant film on the second recess, a step of oxidizing the silicon film to form a silicon oxide film, and a step of removing the silicon oxide film. Is.

Here, the first recess is, for example, a trench separating groove.

[0020]

According to the present invention, after the oxidation resistant film is formed in the second concave portion on the silicon film as described above, the bottom surface of the silicon oxide film formed by this thermal oxidation step is thermally oxidized. It can be flattened. Therefore, by removing this silicon oxide film, the silicon film can be flattened.

[0021]

【Example】

[Embodiment 1] FIGS. 1A to 1K are process sectional views showing a first embodiment of the present invention. As shown in FIG. 1 (a),
A P-type silicon semiconductor substrate 101 on which an N-type epitaxial layer (not shown) having a thickness of about 2 μm is grown is formed at 1000 ° C.
To form an oxide film 102 having a thickness of about 10000Å.

Then, a photoresist is applied on the oxide film 102, exposed and developed to form a resist pattern, and the oxide film 1 is formed using the resist pattern as a mask.
02 is selectively removed by a well-known etching method, and about 1.
An opening 103 having a width of 5 μm is formed (FIG. 1B).

Next, using the oxide film 102 as a mask, R
The groove 104 is formed in the silicon semiconductor substrate 101 by the IE technique.
To form. For example, using a mixed gas of SiCl ₄ and N ₂ , a power density of 0.32 W / cm ² and an RF power of 13.56 M
Performing RIE at Hz etches at a rate of about 1000Å / min. The depth of the groove is about 3 μm when the thickness of the N-type epitaxial layer is about 2 μm (FIG. 1).
(C)).

Next, using the oxide film 102 as a mask, boron ion implantation (energy 50 keV, dose 1 × 1) is performed.
(0 ¹³ ions / cm ² ) is performed to form a P-type region that serves as a channel stopper (not shown) at the bottom of the groove 104.

Next, by oxidizing in a water vapor atmosphere at 1000 ° C., an inner wall oxide film 105 of about 2000 Å is formed inside the groove 104 (FIG. 3D).

Subsequently, a well-known C using a low pressure CVD apparatus is used.
Polycrystalline silicon 106 is formed by the VD method. The thickness of the polycrystalline silicon 106 may be such that the groove 104 can be sufficiently filled (FIG. 1E). At this time, a recess 104a corresponding to the groove 104 is formed on the surface of the polycrystalline silicon.

Next, a silicon nitride film 107 is formed using a low pressure CVD apparatus. At this time, the apparent film thickness of the silicon nitride film 107 is large on the side wall of the recess (FIG. 1F). Then, the RIE technique is used to anisotropically etch the silicon nitride film 107 with CF ₄ gas. At this time, the silicon nitride film remains only in the recess 104a (FIG. 1G).

Next, the polycrystalline silicon 106 is replaced with 1000
Oxidize in a steam atmosphere at ℃. At this time, since the silicon nitride film 107 is an oxidation resistant mask, the oxide film does not grow from the portion covered with the silicon nitride film. However, since the oxidation of the polycrystalline silicon in the peripheral portion of the silicon nitride film proceeds in the lateral direction, some oxide film is formed just below the silicon nitride film. In this case, the oxide film 108 is replaced with the oxide film 1
It is desirable to grow until the interface between 08 and the polycrystalline silicon 106 is almost at the same position as the bottom of the recess 104a (FIG. 1 (h)).

Next, the silicon nitride film 107 is removed using 170 ° C. phosphoric acid. After that, the oxide film 108 is removed using a buffered hydrofluoric acid solution. Here, as shown in FIG. 1I, the exposed surface of the polycrystalline silicon 106 is
The depth of 04a is reduced and the flatness is improved.

Then, by RIE using a mixed gas of CH ₂ F ₂ and SF ₆ (pressure 0.01 Torr, RF power 45 W),
The polycrystalline silicon 106 is etched until the oxide film 102 is exposed (FIG. 1 (j)).

Next, it is oxidized at 1000 ° C. to form a trench polycrystalline silicon oxide film 109 (FIG. 1 (k)).

[Embodiment 2] FIGS. 2A to 2G are process sectional views showing a second embodiment of the present invention. Figure 2
As shown in (a), a P-type silicon semiconductor substrate 201 on which an N-type epitaxial layer (not shown) having a thickness of about 2 μm has been grown is oxidized in a water vapor atmosphere at 1000 ° C. to give about 10
An oxide film 202 having a thickness of 000Å is formed.

Subsequently, a silicon nitride film 203 of about 1500 Å and an upper oxide film 204 of about 10000 Å are sequentially formed by the CVD technique.

Next, a photoresist is applied on the upper oxide film 204, exposed and developed to form a resist pattern, and the resist pattern is used as a mask to form the upper oxide film 204, the silicon nitride film 203 and the lower oxide film 202.
Is selectively removed by a well-known etching method,
An opening 205 having a width of m is formed.

Next, the oxide film 204 and the silicon nitride film 2
03 and the lower oxide film 202 as a mask, a groove 206 is formed in the silicon semiconductor substrate 201 by the RIE technique. For example, using a mixed gas of SiCl ₄ and N ₂ , a power density of 0.32 W / cm ² and an RF power of 13.56 MHz
Then, when RIE is performed, etching is performed at a rate of about 1000Å / min. The depth of the groove is about 3 μm when the thickness of the N-type epitaxial layer is about 2 μm.

Next, using the oxide film 204 as a mask, boron ion implantation (energy 50 keV, dose 1 × 1) is performed.
(0 ¹³ ions / cm ² ) is performed to form a P-type region that serves as a channel stopper (not shown) at the bottom of the groove 206.

Next, by oxidizing in a water vapor atmosphere at 1000 ° C., an inner wall oxide film 207 of about 2000 Å is formed inside the groove 206 (FIG. 2B).

Subsequently, a well-known C using a low pressure CVD apparatus is used.
Polycrystalline silicon 208 is formed by the VD method. The thickness of the polycrystalline silicon 208 may be such that the groove 206 can be sufficiently filled. At this time, a concave portion 206a corresponding to the groove 206 is formed on the surface of the polycrystalline silicon. here,
It is preferable that the film thickness of the upper oxide film 204, the silicon nitride film 203, or the polycrystalline silicon 208 is appropriately adjusted in advance so that the bottom of the recess 206a is substantially on the same surface as the silicon nitride film 203.

Next, a silicon nitride film 209 is formed by using a low pressure CVD apparatus. At this time, the apparent film thickness of the silicon nitride film 209 is large on the side wall of the recess 206a (FIG. 2C). After this, using RIE technology,
The silicon nitride film 209 is anisotropically etched with CF ₄ gas. At this time, the silicon nitride film 209 remains only in the recess 206a (FIG. 2D).

Next, the polycrystalline silicon 208 is replaced with 1000
Oxidation is performed in a water vapor atmosphere at 0 ° C. to form an oxide film 210 (FIG. 2E). In this case, since the silicon nitride film 203 acts as a stopper for oxidation, the oxide film described in the first embodiment is oxidized such that the interface between the oxide film and the polycrystalline silicon is grown almost at the same position as the bottom of the recess. Adjustment of the film thickness becomes unnecessary.

Next, the silicon nitride film 209 is removed using 170 ° C. phosphoric acid. After that, the oxide film 210 is removed using a buffered hydrofluoric acid solution. Here, as shown in FIG. 2F, the exposed surface of the polycrystalline silicon 208 is the recess 2
The depth of 06a is reduced and the flatness is improved.

Next, it is oxidized at 1000 ° C. to form a polycrystalline silicon oxide film 211 on the trench (FIG. 2 (g)).

[0043]

As described in detail above, according to the first embodiment of the present invention, polycrystalline silicon is formed on a trench groove, and the concave portion on the polycrystalline silicon corresponding to this groove is resistant to oxidation. Since the film is filled and thermal oxidation is performed, the bottom surface of the silicon oxide film formed by this thermal oxidation can be flattened. Therefore, the polycrystalline silicon can be planarized by removing the silicon oxide film.

Further, according to the second embodiment of the present invention,
Since the oxidation resistant film is previously formed under the polycrystalline silicon film as a stopper for oxidation, it is not necessary to adjust the film thickness of the silicon oxide film formed by thermal oxidation.

[Brief description of drawings]

FIG. 1 is a process sectional view showing a first embodiment of the present invention.

FIG. 2 is a process sectional view showing a second embodiment of the present invention.

FIG. 3 is a sectional view of a manufacturing process of a conventional semiconductor integrated circuit device having a trench isolation structure.

[Explanation of symbols]

 101 Semiconductor Substrate 102 Oxide Film 103 Opening Section 104 Groove 104a Recess 105 Inner Wall Oxide Film 106 Polycrystalline Silicon 107 Silicon Nitride Film 108 Polycrystalline Silicon Oxide Film 109 Trench Polycrystalline Silicon Oxide Film

Claims (2)

[Claims] 1. A step of preparing a semiconductor substrate having a first concave portion, a step of forming a silicon film having a second concave portion corresponding to the first concave portion on the semiconductor substrate, and the second step. Manufacturing of a semiconductor device, comprising: a step of forming an oxidation resistant film on the recess, a step of oxidizing the silicon film to form a silicon oxide film, and a step of removing the silicon oxide film. Method. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate has an oxidation resistant film formed in a region other than the recess.