JPS6018930A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6018930A JPS6018930A JP12605083A JP12605083A JPS6018930A JP S6018930 A JPS6018930 A JP S6018930A JP 12605083 A JP12605083 A JP 12605083A JP 12605083 A JP12605083 A JP 12605083A JP S6018930 A JPS6018930 A JP S6018930A
- Authority
- JP
- Japan
- Prior art keywords
- shaped groove
- film
- groove
- semiconductor
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は半導体装置の製造法、特にＵ形溝を用いたアイ
ソレーション（禦子間分Ｍ）技術に閃する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a method of manufacturing a semiconductor device, and in particular to an isolation technique using a U-shaped groove (M between grooves).
ＩＣやＬＳＩ等のごとき半導体集積回路装置において半
導体基体の表面に形成された多数の素子の間を電気的に
分離するために、横方向に面積を大きくとらなくてすむ
Ｕ形溝アイソレーション方式が提案されている。In order to electrically isolate a large number of elements formed on the surface of a semiconductor substrate in semiconductor integrated circuit devices such as ICs and LSIs, a U-shaped groove isolation method that does not require a large horizontal area is used. Proposed.
Ｕ形溝アイソレージロンは、第１図を参照し。For U-shaped groove isolation, see Figure 1.
シリコン半導体基体１の一生面を選択的にエッチしてＵ
形の深い溝２を形成この溝の内にシリコン酸化物（Ｓ
ｉ Ｏｔ ）膜３を介して多結晶（ポリ）シリコン層４
を堆積し溝の上部をシリコン酸化膜５で覆ったもので、
溝内面及び上部の酸化膜を利用して電子間分離を行うも
のである。The whole surface of the silicon semiconductor substrate 1 is selectively etched to form U.
Form a deep groove 2 in the shape of silicon oxide (S) in this groove.
iOt ) Polycrystalline (poly) silicon layer 4 via film 3
is deposited and the upper part of the groove is covered with a silicon oxide film 5.
Electron isolation is performed using the inner surface of the trench and the oxide film on the top.
上記Ｕ形溝形成のためのエッチは第２図に示すように基
体１表面形成したＳ ｒ Ｏｔ膜６（−１：たはこれに
シリコン窒化物（Ｓ；ｓＮ＊）膜を重ねる）をマスクと
してドライエッチにより第２図に示すように基体のｎ型
エピタキシャルＳｉ層１ａをつきぬけｐ−型基板（ザブ
ストレート）ｌｂに達する深い溝２を形成するように行
う。次いでチャネルストッパを形成するために不純物Ｂ
（ボロン）をイオン打ち込みしＵ形溝の底部にｐ型層７
を形成する。As shown in FIG. 2, the etching for forming the U-shaped groove is performed by masking the S r Ot film 6 (-1: or a silicon nitride (S; sN*) film overlaid on this) formed on the surface of the substrate 1. As shown in FIG. 2, dry etching is performed to form a deep groove 2 that penetrates the n-type epitaxial Si layer 1a of the substrate and reaches the p-type substrate (substrate) lb. Then impurity B is added to form a channel stopper.
(boron) is ion-implanted into the p-type layer 7 at the bottom of the U-shaped groove.
form.
このあとＵ形溝内面を全面的に酸化してＳ ’ｉ ０．
膜３ａ、３ｂを形成するが、前記ｐ型層７はＵ形溝底面
のＳ ｒ Ｏ！膜３ｂ下のｎ型反転によるチャネル形成
を防止する。After this, the inner surface of the U-shaped groove is completely oxidized to S'i 0.
Films 3a and 3b are formed, and the p-type layer 7 is S r O! on the bottom surface of the U-shaped groove. This prevents channel formation due to n-type inversion under the film 3b.
前記のＢイオン打ち込みは、第２図に示すようにシリコ
ン基体上方よりイオンビーム８を振って多数のＵ形溝２
内面を走査するようにして行うものであるが、その際に
同図に示すようにイオンビームの角度が大きい（たとえ
ば７°以上）場合、Ｕ形溝の側面に対して傾斜してイオ
ン打ち込みがなされるために側面のＳｉｎ、膜３ａを通
してＵ形溝側面のシリコンにＢが導入されてｐ型層９が
形成されると、ｐ−型基板１ｂとｒ＋ＪＪエピタキシャ
ルシリコン層１ａ層面８表面で電流リークを生じる。た
とえばＵ形溝アインレーションに１する島領域に横形ｐ
ｒｌｌ））ランジスタを形成した場合にコレクタ・エミ
ッタ間のリークとなる。The B ion implantation described above is performed by swinging the ion beam 8 from above the silicon substrate to form a large number of U-shaped grooves 2, as shown in FIG.
This is done by scanning the inner surface, but if the angle of the ion beam is large (for example, 7 degrees or more) as shown in the figure, the ion implantation will be performed at an angle to the side surface of the U-shaped groove. When B is introduced into the silicon on the side surface of the U-shaped groove through the sin of the side surface and the film 3a to form the p-type layer 9, current leaks between the p-type substrate 1b and the surface of the r+JJ epitaxial silicon layer 1a layer surface 8. occurs. For example, a horizontal p
rll)) When a transistor is formed, leakage occurs between the collector and emitter.
本発明は上述した問題点を取り除（ためになされたもの
であり、その目的とするところはＵ形溝アインレーショ
ンの形成の際に、溝側面に不純物のイオン打ち込みによ
って生ずるリーク不良をなく丁ことにあるう
〔発明の概要〕
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。The present invention has been made to eliminate the above-mentioned problems, and its purpose is to eliminate leakage defects caused by impurity ion implantation into the groove side surface when forming U-shaped groove ainlation. [Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.
すなわち、シリコン半導体基体の一生面を選択的にエッ
チしてＵ形溝をあけ、このＵ形溝内罠半導体酸化膜を介
して多結晶半導体を堆積することにより半導体基体にア
イソレーション部（分離領域）を形成する半導体装置の
製造法であって、前記Ｕ形溝内面に半導体酸化膜を形成
した後、Ｕ形溝の底面を選択的にエッチして薄く形成し
た底面の半導体酸化膜を通してチャンネルストッパ用ノ
不純物イオン打ち込みを行うことにより、Ｕ形溝側面へ
の不純物の入り込みによるリーク不良を制御するもので
ある。That is, a U-shaped groove is formed by selectively etching the whole surface of a silicon semiconductor substrate, and a polycrystalline semiconductor is deposited through a semiconductor oxide film trapped in this U-shaped groove, thereby forming an isolation region in the semiconductor substrate. ), in which a semiconductor oxide film is formed on the inner surface of the U-shaped groove, and then the bottom surface of the U-shaped groove is selectively etched to pass through the thin semiconductor oxide film on the bottom surface to form a channel stopper. By implanting impurity ions, leakage defects caused by impurities entering the side surfaces of the U-shaped groove can be controlled.
第３図１８１ 、 ｆｂｌ乃至第１０図１ａｌ 、 ｔ
ｂｌハ本発明ノー実施例であって、半導体基体にＵ形溝
アインレーションを形成する場合のプロセスを示す各工
程の断面図である。なお、同図のうち各ｔａｌは基体表
面に熱酸化膜（Ｓｉｎ、）のみをマスクとしてエッチす
る場合、各（ｂｌは基体表面に酸化膜及び窒化膜（Ｓｉ
、Ｎ、）をマスクとしてエッチする場合の各工程断面図
をあうわ丁。Fig. 3 181, fbl to Fig. 10 1al, t
FIG. 1 is a non-embodiment of the present invention, and is a cross-sectional view of each step showing a process for forming a U-shaped groove inlation in a semiconductor substrate. Note that in the same figure, each tal is etched using only a thermal oxide film (Si) on the substrate surface, and each (bl is an oxide film and a nitride film (Si) on the substrate surface).
, N, ) are used as masks for etching.
以下工程順に従って具体的に説明する。A detailed explanation will be given below in accordance with the order of the steps.
（１） 第３図１ａｌ 、 （ｂｌに示すように、Ｓｉ
基体１（ｎ′型エピタキシャルＳｉ層及びｐ−型Ｓｉ基
板を含む）に形成したＳｉｎ、膜６（厚さ１０００又程
度）又はＳｉｎ、の上にＳｉ３Ｎ４膜１０ （２５００
〜３０００んを形成した膜をマスクとして選択エッチを
行い、幅１．５μｍ、深さ３，５μｍ程度のＵ形溝２を
形成する。上記選択エッチは、ＫＯＨ等を用い′る異方
性エッチや、 ’ＣＦ４ ＋Ｏｘ（１５％）のエッチャ
ントを用いた反応性イオンエツチング（す、・アクティ
ブ・イオン・エツチング；略してＲＹＥと称ｆ）を併用
して行う。(1) As shown in Fig. 3 1al, (bl), Si
A Si3N4 film 10 (2500 mm thick) is formed on the Si film 6 (about 1000 mm thick) or the Sin formed on the substrate 1 (including the n' type epitaxial Si layer and the p- type Si substrate).
Selective etching is performed using the film with a thickness of ~3,000 μm as a mask to form a U-shaped groove 2 with a width of about 1.5 μm and a depth of about 3.5 μm. The selective etching mentioned above is anisotropic etching using KOH or the like, or reactive ion etching (abbreviated as RYE) using an etchant of CF4 + Ox (15%). This is done in combination with
（２） ウェット雰囲気で酸化することにより第４図ｔ
ａ＋、、ｔｂｌに示すようにＵ形溝２内面に５００Ａ程
度の厚さの５ｉｎ２膜３を形成する（これまでは２００
八程度であった。）
ｔ；３１ Ｓ ｒ ０２膜のドライエッチを行い、第５
図（ａｌ。(2) By oxidizing in a wet atmosphere, the
As shown in a+, tbl, a 5in2 film 3 with a thickness of about 500A is formed on the inner surface of the U-shaped groove 2 (up to now, a 5in2 film 3 with a thickness of about 200A is
It was about eight. ) t; 31 Dry etching the S r 02 film, and
Figure (al.
ｔｂｌに示すようにＵ形溝底面のＳｉｎ、膜のみを選択
的にたとえば２５０＾エツチすることにより溝底面の５
ｉｎ２膜３ｂは２００〜２５０八程度となる。As shown in FIG.
The in2 film 3b has a thickness of about 200 to 2508.
なお、溝側面の８１０□膜３ａはこの際エッチされるこ
とはない。Note that the 810□ film 3a on the side surface of the groove is not etched at this time.
（４１Ｂ（ボロン）イオン打ち込みを行い、第６図・＋
ａｌ 、ｆｂｌに示すように溝底面の５ｉｎ２膜３ｂを
通してＳｉ層−１にＢを導入する。このとき、イオンビ
ーム８の振れの角度が大きくても溝側面は厚いＳ ｔ
０２ ＠ ３ ａ ＫよってＢは導入されない。(41B (boron) ion implantation was performed, Figure 6. +
As shown in al and fbl, B is introduced into the Si layer-1 through the 5in2 film 3b at the bottom of the groove. At this time, even if the deflection angle of the ion beam 8 is large, the groove side surface is thick S t
02 @ 3 a K therefore B is not introduced.
（５１ウェット雰囲気で酸化２行い第３図１ａｌ 、、
ｌ−１）ｌに示すようにＵ形溝内面のＳｉｎ、、膜１
１を１００ＯＡ程度に厚（する。(51 Oxidation 2 performed in a wet atmosphere Fig. 3 1al)
l-1) Sin, film 1 on the inner surface of the U-shaped groove as shown in l.
1 to a thickness of about 100OA.
（６） この後、低圧ＣＶＤ（気相化学堆積）法により
、第８図に示すようにポリ５ｉ１２を基体表面よりりな
くとも溝の深さに対応する３μｍの卯さに堆積してＵ溝
を埋め込む。(6) After that, as shown in Fig. 8, by low-pressure CVD (vapor phase chemical deposition) method, poly 5i12 is deposited on the substrate surface to a depth of at least 3 μm, which corresponds to the depth of the groove. Embed.
（７）次いでポリ８１層１２０表面に対しＣＦ４十〇ｇ
（１５％）をエッチャントとするプラズマエッチを行い
、第９図ｔａｌ 、 ｔｂｌＫ全面を平坦化する。(7) Next, apply 400 g of CF to the poly 81 layer 120 surface.
Plasma etching is performed using (15%) as an etchant to planarize the entire surface of the tal and tblK in FIG.
（８）低温酸化を行い、第１０図ｔａｌ 、 ｔｂｌに
示すようにＵ形溝におけるボＩＪ Ｓ ｉ層１２の表面
部分に充分に厚いＳｉｎ、膜１３を形成し、Ｕ形溝アイ
ンレーション部を完成させる。この工程でＳｉ、Ｎ、を
用いたケースｔｂｌではＳｉ３Ｎ、膜が耐酸化マスクに
なり、ポリＳｉ層のある部分のみが厚く酸化されるっこ
の後Ｓｉ、Ｎ４膜は熱リン酸等を用いてエッチ除去され
る。(8) Perform low-temperature oxidation to form a sufficiently thick Sin film 13 on the surface of the void IJSi layer 12 in the U-shaped groove, as shown in FIG. Finalize. In the case TBL in which Si, N, and Si are used in this process, the Si3N film serves as an oxidation-resistant mask, and only a certain part of the poly-Si layer is oxidized thickly. Etched away.
この後１図示されないが、上記アイソレージタン部によ
り囲まれたＳｉ層の島領域内に選択拡散により、ｐ型ベ
ースｂｎ＋ａエミッタ等から構成される素子領域を形成
することになる。After this, although not shown in the drawings, an element region consisting of a p-type base bn+a emitter, etc. is formed by selective diffusion in the island region of the Si layer surrounded by the isolator region.
以上実施例によれば、工程（３）でＳｉｎ、のドライエ
ッチを行うことによりＵ形溝底面のＳｉｎ、膜のみ選択
的にエッチされ側面のＳｉｎ、膜はエッチされないた約
、チャネルストッパ形成のためＢイオン打込みを行う場
合に、イオンビームの振れの角度が大きくても％Ｕ形溝
底面にＢは打込まれるが溝側面に５ｉｎ２膜が厚さを保
っているたぬＢが導入されることがなくアイソレージタ
ン溝側面にそってのリークの発生を防止することができ
、欠陥のない半導体装ＩＷを提ｇ４−１”ることかでき
る。According to the above embodiment, by performing the dry etching of the Sin in step (3), only the Sin film on the bottom surface of the U-shaped groove is selectively etched, and the Sin film on the side surface is not etched. Therefore, when performing B ion implantation, even if the angle of deflection of the ion beam is large, B is implanted into the bottom of the U-shaped groove, but Tanu B is introduced on the side of the groove with a 5in2 film that maintains the thickness. It is possible to prevent the occurrence of leakage along the side surface of the isolation tongue groove without causing any defects, and it is possible to provide a defect-free semiconductor device IW.
以上本発明者によってなされた発明ケ実施例にもとづき
具体的に説明したが１本発明は上記実施例に限定される
ものではな（、その要旨を逸脱しない範曲で穐々変史可
能であることはいうまでもない。Although the invention made by the present inventor has been specifically explained based on the embodiments described above, the present invention is not limited to the above embodiments (the present invention can be modified in various ways without departing from the gist of the invention). Needless to say.
本発明はＵ形溝アイツレ−７ヨンを適用した半導体装置
、特に高集積化したメモリに適用して最も有効である、
本発明は上記以外に垂直な溝をあけ？＝Ｓｉ基体側面に
イオン打込みにより不純物を導入したくない場合に同様
に応用することができる。The present invention is most effective when applied to semiconductor devices to which U-shaped grooves are applied, particularly to highly integrated memories. = It can be similarly applied when it is not desired to introduce impurities into the side surface of a Si substrate by ion implantation.
第１図は、Ｕ形溝アインレーションの例を示す半導体装
置の正面断面斜視図である。
第２図は、Ｕ形溝内に不純物イオン打込みを行う場合の
形態な示す断面図である。
第３図１８１ 、 ｌｂｌ乃至第１０図ｔａｌ 、 Ｃ
ｂｌ＋’；ｉ、本発明による実施例であってＵ形溝アイ
ソレーション形成のためのプロ支スを示す工程断面図で
ある。
１・・・シリコン基体、１ａ・・・エピタキシャルｎ型
シリコン層、ｌｂ・・・ｐ−型シリコン基体、２・・・
Ｕ形溝、３・・・シリコン酸化膜、４・・・ポリシリコ
ン層。
５．６・・・シリコン酸化膜、７・・・チャネルストッ
パ（ｐ型層）、８・・・イオンビーム、９・・・ｐｕ層
、ｉｏ・・・ナイトライド膜、１１・・・シリコン酸化
膜、１２・・・ポリシリコン、１３・・・厚いシリコン
酸化膜。−第 １ 図
第 ４ 図
第 ５ 図
第 ６ 図
第 ７ 図
第 ８ 図
≦
第１
（ｏ−２
）図
（４）
Ｏ図FIG. 1 is a front cross-sectional perspective view of a semiconductor device showing an example of U-shaped groove ainlation. FIG. 2 is a sectional view showing a case where impurity ions are implanted into a U-shaped groove. Figure 3 181, lbl to Figure 10 tal, C
bl+';i is an embodiment of the present invention, and is a process cross-sectional view showing a professional support for forming U-shaped groove isolation. DESCRIPTION OF SYMBOLS 1...Silicon base, 1a...Epitaxial n-type silicon layer, lb...P-type silicon base, 2...
U-shaped groove, 3... silicon oxide film, 4... polysilicon layer. 5.6...Silicon oxide film, 7...Channel stopper (p-type layer), 8...Ion beam, 9...PU layer, io...Nitride film, 11...Silicon oxide Film, 12... polysilicon, 13... thick silicon oxide film. -Figure 1 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 ≦ Figure 1 (o-2) Figure (4) Figure O
Claims (1)
てＵ形溝をあけ、このＵ形溝内に半導体酸化膜を介して
多結晶半導体を堆積することにより半導体基体にアイソ
レーション部（分離領域）を形成する半導体装置の製造
法であって、前記Ｕ形溝内面に半導体酸化膜を形成した
後、Ｕ形溝の底面な選択的にエッチして薄く形成した底
面の半導体酸化膜を通してチャンネルストッパ用の不純
物イオン打ち込みを行うことを特徴とする半導体装置の
製造法。 ２、前記Ｕ形溝底面の選択的エッチは半導体酸化膜ドラ
イエッチにより行う特許請求の範囲第１項記載の半導体
装置の製造法。[Claims] 1. A U-shaped groove is formed by selectively etching the entire surface of a silicon semiconductor substrate, and a polycrystalline semiconductor is deposited in the U-shaped groove via a semiconductor oxide film to form a semiconductor substrate. A method of manufacturing a semiconductor device forming an isolation region (separation region), wherein a semiconductor oxide film is formed on the inner surface of the U-shaped groove, and then the bottom surface of the U-shaped groove is selectively etched to form a thin layer. A method for manufacturing a semiconductor device characterized by implanting impurity ions for a channel stopper through a semiconductor oxide film. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the selective etching of the bottom surface of the U-shaped groove is performed by dry etching of a semiconductor oxide film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12605083A JPS6018930A (en) | 1983-07-13 | 1983-07-13 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12605083A JPS6018930A (en) | 1983-07-13 | 1983-07-13 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6018930A true JPS6018930A (en) | 1985-01-31 |
Family
ID=14925404
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12605083A Pending JPS6018930A (en) | 1983-07-13 | 1983-07-13 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6018930A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61268038A (en) * | 1985-05-22 | 1986-11-27 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPH01251736A (en) * | 1988-03-31 | 1989-10-06 | Toshiba Corp | Manufacture of semiconductor device |
| JPH0653315A (en) * | 1992-07-30 | 1994-02-25 | Nec Corp | Semiconductor device and manufacture thereof |
| JPH08139176A (en) * | 1994-11-03 | 1996-05-31 | Lg Semicon Co Ltd | Manufacture of semiconductor device |
-
1983
- 1983-07-13 JP JP12605083A patent/JPS6018930A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61268038A (en) * | 1985-05-22 | 1986-11-27 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPH01251736A (en) * | 1988-03-31 | 1989-10-06 | Toshiba Corp | Manufacture of semiconductor device |
| JPH0653315A (en) * | 1992-07-30 | 1994-02-25 | Nec Corp | Semiconductor device and manufacture thereof |
| JPH08139176A (en) * | 1994-11-03 | 1996-05-31 | Lg Semicon Co Ltd | Manufacture of semiconductor device |
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