KR940005720B1 - Manufacturing method for elements segregation of semiconductor device - Google Patents

Abstract

The method is for isolating N/P-channel device in an integrated circuit (IC). The method comprises the steps of: (a) removing netrogenous layer on a field region; (b) forming a netrogenous thin film and thermal oxide layer sequentially; (c) forming thermal oxide spacer on both sides of the field region; (d) removing the netrogenous thin film, pad oxide layer on field region and etching silicon substrate; (e) removing the thermal oxide layer spacer, forming a damage cure oxide layer and forming a netrogenous spacer; and (f) oxidizing the field region.

Description

Device Separation Manufacturing Method of Semiconductor Device

1A to 1E are sectional views of a process of forming an OSELO-II structure in which a LOCOS device is separated after a shallow trench using a spacer in a field region by a conventional device isolation method.

2A to 2E are cross-sectional views of a device isolation formation process that ameliorates the disadvantages of conventional OSELO-II structures by the method of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a device isolation method capable of improving device isolation characteristics and reducing side diffusion of impurities.

As the integration technology of semiconductor devices has been improved and highly integrated, the electrical separation of N / P-channel devices on the same substrate has become a major problem. As the local localization of silicon (LOCOS) technology is recognized as a bird's beak phenomenon, the limit of device isolation is limited to 1μm, a trench structure that can effectively separate devices with a small area is used. In the trench structure, the oxide film for isolation is very good, but the trench etching of the substrate silicon layer causes crystal defects in the substrate silicon, which increases the leakage current through the defect in the active device operating conditions, thereby degrading the electrical characteristics of the device In addition, the modified LOCOS isolation structure uses a buffer layer that is transformed into any shape, and thus, a buffer under the buffer layer during thermal oxidation of the field region.

As described above, the trench or modified LOCOS device isolation method has many problems. However, the device isolation method having improved isolation characteristics using these methods has been actively studied. For example, the prior art shown in FIG. As an OSELO-II device isolation method described in "IEEE Transistor Electron Device, July 1988, p893", referring to the accompanying drawings, it can be seen that based on the LOCOS device isolation method after a shallow trench.

That is, after the buffer oxide film 11 and the buffer nitride film 12 are sequentially deposited and deposited on the silicon substrate 100, a buffer layer pattern 1P having an open field region is formed (FIG. 1a), and the thin nitride film (thin) The nitride 13 and the high temperature thermal oxide film 14 are sequentially deposited (FIG. 1B).

Subsequently, the entire surface of the high temperature thermal oxide film 14 is etched back by dry etching to form a spacer 14 'on the side of the buffer layer pattern 1P, and the spacer 14' is used as a mask. Etching the unshielded thin film 13 and the substrate silicon 100 in the field region in turn can form a narrow trench 15 of the required depth in the substrate silicon 100 (FIG. 1C). Then, the high temperature thermal oxide spacer 14 'is removed (FIG. 1d), and the trench substrate silicon in the field region is oxidized to form a separation oxide film 16 (FIG. 1E). Using this structure, the sidewall oxidation of the buffer oxide film is prevented by the nitride film placed in the L-shape on the sidewalls of the buffer layer pattern, thereby reducing the Burj beak and having the side diffusion margin of the channel blocking ions by the width of the spacer. To limit the channel blocking ion layer to increase the active area

However, in the OSELO-II technology, when the nitride thin film is etched using the spacer as a mask to form the L-shaped nitride film, the substrate silicon interface in the field region is immediately damaged, and the L-shaped nitride film is formed. There is a problem in that contact with the substrate silicon immediately causes damage and stress in the interface region between the two layers.

Accordingly, the present invention is to provide a method for removing the damage and forcing of silicon during the oxidation process by placing a buffer oxide film between the L-shaped thin nitride film and the substrate silicon of the field region in order to solve the above problems of the prior art. On the other hand, an object of the present invention is to provide a device isolation method capable of increasing vertical oxidation while forming a nitride spacer on a shallow trench sidewall to prevent lateral oxidation during an oxidation process.

In the device isolation fabrication process for achieving the above object of the present invention, a step of removing the buffer nitride film on the field region from the buffer layer on the substrate silicon; Stacking and sequentially depositing a thin nitride film and a high temperature thermal oxide film on the entire surface of the resultant product; And forming a high temperature thermal oxidation spacer on both sides of the field region; Removing the thin nitride film by using the resultant, removing the pad oxide film on the field region, and subsequently trench etching the substrate silicon; Subsequently removing the high temperature thermal oxide spacers, growing a damage cure oxide film of thin films on the inner walls of the trenches, and subsequently forming nitride spacers on the trench sidewalls; And oxidizing the field region.

Hereinafter, the process of the present invention described above with reference to the accompanying drawings, Figure 2 will be described in detail.

First, referring to FIG. 2A, a buffer oxide film 21 and a buffer nitride film 22 are sequentially stacked on an n / p substrate silicon or a substrate silicon 200 in which a well is formed. Then, the buffer nitride film 22 in the field region is removed by a typical photolithography process to expose the buffer oxide film 21.

Subsequently, in FIG. 2B, the nitride nitride film 23 and the high temperature oxide film 24 are sequentially deposited and deposited on the resultant product.

Next, referring to FIG. 2C, when the high temperature oxide film 24 is etched back by anisotropic etching using the nitride film 23 as an end point, sidewalls of the nitride film 23 at both ends of the field region are etched. A spacer 24 'is formed in the wafer, and the dry or wet etching of the nitride film 23 which is not covered by the high temperature oxide film spacer 24' is performed in the active region. The buffer oxide film 21, which is not covered by the spacer, is exposed.

Subsequently, the buffer oxide film 21 in the field region is etched using the spacer 24 ', and then the shallow trench 25 is subsequently anisotropically etched into the substrate silicon 200.

Next, referring to FIG. 2d, the high temperature thermal oxide spacers are removed, and then a thin film of the damage cure oxide layer 26 is grown on the inner wall of the trench 25 to compensate for silicon crystal defects, and then the entire front surface of the resultant. The nitride film spacers 27 can be formed on the trench sidewalls by depositing a nitride film on the substrate and anisotropic etching.

Then, when the field region is oxidized using the result, a separation oxide film 28 is formed, and the shape of device isolation according to the present invention is shown in FIG. 2E.

According to the present invention as described above, the substrate chamber in the problems of the conventional OSELO-II structure

The present invention is not limited to the above embodiments, and it is apparent that numerous modifications can be made by those skilled in the art within the technical idea of the present invention.

Claims (6)

A LOCOS device isolation method of a semiconductor device, comprising: removing a buffer nitride film over a field region from a buffer layer over a substrate silicon; Stacking and sequentially depositing a thin nitride film and a high temperature thermal oxide film on the entire surface of the resultant product; And forming a high temperature thermal oxidation spacer on both sides of the field region; Removing the thin nitride film by using the resultant, removing the pad oxide film on the field region, and subsequently trench etching the substrate silicon; Subsequently removing the high temperature thermal oxide spacers, growing a damage cure oxide film of thin film on the inner wall of the trench, and subsequently forming a nitride spacer on the trench sidewalls; And a step of oxidizing the field region. The method of claim 1, wherein the buffer layer is formed by sequentially depositing a buffer oxide film and a buffer nitride film. The method of manufacturing a semiconductor device according to claim 1, wherein the high temperature thermal oxide film spacer is formed by a front etch back process using an anisotropic etching method with the thin nitride film as an end point. The nitride film of the upper portion of the buffer layer pattern and the field region not covered by the high temperature thermal oxide spacers is subjected to dry or wet removal. The method of claim 1, wherein after the high temperature thermal oxide spacer is removed, a nitride film is deposited on the entire surface of the substrate, and the nitride film spacer is formed on the shallow trench sidewalls by a front etch back process using an anisotropic etching method. The method of claim 5, wherein the high temperature thermal oxide film is removed by a wet etching process.