KR100389911B1 - Trench isolation method - Google Patents
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- KR100389911B1 KR100389911B1 KR1019960039838A KR19960039838A KR100389911B1 KR 100389911 B1 KR100389911 B1 KR 100389911B1 KR 1019960039838 A KR1019960039838 A KR 1019960039838A KR 19960039838 A KR19960039838 A KR 19960039838A KR 100389911 B1 KR100389911 B1 KR 100389911B1
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- 238000002955 isolation Methods 0.000 title claims abstract description 31
- 239000004065 semiconductor Substances 0.000 claims abstract description 31
- 150000004767 nitrides Chemical class 0.000 claims abstract description 29
- 238000000034 method Methods 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 125000006850 spacer group Chemical group 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 13
- 230000003647 oxidation Effects 0.000 claims abstract description 10
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims description 12
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 6
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 5
- 238000005498 polishing Methods 0.000 abstract description 2
- 230000002950 deficient Effects 0.000 description 5
- 230000007547 defect Effects 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000008439 repair process Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
- H01L21/76235—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls trench shape altered by a local oxidation of silicon process step, e.g. trench corner rounding by LOCOS
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
Description
본 발명은 반도체 장치의 소자 분리 방법에 관한 것으로서, 보다 상세하게는 STI(Shallow Trench Isolation) 공정에서 활성 영역과 필드 영역의 경계 부분이 함몰되는 현상을 개선한 트렌치 소자 분리 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device isolation method of a semiconductor device, and more particularly, to a trench device isolation method in which a boundary between an active region and a field region is reduced in a shallow trench isolation (STI) process.
일반적으로, 반도체 장치의 제조에 널리 이용되는 선택적 산화에 의한 소자 분리 방법인 LOCOS(LOCal Oxidation of Silicon) 방법은 측면 산화에 의한 버즈비크(Bird's beak) 현상, 열공정으로 유발되는 버퍼층 응력에 의한 실리콘 기판의 결정 결함 및 채널 저지를 위해 이온 주입된 불순물의 재분포 등의 문제로 반도체 장치의 전기적 특성 향상 및 고집적화 추세에 난점이 되고 있다.In general, the LOCOS (LOCal Oxidation of Silicon) method, which is a method of device isolation by selective oxidation, which is widely used in the manufacture of semiconductor devices, is characterized by a bird's beak phenomenon caused by lateral oxidation and a silicon layer caused by a buffer layer stress caused by thermal processes. Problems such as redistribution of ion implanted impurities for crystal defects and channel blocking of substrates have made it difficult to improve the electrical characteristics and high integration of semiconductor devices.
상기 LOCOS 방법의 문제점을 개선하기 위한 방법의 하나로서 반도체 기판을 식각하여 트렌치를 형성하고, 여기에 절연 물질을 매립하여 소자 분리층을 형성하는 STI 방법이 제안되었으며, 그 기본 구조는 문헌(1994 IEDM, "Characteristics of CMOS Device Isolation for the ULSI Age", pp671-674)에 잘 나타나 있다.As a method for improving the problem of the LOCOS method, an STI method has been proposed, in which a trench is formed by etching a semiconductor substrate and a device isolation layer is formed by embedding an insulating material therein. , "Characteristics of CMOS Device Isolation for the ULSI Age", pp 671-674.
이 STI 방법은 소자 분리막의 형성에 있어서 상기 LOCOS류와 같이 열산화 공정에 의하지 않으므로, 열산화 공정으로 인해 유발되는 상기 LOCOS류의 단점들을 어느 정도 줄일 수 있으며, 기술적으로 STI의 깊이를 조절함으로써 1G DRAM급 이상의 고집적화에 필요한 0.2㎛ 이하의 폭을 갖는 소자 분리층 즉, 트렌치의 형성이 가능하게 되었다.Since the STI method is not based on the thermal oxidation process like the LOCOS in forming the device isolation film, it is possible to reduce the disadvantages of the LOCOS caused by the thermal oxidation process to some extent, and technically by adjusting the depth of the STI. Formation of a device isolation layer, that is, a trench, having a width of 0.2 μm or less, which is required for higher integration than DRAM grade, is possible.
도 1 내지 도 4는 종래 기술에 따른 트렌치 소자 분리 방법을 설명하기 위하여 공정 순서에 따라 도시한 단면도이다.1 to 4 are cross-sectional views according to a process sequence to explain a trench isolation method according to the prior art.
도 1을 참조하면, 반도체 기판(10)상에 얇은 산화막을 형성하고, 그 위에 질화막을 적층한 후, 사진 공정에 의하여 활성 영역과 소자 분리 영역을 한정하는 포토레지스트 패턴(16)을 형성한다. 그 후, 상기 포토레지스트 패턴(16)을 마스크로하여 상기 질화막과 얇은 산화막을 이방성 식각하여 질화막 패턴(14)과 산화막 패턴(12)을 차례로 형성한다. 그 후, 노출된 상기 반도체 기판(10)을 원하는 깊이로 이방성 식각하여 상기 반도체 기판(10) 내에 트렌치 영역(t1)을 형성한다.Referring to FIG. 1, a thin oxide film is formed on a semiconductor substrate 10, a nitride film is laminated thereon, and a photoresist pattern 16 defining an active region and an isolation region is formed by a photolithography process. Thereafter, the nitride film and the thin oxide film are anisotropically etched using the photoresist pattern 16 as a mask to sequentially form the nitride film pattern 14 and the oxide film pattern 12. Thereafter, the exposed semiconductor substrate 10 is anisotropically etched to a desired depth to form a trench region t1 in the semiconductor substrate 10.
도 2를 참조하면, 상기 포토레지스트 패턴(16)을 제거한 후, 상기 반도체 기판(10)의 트렌치 영역(t1)에 열산화에 의해 얇은 산화막(18)을 형성한다. 상기 산화막(18)은 트렌치 영역(t1)을 형성하기 위한 식각시에 받은 손상을 복구시키고, 활성 영역의 에지 부분을 산화막으로 감싸는 효과를 제공한다.Referring to FIG. 2, after the photoresist pattern 16 is removed, a thin oxide film 18 is formed in the trench region t1 of the semiconductor substrate 10 by thermal oxidation. The oxide layer 18 repairs damage received during the etching to form the trench region t1 and provides an effect of wrapping the edge portion of the active region with the oxide layer.
도 3을 참조하면, 상기 결과물 전면에 상기 트렌치 영역(t1)을 채우기에 충분한 두께로 산화막(20)을 증착한다.Referring to FIG. 3, an oxide film 20 is deposited to a thickness sufficient to fill the trench region t1 on the entire surface of the resultant product.
도 4를 참조하면, 상기 산화막을 CMP(Chemical Mechanical Polishing) 공정에 의하여 평탄화한 후에 상기 질화막 패턴(14)을 등방성 식각에 의하여 제거하여, 평탄화된 산화막(20A)을 형성한다. 이 때, 활성 영역과 소자 분리 영역의 경계, 즉 "A"로 표시한 부분이 파여 나가게 된다.Referring to FIG. 4, after the oxide film is planarized by a chemical mechanical polishing (CMP) process, the nitride film pattern 14 is removed by isotropic etching to form a planarized oxide film 20A. At this time, the boundary between the active region and the element isolation region, that is, the portion indicated by "A" is excavated.
도 5는 도 4의 "A" 부분을 확대하여 도시한 도면이다. 도 5에 나타낸 바와 같이, 반도체 기판(10)의 활성 영역과, 소자 분리 영역에 해당하는 펑탄화된 산화막(20A) 사이의 일부 영역이 파여 나가는 결함 부분(30)이 형성되는 현상이 발생한다.FIG. 5 is an enlarged view of a portion “A” of FIG. 4. As shown in FIG. 5, a phenomenon occurs in which a defective portion 30 is formed in which a partial region between the active region of the semiconductor substrate 10 and the punctured oxide film 20A corresponding to the element isolation region is formed.
상기와 같이 반도체 기판의 활성 영역과 소자 분리 영역 사이에서 일부가 파여 나가는 결함 부분이 형성되는 현상은 사진 식각 공정시에 하나의 포토레지스트 패턴을 사용하여 반도체 기판 내에 트렌치 영역을 형성하는 단계까지 진행함으로써야기되는 결과로서, 상기한 바와 같은 종래 기술에 따라 트렌치 소자 분리를 행하는 경우에는 필연적으로 발생되는 것이다. 이는 후 속의 세정 공정 등이 진행됨에 따라 더욱 심화되며, 상기한 바와 같은 결함 부분에 의하여 게이트 산화막의 불량을 초래 하거나, 트렌치 측벽과 인접하는 채널 영역에 국부적으로 강한 전계가 형성되어 낮은 게이트 전압에서도 쉽게 반전(inversion)되어 소오스/드레인 사이에 흐르는 전류를 증가시키게 된다. 따라서, 트랜지스터의 문턱 전압이 낮아지는 역협폭 효과(inverse narrow width effect)가 발생한다.As described above, the phenomenon in which a defective portion is partially formed between the active region and the device isolation region of the semiconductor substrate is formed until the trench region is formed in the semiconductor substrate using a single photoresist pattern during the photolithography process. As a result, it is inevitably generated when trench element isolation is performed according to the conventional technique as described above. This is further deepened as a subsequent cleaning process is performed, and defects as described above may cause defects in the gate oxide film, or locally strong electric fields may be formed in the channel region adjacent to the trench sidewalls, thereby easily at low gate voltages. Inversion will increase the current flowing between the source / drain. Thus, an inverse narrow width effect occurs in which the threshold voltage of the transistor is lowered.
또한, 종래 기술에 의한 트렌치 소자 분리 방법에서는 트렌치 영역 형성시에 마스크로 사용되는 질화막 패턴의 측벽이 완전히 수직으로 형성되어야 한다. 만일, 상기 질화막 패턴의 측벽이 경사지게 형성되면, 상기한 바와 같은 결함 부분이 형성되는 경향이 더욱 커지게 된다.Further, in the trench isolation method according to the prior art, the sidewalls of the nitride film pattern used as a mask when forming the trench region should be completely vertical. If the sidewalls of the nitride film pattern are formed to be inclined, the defect portion as described above is more likely to be formed.
따라서, 본 발명의 목적은 반도체 장치의 활성 영역과 소자 분리 영역 사이에서 일정 부분이 파여 나가서 형성되는 결함 부분을 제거할 수 있는 트렌치 소자 분리 방법을 제공하는 것이다.Accordingly, an object of the present invention is to provide a trench element isolation method capable of removing a defective portion formed by digging a portion between an active region and an element isolation region of a semiconductor device.
도 1 내지 도 4는 종래 기술에 따른 트렌치 소자 분리 방법을 설명하기 위하여 공정 순서에 따라 도시한 단면도이다.1 to 4 are cross-sectional views according to a process sequence to explain a trench isolation method according to the prior art.
도 5는 도 4의 "A" 부분을 확대하여 도시한 도면이다.FIG. 5 is an enlarged view of a portion “A” of FIG. 4.
도 6 내지 도 11은 본 발명의 바람직한 실시예에 따른 트렌치 소자 분리 방법을 설명하기 위하여 공정 순서에 따라 도시한 단면도이다.6 to 11 are cross-sectional views according to a process sequence to explain a trench device isolation method according to a preferred embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
100 : 반도체 기판, 112 : 산화막 패턴100: semiconductor substrate, 112: oxide film pattern
114 : 질화막 패턴, 116 : 포토레지스트 패턴114: nitride film pattern, 116: photoresist pattern
118 : 산화막, 120 : 산화막118: oxide film, 120: oxide film
120A : 매몰 산화막, 130 : 스페이서120A: buried oxide film, 130: spacer
t2 : 트렌치 영역t2: trench area
상기 목적을 달성하기 위하여 본 발명은, 반도체 기판상에 제1 산화막과 질화막을 차례로 적층하는 단계와, 활성 영역과 소자 분리 영역을 한정하는 포토레지스트 패턴을 사용하여 상기 질화막과 제1 산화막을 차례로 패터닝하여 상기 반도체 기판의 소자 분리 영역을 노출시키는 질화막 패턴과 제1 산화막 패턴을 차례로 형성하는 단계와, 상기 포토레지스트 패턴을 마스크로하여 상기 노출된 반도체 기판을 소정의 깊이로 이방성 식각하여 상기 반도체 기판 내에 트렌치 영역을 형성하는 단계와, 상기 트렌치 영역에 열산화에 의해 제2 산화막을 형성하는 단계와, 상기 결과물 전면에 상기 트렌치를 채우기에 충분한 두께로 제3 산화막을 증착하는 단계와, 상기 제3 산화막을 상기 질화막 패턴의 높이까지 제거하여 매몰 산화막을 형성하는 단계와, 상기 질화막 패턴을 제거하는 단계와, 상기 매몰 산화막의 노출된 측벽에 스페이서를 형성하는 단계를 포함하는 것을 특징으로 하는 트렌치 소자 분리 방법을 제공한다.In order to achieve the above object, the present invention provides a method for fabricating a semiconductor device, comprising sequentially stacking a first oxide film and a nitride film on a semiconductor substrate, and sequentially patterning the nitride film and the first oxide film using a photoresist pattern defining an active region and a device isolation region. Sequentially forming a nitride layer pattern and a first oxide layer pattern exposing the device isolation region of the semiconductor substrate, and anisotropically etching the exposed semiconductor substrate to a predetermined depth by using the photoresist pattern as a mask. Forming a trench region, forming a second oxide film by thermal oxidation in the trench region, depositing a third oxide film to a thickness sufficient to fill the trench over the entire surface of the resultant, and forming the third oxide film. Removing to the height of the nitride film pattern to form a buried oxide film, and Removing the hwamak pattern provides a trench isolation method which is characterized in that it comprises a step of forming a spacer on the exposed sidewall of the buried oxide film.
바람직하게는, 상기 매몰 산화막을 형성하는 단계에서 상기 결과물로서 얻어지는 매몰 산화막이 상기 반도체 기판보다 적어도 700Å 높게 되도록 상기 제3 산화막을 제거한다.Preferably, in the forming of the buried oxide film, the third oxide film is removed so that the buried oxide film obtained as the resultant is at least 700 kHz higher than the semiconductor substrate.
또한 바람직하게는, 상기 질화막 패턴을 제거하는 단계는 인산으로 구성되는 식각액을 사용하여 등방성 식각에 의해 제거한다.Also preferably, the removing of the nitride layer pattern may be performed by isotropic etching using an etchant composed of phosphoric acid.
또한 바람직하게는, 상기 스페이서를 형성하는 단계는 상기 질화막 패턴이 제거된 결과물 전면에 제4 산화막을 증착하는 단계와, 상기 제4 산화막을 이방성 식각에 의해 제거하여 상기 매몰 산화막의 노출된 측벽에 스페이서를 형성하는 단계를 포함한다.Also preferably, the forming of the spacer may include depositing a fourth oxide film on the entire surface of the product from which the nitride film pattern is removed, and removing the fourth oxide film by anisotropic etching to remove spacers on the exposed sidewall of the buried oxide film. Forming a step.
다음에, 본 발명의 바람직한 실시예에 대하여 첨부 도면을 참조하여 상세히 설명한다.Next, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.
도 6 내지 도 11은 본 발명의 바람직한 실시예에 따른 트렌치 소자 분리 방법을 설명하기 위하여 공정 순서에 따라 도시한 단면도이다.6 to 11 are cross-sectional views according to a process sequence to explain a trench device isolation method according to a preferred embodiment of the present invention.
도 6을 참조하면, 반도체 기판(100)상에 얇은 산화막을 형성하고, 그 위에 질화막을 적층한 후, 사진 공정에 의하여 활성 영역과 소자 분리 영역을 한정하는 포토레지스트 패턴(116)을 형성한다. 그 후, 상기 포토레지스트 패턴(116)을 마스크로하여 상기 질화막과 얇은 산화막을 이방성 식각하여 질화막 패턴(114)과 산화막 패턴(112)을 차례로 형성한다. 그 후, 노출된 상기 반도체 기판(100)을 원하는 깊이로 이방성 식각하여 상기 반도체 기판(100) 내에 트렌치 영역(t2)을 형성한다.Referring to FIG. 6, a thin oxide film is formed on the semiconductor substrate 100, a nitride film is stacked thereon, and a photoresist pattern 116 defining an active region and an isolation region is formed by a photolithography process. Thereafter, the nitride film and the thin oxide film are anisotropically etched using the photoresist pattern 116 as a mask to sequentially form the nitride film pattern 114 and the oxide film pattern 112. Thereafter, the exposed semiconductor substrate 100 is anisotropically etched to a desired depth to form a trench region t2 in the semiconductor substrate 100.
도 7을 참조하면, 상기 포토레지스트 패턴(116)을 제거한 후, 상기 반도체 기판(100)의 트렌치 영역(t2)에 열산화에 의해 얇은 산화막(118)을 형성한다. 상기 산화막(118)은 트렌치 영역(t2)을 형성하기 위한 식각시에 받은 손상을 복구시키고, 활성 영역의 에지 부분을 산화막으로 감싸는 효과를 제공한다.Referring to FIG. 7, after removing the photoresist pattern 116, a thin oxide film 118 is formed in the trench region t2 of the semiconductor substrate 100 by thermal oxidation. The oxide layer 118 repairs damage received during etching to form the trench region t2 and provides an effect of wrapping the edge portion of the active region with the oxide layer.
도 8을 참조하면, 상기 결과물 전면에 상기 트렌치 영역(t2)을 채우기에 충분한 두께로 산화막(120)을 증착한다.Referring to FIG. 8, an oxide film 120 is deposited to a thickness sufficient to fill the trench region t2 on the entire surface of the resultant product.
도 9를 참조하면, CMP 공정에 의해 상기 질화막 패턴(114)의 높이까지 상기 산화막(120)을 제거하여 매몰 산화막(120A)을 형성한다. 이 때, 결과물상에 남아 있는 매몰 산화막(120A)은 상기 반도체 기판(100)보다 적어도 700Å 이상 더 높은 것이 바람직하다.9, the oxide film 120 is removed to the height of the nitride film pattern 114 by a CMP process to form a buried oxide film 120A. At this time, it is preferable that the buried oxide film 120A remaining on the resultant is at least 700 kV or more higher than that of the semiconductor substrate 100.
도 10을 참조하면, 예를 들면 인산으로 구성되는 식각액을 사용하여 상기 질화막 패턴(114)을 등방성 식각한다.Referring to FIG. 10, the nitride film pattern 114 is isotropically etched using, for example, an etching solution composed of phosphoric acid.
도 11을 참조하면, 상기 결과물상에 스페이서 형성용 산화막을 증착한 후,이방성 식각에 의해 상기 매몰 산화막(120A)중 외부로 노출된 측벽에 스페이서(130)를 형성한다.Referring to FIG. 11, a spacer 130 is formed on a sidewall of the buried oxide film 120A exposed to the outside by anisotropic etching after depositing an oxide film for forming a spacer on the resultant.
상기한 바와 같은 본 발명의 바람직한 실시예에 따른 방법에 의해 트렌치 소자 분리를 행하는 경우에는, 반도체 기판의 활성 영역과 소자 분리 영역 사이에서 일부가 파여 나가는 결함 부분이 형성되더라도, 소자 분리 영역의 매몰 산화막의 측벽을 산화물로 이루어지는 스페이서에 의해 감싸게 되므로, 게이트 산화막의 불량을 초래 하거나, 역협폭 효과가 발생하는 것을 방지할 수 있다.When trench element isolation is performed by the method according to a preferred embodiment of the present invention as described above, even if a defective portion in which part of the trench is formed between the active region and the element isolation region of the semiconductor substrate is formed, the buried oxide film of the element isolation region is formed. Since the sidewalls of the semiconductor film are covered by the spacer made of oxide, it is possible to prevent the gate oxide film from being defective or to generate an inverse narrow effect.
또한, 질화막을 이방성 식각하여 질화막 패턴을 형성할 때 질화막 패턴의 측벽이 경사지도록 형성되는 경우에도, 후속 공정에서 매몰 산화막의 측멱에 형성되는 스페이서에 의해 상기 경사 부분이 커버될 수 있으므로, 질화막 패턴의 측벽을 반드시 수직으로 형성할 필요가 없다.In addition, even when the nitride film is anisotropically etched to form the nitride film pattern, the inclined portion may be covered by a spacer formed on the side of the buried oxide film in a subsequent process, so that the inclined portion may be covered by the spacer layer formed on the side of the buried oxide film. It is not necessary to form the side walls vertically.
이상, 본 발명을 바람직한 실시예를 들어 상세하게 설명하였으나, 본 발명은 상기 실시예에 한정되지 않고, 본 발명의 기술적 사상의 범위 내에서 당 분야에서 통상의 지식을 가진 자에 의하여 여러가지 변형이 가능하다.The present invention has been described in detail with reference to preferred embodiments, but the present invention is not limited to the above embodiments, and various modifications can be made by those skilled in the art within the scope of the technical idea of the present invention. Do.
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| KR940004779A (en) * | 1992-08-31 | 1994-03-16 | 김주용 | Device isolation region formation method of semiconductor device using trench technology |
| US5387540A (en) * | 1993-09-30 | 1995-02-07 | Motorola Inc. | Method of forming trench isolation structure in an integrated circuit |
| KR970053422A (en) * | 1995-12-23 | 1997-07-31 | 김주용 | Device Separating Method of Semiconductor Device |
| KR980006083A (en) * | 1996-06-29 | 1998-03-30 | 김주용 | Method for forming an element isolation film of a semiconductor element |
| KR980006061A (en) * | 1996-06-27 | 1998-03-30 | 김주용 | Method for fabricating device isolation film of semiconductor device |
| KR100204023B1 (en) * | 1996-06-27 | 1999-06-15 | 김영환 | Method for forming an element isolation region in a semiconductor device |
| KR100361761B1 (en) * | 1995-06-02 | 2003-02-05 | 주식회사 하이닉스반도체 | Method for forming isolating layer of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR940004779A (en) * | 1992-08-31 | 1994-03-16 | 김주용 | Device isolation region formation method of semiconductor device using trench technology |
| US5387540A (en) * | 1993-09-30 | 1995-02-07 | Motorola Inc. | Method of forming trench isolation structure in an integrated circuit |
| KR100361761B1 (en) * | 1995-06-02 | 2003-02-05 | 주식회사 하이닉스반도체 | Method for forming isolating layer of semiconductor device |
| KR970053422A (en) * | 1995-12-23 | 1997-07-31 | 김주용 | Device Separating Method of Semiconductor Device |
| KR980006061A (en) * | 1996-06-27 | 1998-03-30 | 김주용 | Method for fabricating device isolation film of semiconductor device |
| KR100204023B1 (en) * | 1996-06-27 | 1999-06-15 | 김영환 | Method for forming an element isolation region in a semiconductor device |
| KR980006083A (en) * | 1996-06-29 | 1998-03-30 | 김주용 | Method for forming an element isolation film of a semiconductor element |
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