KR100271802B1 - A mothod of isolation in semicondcutor device - Google Patents
A mothod of isolation in semicondcutor device Download PDFInfo
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- KR100271802B1 KR100271802B1 KR1019980020202A KR19980020202A KR100271802B1 KR 100271802 B1 KR100271802 B1 KR 100271802B1 KR 1019980020202 A KR1019980020202 A KR 1019980020202A KR 19980020202 A KR19980020202 A KR 19980020202A KR 100271802 B1 KR100271802 B1 KR 100271802B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/3115—Doping the insulating layers
- H01L21/31155—Doping the insulating layers by ion implantation
Abstract
본 발명은 반도체장치의 소자격리방법에 관한 것으로서, 특히, 소자격리용 트렌치 형성후 트렌치에 절연물질을 매립한 다음 질소 이온주입 또는 질소분위기에서의 열처리를 실시하여 절연물질의 식각률(etch rate)을 감소시키도록한 반도체장치의 트렌치 소자격리방법을 제공한다. 본 발명은 반도체기판 상에 버퍼층과 마스크층을 차례로 형성하고 반도체기판의 소정 부분이 노출되도록 패터닝하여 소자격리영역과 활성영역을 한정하는 공정과, 반도체기판의 노출된 부분에 소정 깊이의 트렌치를 형성하는 공정과, 트렌치를 채우는 절연물질층을 형성하는 공정과, 버퍼층의 표면이 노출되도록 절연물질층과 마스크층에 평탄화공정을 실시하는 단계와, 잔류한 절연물질층과 잔류한 버퍼층에 질소처리를 실시하는 단계를 포함하여 이루어진다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device isolation method for a semiconductor device. In particular, after forming a trench for device isolation, an insulating material is embedded in a trench and then etch rate of the insulating material is performed by injecting nitrogen ion or heat treatment in a nitrogen atmosphere. A method for isolating trench elements in a semiconductor device is provided. According to the present invention, a buffer layer and a mask layer are sequentially formed on a semiconductor substrate and patterned to expose a predetermined portion of the semiconductor substrate to define an isolation region and an active region, and a trench having a predetermined depth is formed in the exposed portion of the semiconductor substrate. A step of forming an insulating material layer filling the trench, a planarization step of the insulating material layer and the mask layer so that the surface of the buffer layer is exposed, and nitrogen treatment of the remaining insulating material layer and the remaining buffer layer. It includes the step of performing.
Description
본 발명은 반도체장치의 소자격리방법에 관한 것으로서, 특히, 소자격리용 트렌치 형성후 트렌치에 절연물질을 매립한 다음 질소 이온주입 또는 질소분위기에서의 열처리를 실시하여 절연물질의 식각률(etch rate)을 감소시키도록한 반도체장치의 트렌치 소자격리방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device isolation method for a semiconductor device. In particular, after forming a trench for device isolation, an insulating material is embedded in a trench and then etch rate of the insulating material is performed by injecting nitrogen ion or heat treatment in a nitrogen atmosphere. A method for isolating trench elements in a semiconductor device to reduce the number of semiconductor devices.
반도체장치의 집적화가 거듭되면서 반도체장치의 상당한 면적을 점유하는 소자격리영역을 줄이기 위한 기술 개발이 활발히 진행되고 있다.As the integration of semiconductor devices continues, technology development for reducing the device isolation region occupying a considerable area of the semiconductor device is actively progressing.
일반적으로 반도체장치는 LOCOS(Local Oxidation of Silicon) 방법으로 소자를 격리하였다. LOCOS 방법은 활성영역을 한정하는 산화마스크인 질화막과 반도체기판의 열적 특성이 다르기 때문에 발생하는 스트레스를 해소하기 위하여 질화막과 반도체기판 사이에 박막의 버퍼산화막(buffer oxide)을 형성하고 산화시켜 소자격리영역으로 이용되는 필드산화막를 형성한다. 상기에서 필드산화막은 반도체기판의 수직 방향으로 성장할 뿐만 아니라 산화체(Oxidant : 02)가 버퍼산화막을 따라 수평 방향으로도 확산되므로 질화막의 패턴 엣지(edage)밑으로 성장되게 되는 특징을 갖는다.In general, semiconductor devices have isolated devices by a local oxide of silicon (LOCOS) method. In the LOCOS method, a thin film buffer oxide is formed between the nitride film and the semiconductor substrate and oxidized to eliminate stress caused by the thermal characteristics of the nitride film and the semiconductor substrate, which are the oxide masks that define the active region. A field oxide film to be used is formed. The field oxide film is grown not only in the vertical direction of the semiconductor substrate but also in the oxidant (Oxidant: 0 2 ) in the horizontal direction along the buffer oxide film, so that it is grown under the pattern edge of the nitride film.
이와같이 필드산화막이 활성 영역을 잠식하는 현상을 그 형상이 새의 부리 모양과 유사하여 버즈 비크(Bird's Beak)이라 한다. 이러한 버드 비크의 길이는 필드산화막 두께의 1/2이나 된다. 그러므로, 활성 영역의 크기가 감소되는 것을 줄이기 위하여는 버즈 비크의 길이를 최소화 하여야 한다.The phenomenon in which the field oxide film encroaches on the active region is called Bird's Beak because its shape is similar to that of a bird's beak. This bird beak is half the thickness of the field oxide film. Therefore, the length of the buzz bek should be minimized to reduce the size of the active area.
버즈 비크의 길이를 줄이기 위한 방법으로 필드산화막의 두께를 감소시키는 방식이 도입되었으나 16M DRAM급 이상에서 필드산화막의 두께를 감소시키면 배선과 반도체기판 사이의 정전 용량이 증가되어 신호전달 속도가 저하되는 문제가 발생된다. 또한, 소자의 게이트로 사용되는 배선에 의해 소자 사이의 격리영역에 형성되는 기생 트랜지스터의 문턱전압(Vt)이 저하되어 소자 사이의 격리특성이 저하되는 문제점이 있다.In order to reduce the length of the buzz beak, a method of reducing the thickness of the field oxide film was introduced. However, when the thickness of the field oxide film is reduced in the 16M DRAM class or higher, the capacitance between the wiring and the semiconductor substrate increases and the signal transmission speed decreases. Is generated. In addition, there is a problem that the threshold voltage Vt of the parasitic transistor formed in the isolation region between the elements is lowered by the wiring used as the gate of the element, thereby lowering the isolation characteristic between the elements.
따라서, 버즈 비크의 길이를 감소시키면서 소자격리를 하는 방법이 개발되었다. 버즈 비크의 길이를 감소시키면서 소자격리를 하는 방법으로는 스트레스 완충용 버퍼산화막의 두께를 낮추고 반도체기판과 질화막 사이에 다결정실리콘층을 개입시킨 PBLOCOS(Poly Si Buffered LOCOS), 버퍼산화막의 측벽을 질화막으로 보호하는 SILO(Sealed Interface LOCOS), 그리고, 반도체기판 내에 필드산화막을 형성시키는 리세스(Recessed) LOCOS 기술들이 있다.Thus, a method for device isolation while reducing the length of the buzz bee has been developed. As a method of isolation of the device while reducing the length of the buzz beak, the thickness of the stress buffer buffer oxide film is reduced, and the polysilicon buffer layer (PBLOCOS) and the sidewall of the buffer oxide film are interposed between the semiconductor substrate and the nitride film. There are shielded interface LOCOS (SILO) to protect, and recessed LOCOS techniques to form a field oxide film in a semiconductor substrate.
그러나, 상기 기술들은 격리 영역 표면의 평탄도와 정밀한 디자인 룰(Design Rule) 등의 이유로 256M DRAM급 이상의 집적도를 갖는 차세대 소자의 소자격리기술로 적합하지 않게 되었다.However, the above techniques are not suitable for device isolation technology of next-generation devices having an integration level of 256M DRAM or more due to the flatness of the isolation region surface and the precise design rule.
기존의 여러 소자격리기술들의 문제점을 극복할 수 있는 BOX(buried oxide)형 얕은트렌치소자격리(shallow trench isolation) 기술이 개발되었다. BOX형 소자격리기술은 반도체기판에 트렌치를 형성하고 화학기상증착(Chemical Vapor Deposition : 이하, CVD라 칭함) 방법으로 산화실리콘 또는 불순물이 도핑되지 않은 다결정실리콘을 매립한 구조를 갖는다. 그러므로, 버즈 비크가 발생되지 않아 활성영역의 손실이 전혀 없으며, 또한, 산화막을 메립하고 에치 백(etch back)하여 평탄한 표면을 얻을 수 있다.BOX (buried oxide) type shallow trench isolation technology has been developed to overcome the problems of the existing device isolation techniques. The BOX type device isolation technology has a structure in which a trench is formed in a semiconductor substrate and a silicon oxide or a doped polycrystalline silicon is buried by chemical vapor deposition (hereinafter, referred to as CVD). Therefore, no buzz beaking occurs, there is no loss of the active region, and a flat surface can be obtained by embedding and etching back the oxide film.
따라서, 현재 사용중인 일부 반도체 제품들과 향후 제조되는 가의 모든 차세대 반도체 제품들은 각소자간의 절연을 위하여 트렌치 격리방법을 사용하고 잇다. 그러나 이러한 트렌치에 매립된 절연물질들이 다수의 세정과정과 식각공정으로 과도식각되어 표면단차 발생, 졍션 누설전류의 증가, 트랜지스터의 내로우위쓰 이펙트(narrow width effect)의 증가, 트랜지스터의 써브문턱 헙프(subthreshold hump) 생성 게이트산화막의 신뢰성 저하 등의 문제가 반도체에 치명적인 악영향을 초래한다.Therefore, some semiconductor products currently in use and all future next-generation semiconductor products that are manufactured in the future use trench isolation to insulate each device. However, the insulating materials embedded in these trenches are excessively etched through a number of cleaning and etching processes, resulting in surface stepping, increased leakage leakage current, increased transistor's narrow width effect, and transistor's subthreshold pump. Subthreshold humps) Problems such as deterioration in the reliability of the gate oxide film cause a fatal adverse effect on the semiconductor.
도 1a 내지 도 1d는 종래 기술에 따른 얕은 트렌치를 이용한 소자격리방법을 도시하는 공정도이다.1A to 1D are process diagrams illustrating a device isolation method using a shallow trench according to the prior art.
도 1a를 참조하면, 반도체기판(11) 상에 열산화 방법으로 버퍼산화막(13)을 형성하고, 이 버퍼산화막(13) 상에 화학기상증착(Chemical Vapor Deposition : 이하, CVD라 칭함) 방법으로 질화실리콘을 증착하여 마스크층(15)을 형성한다.Referring to FIG. 1A, a buffer oxide film 13 is formed on a semiconductor substrate 11 by a thermal oxidation method, and chemical vapor deposition (hereinafter referred to as CVD) is performed on the buffer oxide film 13. Silicon nitride is deposited to form a mask layer 15.
그리고, 마스크층(15) 및 버퍼산화막(13)을 포토리쏘그래피 방법으로 반도체기판(11)이 노출되도록 순차적으로 패터닝하여 소자격리영역과 활성영역을 한정한다.The mask layer 15 and the buffer oxide film 13 are sequentially patterned to expose the semiconductor substrate 11 by a photolithography method to define the device isolation region and the active region.
도 1b를 참조하면, 마스크층(15)을 마스크로 사용하여 반도체기판(11)의 노출된 소자격리영역을 소정 깊이로 식각하여 트렌치(17)를 형성한다. 상기에서 트렌치(17)를 반응성이온식각(Reactive Ion Etching : 이하, RIE라 칭함)이나 플라즈마 식각 등으로 이방성 식각하여 형성한다.Referring to FIG. 1B, the trench 17 is formed by etching the exposed device isolation region of the semiconductor substrate 11 to a predetermined depth using the mask layer 15 as a mask. The trench 17 is formed by anisotropic etching by reactive ion etching (hereinafter referred to as RIE) or plasma etching.
도 1c를 참조하면, 마스크층(15) 상에 산화실리콘을 트렌치(17)를 채우도록 CVD 방법으로 증착한다. 그리고, 산화실리콘을 마스크층(15)이 노출되어 화학-기계적연마(Chemical-Mechanical Polishing : 이하, CMP라 칭함) 방법 또는 RIE 방법으로 에치 백하여 트렌치(17) 내에만 잔류되도록 한다. 이 때, 트렌치(17) 내에 잔류하는 산화실리콘은 소자를 분리하는 필드산화막(19)이 된다.Referring to FIG. 1C, silicon oxide is deposited on the mask layer 15 by CVD to fill the trench 17. Then, the silicon oxide is exposed to the mask layer 15 to be etched back by chemical-mechanical polishing (hereinafter referred to as CMP) method or RIE method so as to remain only in the trench 17. At this time, the silicon oxide remaining in the trench 17 becomes a field oxide film 19 separating the elements.
도 1d를 참조하면, 마스크층(15) 및 버퍼산화막(13)을 습식 식각 방법으로 순차적으로 제거하여 반도체기판(11)의 활성영역을 노출시킨다. 이 때, 필드산화막(19)의 반도체기판(11)의 표면 보다 높은 부분도 식각되어 단차가 감소된다.Referring to FIG. 1D, the mask layer 15 and the buffer oxide film 13 are sequentially removed by a wet etching method to expose the active region of the semiconductor substrate 11. At this time, a portion higher than the surface of the semiconductor substrate 11 of the field oxide film 19 is also etched to reduce the level difference.
상술한 종래의 반도체장치의 소자격리방법은 마스크층 및 버퍼산화막을 습식 식각하여 제거하면서 필드산화막의 반도체기판 표면 보다 높은 부분도 식각할 때 이 필드산화막은 습식 식각에 의해 트렌치와 접합 부분의 상부에 홈이 형성되거나, 과도식각되어 실리콘기판 표면과 단차가 심해지게 된다.The device isolation method of the conventional semiconductor device described above uses a wet etching process to remove the mask layer and the buffer oxide film while etching the portion higher than the surface of the semiconductor substrate of the field oxide film, and the field oxide film is formed on the upper portion of the trench and the junction by wet etching. Grooves may be formed or overetched to increase the level of the silicon substrate.
이 후에 게이트산화막과 다결정실리콘으로 게이트를 형성할 때 홈이 형성된 부분에서 게이트산화막의 두께가 감소되고 이 홈의 내부에 다결정실리콘이 잔류하게 되므로 게이트가 활성영역을 에워싸는 구조가 된다. 그러므로, 소자 구동시 홈의 내부에 잔류하는 다결정실리콘에 의해 전계가 증가되어 누설 전류가 흐르며, 또한, 게이트산화막의 두께가 감소에 의해 전계가 집중되어 소자 특성을 저하시키는 문제점이 있다.Subsequently, when the gate is formed of the gate oxide film and the polysilicon, the thickness of the gate oxide film is reduced in the grooved portion, and the polysilicon remains in the groove so that the gate surrounds the active region. Therefore, there is a problem that the electric field is increased due to the polycrystalline silicon remaining inside the groove during device driving, and the leakage current flows, and the electric field is concentrated by decreasing the thickness of the gate oxide film, thereby degrading device characteristics.
즉 세정과정과 식각공정으로 트렌치 매립용 절연물질이 과도식각되어 후속공정에서의 평탄화 불량, 졍션 누설전류의 증가, 상부 모서리에서의 필드 크라우딩 효과(field crowding effect), 붕소의 세그리게이션(segregation)에 의한 내로우 위쓰 효과의 증가, 서브문턱 험프의 생성 그리고 게이트산화막의 신뢰성 저하 등의 반도체 소자에 치명적인 불량을 발생시키는 문제점이 있다.In other words, the cleaning process and the etching process overetch the insulating material for filling the trench. ), There is a problem of causing a fatal defect in the semiconductor device, such as an increase in the narrow whistle effect, the generation of a sub-threshold hump, and a decrease in the reliability of the gate oxide film.
따라서, 본 발명의 목적은 식각시 식각률을 감소시키므로서 과도식각을 방지하여 트렌치 매립물질 상부와 기판 표면사이의 단차발생을 억제하므로서 소자의 신뢰성을 향상시킬 수 있는 반도체장치의 소자격리방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a device isolation method of a semiconductor device which can improve the reliability of the device by reducing the etching rate during etching to prevent excessive etching to prevent the occurrence of the step between the trench buried material and the substrate surface. have.
상기 목적을 달성하기 위해 본 발명에 따른 반도체장치의 소자격리방법은 반도체기판 상에 버퍼층과 마스크층을 차례로 형성하고 반도체기판의 소정 부분이 노출되도록 패터닝하여 소자격리영역과 활성영역을 한정하는 공정과, 반도체기판의 노출된 부분에 소정 깊이의 트렌치를 형성하는 공정과, 트렌치를 채우는 절연물질층을 형성하는 공정과, 버퍼층의 표면이 노출되도록 절연물질층과 마스크층에 평탄화공정을 실시하는 단계와, 잔류한 절연물질층과 잔류한 버퍼층에 질소처리를 실시하는 단계를 포함하여 이루어진다.In order to achieve the above object, a device isolation method of a semiconductor device according to the present invention includes forming a buffer layer and a mask layer on a semiconductor substrate, and patterning the semiconductor substrate to expose a predetermined portion of the semiconductor substrate, thereby defining a device isolation region and an active region. Forming a trench having a predetermined depth in the exposed portion of the semiconductor substrate, forming an insulating material layer filling the trench, and planarizing the insulating material layer and the mask layer to expose the surface of the buffer layer; And, subjecting the remaining insulating material layer and the remaining buffer layer to nitrogen treatment.
도 1a 내지 도 1d는 종래 기술에 따른 반도체장치의 소자격리방법을 도시하는 공정단면도1A to 1D are process cross-sectional views showing a device isolation method of a semiconductor device according to the prior art.
도 2a 내지 도 2b는 본 발명에 따른 반도체장치의 소자격리방법을 도시하는 공정도2A to 2B are process diagrams showing a device isolation method for a semiconductor device according to the present invention.
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2b는 본 발명에 따른 반도체장치의 소자격리방법을 도시하는 공정단면도이다.2A to 2B are process cross-sectional views showing a device isolation method of a semiconductor device according to the present invention.
도 2a를 참조하면, 반도체기판(21) 상에 열산화 방법으로 버퍼산화막(22)을 형성하고, 이 버퍼산화막(22) 상에 CVD 방법으로 질화실리콘을 증착하여 마스크층(23)을 형성한다. 질화막과 반도체기판의 열적 특성이 다르기 때문에 발생하는 스트레스를 해소하기 위하여 질화막과 반도체기판 사이에 박막의 버퍼산화막(buffer oxide, 22)을 형성한다.Referring to FIG. 2A, a buffer oxide film 22 is formed on a semiconductor substrate 21 by a thermal oxidation method, and silicon nitride is deposited on the buffer oxide film 22 by a CVD method to form a mask layer 23. . Since the thermal properties of the nitride film and the semiconductor substrate are different, a thin buffer oxide layer 22 is formed between the nitride film and the semiconductor substrate in order to relieve stress.
그리고, 마스크층(23) 및 버퍼산화막(22)을 포토리쏘그래피 방법으로 소정 부위의 반도체기판(21) 표면이 노출되도록 순차적으로 패터닝하여 소자격리영역과 활성영역을 한정한다.The mask layer 23 and the buffer oxide film 22 are sequentially patterned so as to expose the surface of the semiconductor substrate 21 at a predetermined portion by a photolithography method to define the device isolation region and the active region.
그리고, 마스크층(23)을 마스크로 사용하여 반도체기판(21)의 노출된 부분, 즉, 소자격리영역을 소정 깊이로 식각하여 트렌치를 형성한다. 상기에서 트렌치는 RIE 또는 플라즈마 식각 등으로 노출된 기판(21)을 이방성 식각하여 형성한다.A trench is formed by etching the exposed portion of the semiconductor substrate 21, that is, the device isolation region, to a predetermined depth using the mask layer 23 as a mask. The trench is formed by anisotropically etching the substrate 21 exposed by RIE or plasma etching.
도 2b를 참조하면, 마스크층(23) 상에 산화실리콘층(24)을 트렌치를 매립하도록 CVD 방법으로 증착한다. 그리고, 산화실리콘층(24)을 버퍼산화막층(22)이 노출되도록 CMP 방법 또는 RIE 방법으로 에치 백하여 트렌치내에만 잔류되도록 한다. 이 때, 트렌치 내에 잔류하는 산화실리콘은 소자를 분리하는 필드산화막(24)이 된다.Referring to FIG. 2B, a silicon oxide layer 24 is deposited on the mask layer 23 by CVD to fill the trench. The silicon oxide layer 24 is etched back by the CMP method or the RIE method so that the buffer oxide layer 22 is exposed so as to remain only in the trench. At this time, the silicon oxide remaining in the trench becomes a field oxide film 24 separating the elements.
그다음, 기판(21)의 전면에 질소 이온주입을 실시하거나 질소 분위기에서 열처리를 실시하여 잔류한 산화실리콘층(24)의 식각률을 감소시키므로서 과도식각을 방지한다.Thereafter, nitrogen ion implantation is performed on the entire surface of the substrate 21 or heat treatment is performed in a nitrogen atmosphere to reduce the etching rate of the remaining silicon oxide layer 24, thereby preventing excessive etching.
이후 n 웰과 p 웰을 형성하고 트랜지스터 등을 형성하여 반도체 소자를 완성한다.After that, n well and p well are formed, and a transistor or the like is formed to complete a semiconductor device.
따라서, 본 발명은 세정과정과 식각공정으로 트렌치 매립용 절연물질의 과도식각이 방지되어 후속공정에서의 평탄화 불량, 졍션 누설전류의 증가, 상부 모서리에서의 필드 크라우딩 효과(field crowding effect), 붕소의 세그리게이션(segregation)에 의한 내로우 위쓰 효과의 증가, 서브문턱 험프의 생성 그리고 게이트산화막의 신뢰성 저하 등의 반도체 소자에 치명적인 불량을 발생시키는 문제점을 해결하는 장점이 있다.Therefore, the present invention prevents excessive etching of the trench filling insulating material by the cleaning process and the etching process, so that the planarization failure in the subsequent process, the increase of the leakage leakage current, the field crowding effect at the upper edge, boron There is an advantage to solve the problem of causing a fatal defect in the semiconductor device, such as the increase in the narrow whistle effect due to the segmentation, the generation of sub-threshold humps, and the reliability of the gate oxide film.
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